Designing Single-Switch

Forward Converters
By Suresh Hariharan, Senior Corporate Applications
Engineer, and David Schie, Director of IC Design, Maxim
Integrated Products Inc., Sunnyvale, Calif.
Often used in dc-dc converter modules for power
levels below 100 W, single-transistor, resonantreset forward converters are also useful for dc-dc
converters with adjustable output voltages.

mong power-converter topologies, the

single-transistor forward converter is one
of the most common for power levels below
100 W. This article, however, focuses on the
improvements to the circuit known as the
single-transistor, resonant-reset forward converter, which
eliminates the reset winding and a diode (DTR) while
offering several other advantages.
Its duty cycle can exceed 50%, making it suitable for
low-cost dc-dc converters that operate from a wide range of
input voltages and deliver widely varying outputs. The absence
of a reset winding reduces costs by simplifying the transformer,
especially for the planar transformers widely used in
high-density dc-dc converter modules. Finally, the resonantreset circuits sinusoidal reset voltage reduces EMI.
To properly appreciate the resonant-reset topology,
we must rst understand the conventional single-switch
forward converter (Fig. 1). When switch Q1 turns on, the
transformer current rises from zero and the diode DTR is
reverse biased. Transformer magnetizing current builds up
to a value IM=VINTON/LM, where TON is the on time per
switching cycle and LM is the magnetizing inductance.
During the switchs on period, the load current I O is
DR

VIN

LO

reected in the primary as IP=IONS/NP, where NS is the

number of secondary turns and NP is the number of primary
turns. Output voltage is VO=VINDNS/NP, where D=TON/
TS and 1/TS is the switching frequency. Magnetizing current
in the transformer primary just before turnoff is VINTON/
LM. When Q1 turns off, the transformer voltage tends to
reverse. Voltage on the DTR cathode keeps decreasing until
DTR turns on.
For typical applications, the NP/NR turns ratio is 1, where
NR is the number of turns in the primary reset winding.
The transformer magnetizing current now decreases from
IM to zero. When it reaches zero, the transformer is fully
reset and voltage across the transformer remains at zero
until the start of the next switching cycle. The maximum
duty cycle (DMAX) in these applications is limited to 50%.
On the other hand, single-switch, resonant-reset forward
converters (Fig. 1) are characterized by the absence of a
reset winding. During the off time, the transformer resets
(without loss) through a resonant circuit consisting of the
magnetizing inductance and the combined capacitance
of the switch (CS), primary winding (CP) and all reected
secondary capacitances (CRS), including the rectifyingdiode capacitance.

Description of
Operation

IO
VO

VIN

IO

As su m p t i on s a re
made in the following
circuit analysis:
C IN
CO
The circuit has
DR
CD
CIN
reached steady-state
operation.
D
D
Q1
Q1
L and C (fairly
O
O
CS
DTR
large) can be considered
G
innite.
S
G
S
Leakage induc(a)
(b)
tance is neglected.
Fig. 1. A conventional single-transistor forward converter (a). A single-switch, resonant-reset forward converter (b).
Drops due to the
TR

DF

Power Electronics Technology October 2005

CO

LO

TR

VO

C P CRS

38

www.powerelectronics.com

FORWARD CONVERTERS
diode and switch on-resistance are neglected.
Steady-state operation for the circuit comprises three
intervals in each switching cycle:
Interval 1. Initially, t=0 and Q1 is on (Fig. 2a). The
transformer is magnetized with a ramp current during this
interval, dened as TON. Secondary current ows through
VIN

IP
+

IS
I MAG

CIN

VDS
+ DF

NS

NP

CO

VIN

TON

I MAG

D
CD
G

I2 = I1 +

IO

LO

IR

LM

the secondary diode DR, and the voltage across capacitance

CD is approximately zero. CD includes the internal diode
capacitance and the external capacitance added across diode
DR. The primary magnetizing current has a value of I1 at the
start of this interval and I2 at the end of the interval:

DR

I2
T=O

TON

I1

(a)
VIN

IO

LO

IP

+
CR

C IN

CT
NP

DF
+

NS

CO

+
O
T

I MAG

D
CD

G
SC

L M / CR

VIN

I MAG
LM

VIN + I 2

VDS

I R IS

DR

I2
T=O

I1=-I2

TON

TR

(b)
VIN

IP = 0

IS

V IN + I 2 L M / C R

VDS
I MAG

CIN

IO

LO

LM

DF
+

NS

NP

CO

VIN

(Eq. 1)
The primary current IP
is the sum of the reected
current IR (equal to IONS/
NP) and the primary
magnetizing current IMAG.
In t e r v a l 2 . Wh e n t h e
switch is turned off, the
switch Q1 drain-to-source
voltage beg ins to r ise
(Fig. 2b). When that voltage
exceeds V IN , the polarity
a c ro s s t h e s e co n d a r y
winding is reversed. Then the
secondary diode DR turns
off and the freewheeling
diode DF turns on. A
sinusoidal demagnetization
current star ts to flow
through the resonant circuit
formed by the parallel
combination of transformer
magnetizing inductance
L M and the capacitance
C R reflected across the
transformer primary. The
capacitance CR is the sum
of all capacitances across
the primary including the
reflected capacitance C D,
the internal plus external
capacitance across diode DR
(internal diode capacitance
of DR<<CD):
2

N
CR = CD S + CS + CT
N

O
I MAG

VIN TON
LM

(Eq. 2)
where CS is the primary
S
T=O
switch capacitance and CT
+

T
DR
is the transformer primary
I =-I
TON
TR
capacitance. Interval 2
TS
equals TON + TR, where TR
(c)
is one-half of a resonant
interval:
Fig. 2. From Fig. 1b, an equivalent circuit for the voltage on Q1 and the primary magnetizing-current
1
f RES =
waveform during Interval 1not to scale (a). From Fig. 1b, an equivalent circuit for the voltage on Q1 and the
2 L M C R
primary magnetizing-current waveform during Interval 2not to scale (b). From Fig. 1b, an equivalent circuit
G

CD

I2

for the voltage on Q1 and the primary magnetizing-current waveform during Interval 3not to scale (c).
www.powerelectronics.com

39

Power Electronics Technology October 2005

FORWARD CONVERTERS

ISENSE Circuit

Q9
4
CMLT3946E
CMLT3946E
PO368

C53
1000 pF
NDRV R49

Primary PWM
Control Circuit

T4

PWRAMP_TRNS 12
1 T5 PWRAMP_TRNS

R51
22

75
1N4148 W
D20

3
4

-48 VOUT

D23

19T

15T

10

6T

3T

1N4148 W

-48 VOUT

C64
0.1 FF

47 R53
Q11
Q1
1
Si3458DV

C56
220 pF
pF,, 100 V

4.7 F, 25 V

C59

22

C62

C55
2.2 nF
nF, 250 Vacc
-48 VOUT

Q1
Q15
INDS351AN

VCC

AN

/OUT
GND

-48 VOUT

CA

1
2

Secondary VSENSE and Feedback and Control

VRE
REFF

PS9121
R37

C61

SOURCEQ9
SOURCEQ

NDRV

C60

4.7 F, 25 V 4.7 F, 25 V 0.1 F, 16 V

U9

R59

D24 4.99 k
IN4148 W

15 R62

1N4148 W

Gate
Gat

R60
.47
REG5

VOUT

H
L4 47

D22

Q14
Q1
4
FQD4N25

-48 VOUT

R52
Si3440DV
22

D21

9
15T

Q10
Q1
0
C54

100 pF , 200 V

-48 VOUT

VIN

VCC

1N4148 W

C41
.1 F,
F, 16 V

C40

T3

0.1 F, 16 V
-48 VOUT

C42

0.1 F. 16 V
5

D17
B0520

Gate
R40
10 k

PAO184

Fig. 3. Resonant-reset forward converter with an input range of ground to 48 VOUT (36 V to 56 V) and output range 4 V to 18 V.

TR = L M C R

(Eq. 4)
The external capacitance CR charges from zero to a peak
value of:
L
I2 M
CR

is possible if L M C R > TR. In that case, a full half-cycle of

resonance has not been completed before the next switching
cycle begins, and therefore the voltage across the primary
switch exceeds VIN at the start of each switching cycle. That
condition increases the switching loss.

during this interval, and then discharges back to zero.

The magnetizing current I1 at the end of the interval should
therefore equal I2. The drain-to-source voltage (VDS) on
the primary switch Q1 at the end of this interval is VIN, but
reaches a peak of:
L M halfway through Interval 2.
VIN + I2
C

Transient Operation
Transient stresses on the primary switch and secondary
output diodes can vary greatly depending on the type of
controller used in the application. If the design is not optimal,
transients can cause failure in the primary switches or the
secondary diodes.
Consider operation with a current-mode PWM
controller. Initially, the power supply operates at no-load
and high-line voltage. A load transient is applied (minimum
load to full load), which causes an immediate duty-cycle step
to maximum duty cycle. In turn, that event causes a large
increase in the transformers magnetizing current and may
saturate the transformer unless its design accounted for such
transients. The resonant-reset voltage is much higher than
that during steady-state operation and may cause failure in
the forward diode or the primary switch.
To combat this problem, we introduce a volt-sec clamp.
Consider the controller above with a maximum duty-cycle
clamp that is inversely proportional to the input voltage.
That arrangement limits the maximum ux excursion along
the B-H loop of the transformer during a transient, which
allows the use of a smaller transformer. Transient-voltage
stress on the forward diode and the primary switch is

Interval 3. During this interval, diodes DR and DF are

both on, and the primary switch is off (Fig. 2c). Voltage
across the transformer primary is held to zero by the reected
virtual short across diode DF, and the magnetizing current
is held to -I2 for the entire interval. The end of Interval 3
denes the end of a switching cycle, and because the circuit
is at steady state, the current I1 equals -I2. Substituting for I1
in Eq. 1, we see that the primary magnetizing current at the
start of each switching cycle is:
I1 =

(VIN TON )
2 LM

(Eq. 5)

During the entirety of Interval 3, the voltage across the

transformer primary is held at 0 V, so the primary switch
voltage VDS remains at VIN. Note that at the end of TS, I2I1

Power Electronics Technology October 2005

40

www.powerelectronics.com

FORWARD CONVERTERS
signicantly less, but is still higher than during steady-state
operation.
Now consider the operation of this converter type with
a very light load using diodes for rectication. Magnetizing
current is very close to zero during this mode of operation,
and the duty cycle is low. If we now apply a load transient
(from no load to full load), the duty cycle immediately
increases to the maximum value allowed by the adaptive
duty-cycle clamp. Before application of the transient, the
magnetizing current is zero. The transient peak duty cycle
at high-line voltage is:

duty cycle, controlling any buildup of magnetizing energy

while alleviating voltage stress.

Design Example
The working power supply of Fig. 3 accepts dc input
voltages in the range 36 V to 56 V, and produces an isolated
variable output voltage in the range of 4 V to 18 V, controlled
by an adjustable external reference. The maximum output
current is 0.4 A and the switching frequency is 500 kHz.
The resonant-reset forward converter is most suitable for
this design because it lets us maximize the duty cycle. That
capability is necessary if the output voltage is to be properly
controlled from high levels all the way down to 4 V. Otherwise,
the PWM controllers minimum on time is a limitation that
could introduce problems. Synchronous rectiers should
be included to maximize efciency and enable the PWM
controller to control the output voltage down to 4 V at
light loads. The current-mode PWM controller shown also
includes an adaptive volt-sec clamp.
Because the power supply must turn on at 36 V and
provide full power at 36 V, we set its turn-on point at 34.2
V. That value of turn-on voltage includes a 5% margin to
compensate for component tolerances. We then set the
maximum duty cycle corresponding to the turn-on point
(set by the adaptive duty cycle) at 75%. That leaves 25% of

VIN min DMAXtr

VIN max
where VINmin is the low-line input voltage, DMAXtr is the
maximum duty cycle at low-line voltage set by the adaptive
duty-cycle clamp, and VINmax is the input voltage at high-line
voltage. When a transient occurs, the magnetizing current
increases from zero to:
VIN min DMAXtr
L M fS
in the rst switch-on cycle after the transient, where LM is
the primary magnetizing inductance and fS is the switching
frequency. After the switch turns off, the magnetizing current
reverses in a sinusoidal fashion set by the magnetizing
inductance LM and capacitance CR. Peak voltage on the
switch is:
V
DMAXtr L M
VP max TR = VIN max + IN min
(Eq. 6)
L M fS
CR
For steady-state operation at full-load and high-line
voltage, the peak steady-state voltage on the switch is:
VP max S = VIN max +

VIN min DMAXs

2 L M fS

LM
CR

(Eq. 7)

where DMAXs is the steady-state duty cycle at full load and

low line. In practical applications, we try to set DMAXtr slightly
higher than DMAXs. We also see that the peak transient reverse
voltage on the diode DF is more than twice as high as the
peak steady-state reverse voltage with this type of pulsewidth modulated (PWM) controller. For PWM controllers
without the volt-sec clamp, the transient voltage can be
even higher.
If the circuit includes synchronous rectiers, the inductor
current does not become discontinuous, and the magnetizing
currents at light load and at full load are almost the same.
For PWM current-mode controllers with volt-sec clamps,
the transient-voltage stress on the primary switch and the
secondary diode DF is closer to the peak steady-state voltage
stress.
The behavior of voltage-mode controllers is similar to
that of current-mode PWM controllers. Again, the use of an
adaptive volt-sec clamp can reduce stress. These converter
types often include a duty-cycle soft-start that ramps up the

www.powerelectronics.com

41

Power Electronics Technology October 2005

FORWARD CONVERTERS

Fig. 4. From Fig. 3, VDS on Q14 at an input of 48 Vdc, with output voltage at 4 V (a) and at 8 V (b).

the switching time available for resetting the transformer at

the converters lowest operating voltage.
At the lowest operating voltage, the maximum-available
reset time for the transformer is:
TR =

(1 DMA
MAX
X)
fS

is 11 pF. Based on the available reset time, the maximum

allowable primary capacitance is 176 pF. That value allows
a maximum of 165 pF for the sum of switch capacitance
and reected diode capacitance (CR). Because MOSFET
capacitance is not easily determined, we must build the
circuit and adjust the value of added capacitance across the
synchronous MOSFET (QR) to get the appropriate reset
time. In the actual power supply, the added capacitance across
MOSFET QR is 100 pF.
The output inductor and capacitor are chosen to optimize
efciency and ensure compliance with the output-ripple
specication. Thus, the inductor value is 47 H, and CO is
formed by connecting three ceramic capacitors in parallel,
each rated 4.7 F and 25 V.
For the primary MOSFET Q1 (voltage rating of 250 V),
we choose an FQD4N25 from Fairchild Semiconductor
(South Portland, Maine) for its low inherent capacitance
and low on-resistance. This MOSFET also minimizes the
gate-drive loss, conduction loss and switching loss.
Peak stress on the synchronous rectier QR is:

(Eq. 8)

where D MAX =0.75 and f S =510 5 . These values yield

a reset time of 0.5 s. To minimize switching loss, the
magnetizing current should complete one half-cycle of
sinusoidal resonant ringing as given by Eq. 4. Therefore,
L M C R = 0.5 10 6 sec , and the peak steady-state voltage
stress on the primary switch (obtained by substituting values
in Eq. 7) is 217.2 V. Thus, for this design we choose a switch
rated at 250 V.
Primary-to-secondary turns ratio for the transformer is:
n

VIN min DMAX

MA
VOUT

(Eq. 9)

We choose a transformer with an EFD15 core of 3F3

material, and obtain n 1.35 by substituting values in
Eq. 9. The actual primary turns (30) and secondary turns
(24) yield a turns ratio of 1.25. The magnetizing inductance
for this transformer, wound using ungapped cores, is 702
H 25%. Tolerance in the magnetizing inductance could
produce a tolerance of (+11%)/(13.4%) in the transformers
self-resonant frequency, not accounting for tolerance in the
total capacitance appearing across the primary in the actual
circuit. The measured self-resonant frequency of a sample
transformer was lower than 1 MHz.
We must guarantee that the actual circuits demagnetizing
self-resonant frequency is higher than fS/(1-DMAX). We
therefore gap the core, both to reduce the transformers
measured self-resonant frequency and to reduce the variation in
magnetizing inductance. Using a gapped core with Al tolerance
of 10% yields a magnetizing inductance of 144 H.
The self-resonant frequency measured for the new transformer sample is 4 MHz, and the transformer capacitance
calculated from the expression for self-resonant frequency
Power Electronics Technology October 2005

VQR

DMA
MAX
X VIN min
2 n A (1 DMAX
MAX )

(Eq. 10)

where nA is the power transformers actual primary-tosecondary turns ratio. In this case, nA is 1.25 and the calculated
value of VQR is 122 V. Therefore, we choose a 150-V MOSFET
for QR. The peak voltage stress on the freewheeling MOSFET
QF is:
VQF

VIN max
nA

(Eq. 11)

where nA is 1.25 and VINmax is 56 V. The calculated value is

44.8 V, so for QF we choose a MOSFET rated at 60 V. (The
control circuit and synchronous MOSFET drives are shown
in Fig. 3 but not discussed further.)

Experimental Results
Figs. 4 and 5 show voltage waveforms on the primary
MOSFET of Fig. 3 at different input voltages and various
42

www.powerelectronics.com

FORWARD CONVERTERS

Fig. 5. From Fig. 3, output voltage at 18 V, with VDS on Q14 at an input of 36 Vdc (a) and 56 Vdc (b).

output voltages, with an output load of 400 mA. The

drain-voltage waveforms clearly show that the resonantreset voltage does not vary with line voltage, but is
proportional to the output voltage. Peak voltage on the
primary MOSFET is equal to the input voltage plus the
resonant-reset voltage.
We conclude that resonant-reset forward converters are
quite suitable for power supplies operating from wide-range

dc-voltage inputs. They also are suitable for applications

requiring a wide range of adjustable output voltage. In
designing resonant-reset forward converters, you should
take care to minimize the stress of transient voltages on
the devices (the use of synchronous rectication reduces
transient-voltage stress on the power semiconductors).
For optimum performance, you also should choose an
appropriate controller.
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43

Power Electronics Technology October 2005