2 bit multiplier

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity twobitmultiplier is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC_VECTOR (3 downto 0));
end twobitmultiplier;

architecture Behavioral of twobitmultiplier is

component and1 is
port(a,b: in std_logic;
z:out std_logic);
end component;
component h_add
Port ( a,b : in STD_LOGIC;
z,c : out STD_LOGIC);
end component;

signal s1,s2,s3,s4:std_logic;

begin
m1:and1 port map(a(0),b(0),z(0));
m2:and1 port map(a(0),b(1),s1);
m3:and1 port map(a(1),b(0),s2);

m4:and1 port map(a(1),b(1),s3);

m5:h_add port map(s3,s4,z(2),z(3));
m6:h_add port map(s1,s2,z(1),s4);

end Behavioral;

RTL SCHEMATIC

OUTPUT BEHAVORAL MODEL

8:3 PRIORITY DECODER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity priority_encoder is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : out STD_LOGIC_VECTOR (2 downto 0);
v : out STD_LOGIC);
end priority_enc;
architecture Behavioral of priority_enc is
begin
process(a)
begin
if (a(7)='1') then
b <="111" ;
v<='1';
elsif (a(6)='1') then
b<="110";
v<='1';
elsif (a(5)='1') then
b<="101";
v<='1';
elsif (a(4)='1') then
b<="100";
v<='1';
elsif (a(3)='1') then
b<="011";

v<='1';
elsif (a(2)='1') then
b<="010";
v<='1';
elsif (a(1)='1') then
b<="001";
v<='1';
elsif (a(0)='1') then
b<="000";
v<='1';
end if;
end process;
end Behavioral;

RTL SCHEMATIC

OUTPUT BEHAVORAL MODEL

4 bit adder/substractor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC_vector (3 downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC);
end adder;
architecture Behavioral of adder is
component f_add
Port ( a,b,c : in STD_LOGIC;
z,c0 : out STD_LOGIC);
end component;
component xor1 is
port ( a,b : in STD_LOGIC;
z: out STD_LOGIC);
end component;
signal s1,s2,s3,s4,s5,s6,s7:std_logic;
begin
m1:xor1 port map(b(0),cin,s1);
m2:xor1 port map(b(1),cin,s2);
m3:xor1 port map(b(2),cin,s3);
m4:xor1 port map(b(3),cin,s4);
m5:f_add port map(s1,a(0),cin,z(0),s5);
m6:f_add port map(s2,a(1),s5,z(1),s6);

m7:f_add port map(s3,a(2),s6,z(2),s7);

m8:f_add port map(s4,a(3),s7,z(3),cout);
end Behavioral;

RTL SCHEMATIC

OUTPUT BEHAVORAL MODEL

16:1 MUX using 4:1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux16_1 is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
o : out STD_LOGIC;
s : in STD_LOGIC_VECTOR (3 downto 0));
end mux16_1;

architecture Behavioral of mux16_1 is

component m_41
port ( a,b,c,d : in STD_LOGIC;
s1,s2 : in STD_LOGIC;
z : out STD_LOGIC);
end component;
signal s1,s2,s3,s4: std_logic;
begin
m1:m_41 port map (a(0),a(1),a(2),a(3),s(0),s(1),s1);
m2:m_41 port map (a(4),a(5),a(6),a(7),s(0),s(1),s2);
m3:m_41 port map (a(8),a(9),a(10),a(11),s(0),s(1),s3);
m4:m_41 port map (a(12),a(13),a(14),a(15),s(0),s(1),s4);
m5:m_41 port map (s1,s2,s3,s4,s(2),s(3),o);

end Behavioral;

RTL SCHEMATIC

OUTPUT BEHAVORAL MODEL

16:1 MUX using 2:1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity m_16_1 is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
o : out STD_LOGIC;
s : in STD_LOGIC_VECTOR (3 downto 0));
end m_16_1;

architecture Behavioral of m_16_1 is

component mux_21 is
Port ( a,b,s : in STD_LOGIC;
z : out STD_LOGIC);
end component;
signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14: std_logic;
begin
m1:mux_21 port map (a(0),a(1),s(0),s1);
m2:mux_21 port map (a(2),a(3),s(0),s2);
m3:mux_21 port map (a(4),a(5),s(0),s3);
m4:mux_21 port map (a(6),a(7),s(0),s4);
m5:mux_21 port map (a(8),a(9),s(0),s5);
m6:mux_21 port map (a(10),a(11),s(0),s6);
m7:mux_21 port map (a(12),a(13),s(0),s7);
m8:mux_21 port map (a(14),a(15),s(0),s8);
m9:mux_21 port map (s1,s2,s(1),s9);
m10:mux_21 port map (s3,s4,s(1),s10);

m11:mux_21 port map (s5,s6,s(1),s11);

m12:mux_21 port map (s7,s8,s(1),s12);
m13:mux_21 port map (s9,s10,s(2),s13);
m14:mux_21 port map (s11,s12,s(2),s14);
m15:mux_21 port map (s13,s14,s(3),o);

end Behavioral;

RTL SCHEMATIC

OUTPUT BEHAVORAL MODEL

2:1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_21 is
Port ( a,b,s : in STD_LOGIC;
z : out STD_LOGIC);
end mux_21;

architecture Behavioral of mux_21 is

begin
process(a,b,s)

begin
if (s='0') then
z<=a;
else
z<=b;
end if;
end process;

end Behavioral;