ISSN 1392-1215 ELEKTRONIKA IR ELEKTROTECHNIKA. 1996. Nr.(1)8. Bipolar Transistor Voltage Breakdown Simulation D. Baranauskas, A. Marcinkevicius Radio Equipment Department Vilnius Technical University Problem Cireuits can sometimes be subjected to much treater voltage than nominal (car starter on/off tran- sient, lighting, power stabilizer damage). This leads to voltage overload and consequent transistor damage. One solution is to choose all transistors with collee- tor-emitter breakdown voltage (BViyo) higher than ever possible overvoltage. This leads to low price sacrificing and other cireuit parameter deterioration Breakdown voltage of a circuit depends on its configuration, breakdown voltages of transistors used and their operation mode. Proper design and choice of the transistor operation mode can increase cireuit immunity to voltage overload without using high voltage transistors. Breakdown voltage "keeping in mind* popular among designers is not a solution because it can easily lead to "slipping from the mind” Appropriate simulation means are necessary, but PSpice built-in transistor model does not take into account voltage breakdown phenomena. ‘Voltage breakdown phenome1 Voltage breakdown is initiated by avalanche carrier multiplication that starts in base-collector junction when collector-emitter voltage approaches fan appropriate value, Collector current increases, transistor output characteristics roll up and can cause device damage if no current limit is present. Collector current increase is caused by generated current that fenters base region, makes sum with base drive current and is multiplied by current transfer ratio Cig). So, voltage breakdown can be simulated by adding a current source in parallel with collector-base junction. The source must be controlled according to ‘1 mathematical model, depending on collector-emit- ter voltage and collector current and must include parameters specifying particular transistor behaviour. Mathematical model (One of the most accurate models for avalanche current I, is described in [1]: ag Vg 1g dn Yast Vee ci z in IP 60 ems. +¥.9)" w [5 is the collector current without avalanche (initial), ct, and b,, are coefficients (for n-p-n tran- a, =705x10%m™ and by = 1.23 10° Vjem). Vie is diffusion voltage, P. is junction gra- ding coefficient, AVL is avalanche parameter. Vy is internal base-collector voltage (excluding voltage drop in epilayer): sistors @ Regi aoeuracy has no significant effect on dis- creet general purpose transistors, so, we assume Rei = RC, where RC is builtin transistor model parameter for collector ohmic resistance. Vi. and P, are calculated using measured de pendence of transistor collector-base depletion capa- citance on collector-base voltage using methodology presented in [1]. Then, AVL. is calculated or extrac- ted from (1) using measured 1,(V,) data ‘Avalanche current temperature dependence is realised making AVL temperature dependent: AVI{T) = AVL(Ty) * 1+ Ly(P-Ty) + La(T Toy ] G3) where Ly =72%10 and Ly =—16 x10" [1] Mathematical model accuracy simulating collee- tor-emitter breakdown voltage, validity and restric- tions are discussed in [1]. Macromodel realisation Complete subeircuit of transistor macro model according to mathematical model described above is Fig. 1. Transistor macromodel subeireuitpresented in Fig. 1. The macromodel has B, C and E rhodes like an ordinary transistor. Avalanche multi plication current 1, is formed by controlled current source G connected in parallel with Q1 base-collector junction. J; is obtained by using Q2 with the same model parameters as Q1 but without avalanche multi plication taken into account. VB is used to obtain Ti. ‘The controlled current source GB ensures Ing = Toys and E2 ensures Vog2 =Voni- So. (VC =[,;. The controlled current source GPS forms current equivalent to dissipated power in Ql (1A= =1W). RT is equivalent to transistor thermal resis- tance. So, voltage at node TPS represents the rise of device temperature due to power dissipation. RI and TT form voltage equivalent to simulation tempera- ture change from TNOM. This is performed making the use of resistor model definition: R= Rox NOM. 147C,(T-Tp) +1C2(T-T)?] : where Ty When Ry =To, TC =1/Ty, TC, =0 and Ig=1A, than Vp =T'. So, voltage at node TJA is equivalent to junction temperature, AVL(T) is performed as voltage at node AVL provided by E3 according to (3). R3 is connected to avoid floating node. If [, is shunted by short circuiting base-emitter junction, according to the mathematical model, tran- sistor breakdown voltage would approach. infinity. ‘While in reality, breakdown takes place when collee- tor-emitter voltage approaches collector-base break- down voltage ( BV,,). Zener diode D is connected in parallel with QI collector-emitter nodes to enable BV.» simulation. Macromodel verification Standard 2N2222A transistor was used 10 verily the macromodel and compare simulation accuracy with the builtin transistor model. Model parameters ‘were obtained using extraction technique described in [1]. AS the model is based on empirically defined correlation between collector-base depletion capaci- tance and J, dependence on Vi, extracted parame- ter values were optimised manually to obtain better experimental and simulated data fitting, Higher value of P, was chosen when simulated curve roll up in the avalanche region had been more sharp than mea- sured, otherwise - lower. Using the new P. value, ‘AVITo) was redefined according to (1) and the fitting verified. The process was repeated till satisfied results were obtained. So, P, and AVL(Ty) parame- ter values are not in the ranges as described in [1]. ‘Avalanche model parameters obtained: Vj. =0.69¥’, P.=001, AVE(Tp)= 40329. (Tp =27°C). Some, ee Ota ree ete rete ete eects eects ets ess eee ees eee eee ese rece ce ce eee standard Goomel-Poon model parameters of 2N2222A were made more exact to enable simulation ‘and experimental data comparison ‘The reverse bias of transistor base-collector junction was used to measure Zener diode parame- ters and PARTS software used to extract model parameters for BV. simulation. Subcireuit macromodel definition, extracted pa- rameters as well as transistor and Zener diode para- meters are presented in Fig. 2. T-(Pae) characteristics simulated using the built- in transistor model and the proposed macromodel are presented in Fig. 3. [-(Ve) characteristic simula- ted using proposed macromodel does not differ from that using the built-in model at low Vee. The diffe- rence is evident starting at about 35V, when ava- lanche carrier multiplication starts to be significant. Measurement data are close to the curve simulated using the proposed macromodel 1.(Vse) characteristics, when base-emitter june- tion is short circuited, are presented in Fig. 4, Simulated curves do not differ at collector-emiter Voltages below BY,. When colleetor-base break- down voltage is approached, the curves’ separation is essential, Measurement data points are very close to simulated curve when the proposed macromodel is used Macromodel merit is demonstrated by simula tion of voltage breakdown protected smart transistor circuit. Simulation of the circuit functioning without ‘macromodel usage would be impossible at al Transistor collector-emitter voltage breakdown increase requires technological process sophistication and some other transistor parameter like Moy, deterioration. The increase of component reliability demand, and the cost decrease of extra component oon an IC chip suggest circuit design methods to be used, Collector-emitter breakdown voltage can be increased up to about collector-base breakdown voltage by transistor connection in common base ‘mode or cascode. The first method limits transistor current transfer coefficient to less than 1 while the other is distinguished for high saturation voltage. ‘Another approach is based on transistor base-emitter junction short circuiting when collector-emitter voltage exceeds some marginal value, The margin is usually set by using a Zener diode. The variation of breakdown voltage between transistors formed on IC chip does not correlate with the variation of Zener diode breakdown voltage. To ensure reliability, protection must tur itself ON when collector-emitter voltage is well below breakdown value. These do notallow transistor to be operated in the full region of [2]. Transistor protection turn ON is determined by ollector-emitter voltages specified by the safe opera- voltage breakdown sensor. The sensor and transistor tion area of a particular device. under protection are made on the same chip and Voltage breakdown simulation enabled an have the same structure. invention of a new approach to transistor protection (SUBCKT OF © BE 7h [-ro=27 3 AVL 0. VALUE=(AVLTO* (1451* (V(TJA)-TO) +L2*PWR( (V(TIA)-TO) ,2)) | 3 AVL 0 10k (0 BI VALUB=(I(Vc) *an* (Vac+(V(C,B)-T(VC) *REPI) } / (bn* (1-Pc) }* exp (-V (AVL) *PUR ( (Vde+ (V(C, B) ~(I(VC) *REPI) }}, (Pe“1)) )) PS 0 TPS VALUE=(V(C,E)*I(VC) | T TPS 0 150 TPS TIA Ri 27 [MODEL R1 RES ( ltt TPs TIA 1 vB BBL O 2 C2 B2 OL jo1 020 2 1 10 VALUE=(V(C,E)} Cc BIEL 3B B2 0 VALUE=(-I(VB)} loon = c DoL |MODEL L NPN(Is=676B-18 Xti-3 Egel.11 Vaf~60 Bi=128.6 Tk£=10 Nkel Xt) Tsc-676E-18 Nc=2 Ikr=0 Re=1 Cjo=19.43p Mjc=.3333 Vi 15 Cje=29.64p Mje=.3333 Vje=.75 Tr=467.3n f=453.1p Itfe1 Xt! 01) MODEL DOL D(Is<10£ Nel Re=.1 Tkf=0 Xti=3 Eg-l.11 cjom0 M-.3333 |, vj=.75 Fo=.5 Isr=100p Nr=2 Bv=120.1 Ibv=17.24m Tt=10E-21) 733 ENDS) 334 proposed ‘macromodel Fig. 3. [,(Voe) characteristics simulated using built-in transistor model and proposed macromodelona So, both transistors have the same breakdown voltage. Such sensor usage requires. however a spe- cial circuit for sensor bias. The breakdown sensor Q3 (Fig. 5.) is biased so that voltage drop across R2 is not enough for Q2 to be turned ON when avalanche carrier multiplication does not present. Ql oppera- tion is not affected by protection circuitry. When avalanche multiplication starts taking place in Ql and Q3, voltage drop across R2 increases and turns Q2 ON. Q2 short circuits base-emitter junction of QL and shunts avalanche current. Q6 is also turned ON protecting the sensor Q3. Q6 emitter current makes sum with that of Q3 and makes higher voltage drop across R2, and Q2 keeps QI OFF independently on its drive current. Voltage drop across RI and R2 ‘equals to about 2Vj~. and is small as compared to breakdown voltage and has no significant effect on the protection turn ON margin. If breakdown voltage of transistors used is low, more sophisticated circuitry Breakdown ‘Transistor under protection Bar Fig. 5. Vollage breakdown protected smart transistor circuit 2N22224, 89 -meusurement proposed macromodel built-in model BVeb ~P Vow Fig. 4. Simulated [,(Vz-) curves, when base-emitter junction is short circuited ‘must be used to minimize the difference between 03 and QI collector-emitter voltages. As transistor current transfer coefficient varies between devices, 10 ensure stable initial Q3 emitter current and voltage drop across R2 not to vary, Ql bias current must vary depending on current transfer coefficient. So Q3 bias current is formed by a Particular circuit. The current source Ire is connected in emitter circuit of Q8, then its base current: Tg = Teg (1+ Fate) Q4, Q5, QT form high output impedance current mirror. So: Ip, =I and Ie, = = Ing. when no avalanche takes place, Q2, 4, Q6- 8 need no protection because collector-emitter voltages are low. The transistor Q5 must have lateral strueture to prevent its breakdown, ‘Smart transistor output characteristics simulated using proposed macromodel are presented in Fig. 6 ‘The smart transistor acts as an ordinary transistor til collector-emitter voltage comes into the avalanche multiplication region and curves start to roll up that causes the protection turn ON. Q6 starts to, bypass Q7 drive current, curves sharply roll down, and collector current switches OFF. Remaining about LOOWA current is due to protection cireuit bias. This state lasts till collector-base breakdown voltage is reached (about 120V). Smart transistor circuit component values were used: Ry =6k, Ry =10k, Teer = 204A - ‘Smart transistor circuit was assembled and simu- lation results were verified by measurements. Q1 and QB were chosen with identical BV, and BV, Q3 and Q8 - with identical faye. This is automatically satisfied in ease of circuit implementation on a single chip. Besides, QI emitter area can be much greater 6Fig. 6 Simulated smart transistor [, versus gg curves than that of Q3 to increase power dissipation capability of the smart transistor and lower Q3 bias current, QI layout can be designed to exclude sharp corners. This will make the protection more reliable. Conclusion ‘The importance of bipolar transistor voltage breakdown simulation and a mathematical model of avalanche multiplication were discussed. PSpice mac- romodel was proposed for the voltage breakdown simulation. Base-collector junction breakdown was taken into account by including a Zener diode. Macromodel definition in terms of PSpice input language was presented and parameter extraction was discussed. Macromodel accuracy was verified by simulating output characteristics of 2N2222A tran- sistor. A voltage protected smart transistor cireuit was presented as an example of a class of circuits - voltage 4) breakdown simulation was a key to design. The circuit enables smart transistor self protection against collector-emitter voltage breakdown and allows ope- ration in full collector-emitter voltage range specified by the safe operation area. Output characteristics of the smart transistor are simulated using proposed macromodel, good agreement with measurements ‘was obtained, References 1. Kloosterman W. J, DE Graaff H.C. Avalanche Maltiplication in a Compact Bipolar Transistor Model for Circuit Simulation // IEEE Transactions on Elec- tron Devices. - Vol. ED-36. 1989. -P.1376-1380. Deseription of Invention: SU No. 1582264. - Device for ‘Transistor Protection Against Overvoltage ~ Authors: D.Baranauskas, VJuodvalkis, V.Wvanov. | } | | |