Q.

NO
1

Solution

Marks

for 4 and 20 are the same in all but the most-significant bit, we can decode
them jointly (0100). We can derive the control signal by decodes the
count value 4 (00100), 20 (10100) and 24 (11000).
2

module debouncer ( output reg pb_debounced,

input pb,
input clk, reset );
reg [18:0] count500000; // values are in the range
// 0 to 499999
wire clk_100 Hz;
reg pb_sampled;
always @(posedge clk or posedge reset)
if (reset) count500000 <= 499999;
else if (clk_100Hz) count500000 <= 499999;
else count500000 <= count500000 1;
assign clk_100Hz = count500000 == 499999;
always @(posedge clk)
if (clk_100Hz) begin
if (pb == pb_sampled) pb_debounced <= pb;
pb_sampled <= pb;
end
endmodule

10EC666 DSD Using Verilog

test 2-Scheme of valuation

Q.NO
3

Solution

Marks

Wide memory: Sufficient memory chips are used so that an entire cache line
can be accessed at once. The line can then be transferred back to the cache on
a wide bus in one clock cycle, or over a narrower bus in several clock cycles.
Burst transfers: The CPU issues the first address of a line to be accessed in
memory. The memory then performs a sequence of accesses at successive
locations, starting from the first address. This technique obviates the time
required to transfer the address for locations other than the first.
Pipelining: The memory system is organized as a pipeline so that steps of
different memory operations can be overlapped. For example, the pipeline
steps might be address transfer, memory access, and returning read data to the
CPU. Thus, the memory system could have three memory operations in
progress concurrently, with one operation completed per clock cycle.
Double data rate (DDR) operation: Rather than transferring data items only
on rising clock edges, data can be transferred on both rising and falling clock
edges. This doubles the rate at which data is transferred, hence the name.

Q.NO
5

Solution

; Program to determine greater of value_1 and value_2

Text
org 0x000 ; start here on reset
jmp main
; Data memory layout
data
value_1: byte 10
value_2: byte 20
result: bss 1
; Main program
text
org 0x010
main: ldm r1, value_1
; load values
ldm r2, value_2
sub r0, r1, r2
; compare values
bc value_2_greater
stm r1, result
; value_1 is greater
jmp finish
value_2_greater: stm r2, result
; value_2 is greater
finish: jmp finish
; idle loop

Mark
s