ALU Module

alu.v

96/01/24
23:21:17
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alu:

The ALU module.

It executes the instructions.
Parameter List:
clk:
the clock (input)
opA:
instruction operand (input)
opB:
instruction operand (input)
aluOp: the ALU control signals (input)
result: the instruction result (output)
Author: Nestoras Tzartzanis
Date:
1/25/96
EE577b Verilog Example

//
Include definition of the control signals
include
"control.h"
module alu (clk, opA, opB, aluOp, result);
input
input
input
output

[7:0]
[1:0]
[7:0]

clk;
opA, opB;
aluOp;
result;

//
reg

The outputs are defined as registers too

[7:0]
result;

//
Definition of the ALU latency time
parameter
aluDelay = 85;
always @(posedge clk)
#aluDelay
//
.

A case-statement is used for the ALU implementation

// Check the control signal

casez (aluOp)
aluMv:
// The instruction is a move
result = opA;
aluAdd:
// The instruction is an add
result = opA + opB;
aluXor:
// The instruction is a xor
result = opA ^ opB;
endcase
endmodule