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  • Verilog-HDL: "Our Actions Inspires To "

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    Karthik Vk
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    This document outlines an advanced digital design workshop that will teach Verilog-HDL. The objectives are to provide an in-depth understanding of logic and system design and apply that knowledge to designing advanced digital hardware systems. Students will learn to design and optimize combinational and sequential circuits, model circuits in Verilog at different levels, develop test benches, and complete experiments modeling combinational and sequential circuits like adders, flip-flops and finite state machines.

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    Verilog Hdl

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    This document outlines an advanced digital design workshop that will teach Verilog-HDL. The objectives are to provide an in-depth understanding of logic and system design and apply that knowledge to designing advanced digital hardware systems. Students will learn to design and optimize combinational and sequential circuits, model circuits in Verilog at different levels, develop test benches, and complete experiments modeling combinational and sequential circuits like adders, flip-flops and finite state machines.

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    © All Rights Reserved
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    22 views3 pages

    Verilog-HDL: "Our Actions Inspires To "

    Uploaded by

    Karthik Vk
    This document outlines an advanced digital design workshop that will teach Verilog-HDL. The objectives are to provide an in-depth understanding of logic and system design and apply that knowledge to designing advanced digital hardware systems. Students will learn to design and optimize combinational and sequential circuits, model circuits in Verilog at different levels, develop test benches, and complete experiments modeling combinational and sequential circuits like adders, flip-flops and finite state machines.

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    © All Rights Reserved
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    of 3

    Verilog-HDL

    Workshop Agenda
    June 2014

    Strive For Excellence

    Our Actions inspires to dream


    more and more
    Go Green

    Advanced Digital Design with the


    Verilog-HDL
    Objectives:
    This course covers the advanced design and analysis of digital circuits with HDL.
    The primary goal is to provide in depth understanding of logic and system
    design. The course enables students to apply their knowledge for the design of
    advanced digital hardware systems.
    Expected Outcome:
    Upon successful completion of this course, students will be able to:
    1. Design and manually optimize complex combinational and sequential digital
    circuits
    2. Model combinational and sequential digital circuits by Verilog HDL
    3. Design and model digital circuits with Verilog HDL at behavioral, structural, and
    RTL Levels
    4. Develop test benches to simulate combinational and sequential circuits
    Theory:
    1.Lexical Conventions
    2.Ports and Modules
    3.Operators 4.Gate Level Modeling
    5. System Tasks&Compiler Directives
    6. Test Bench
    7.Data Flow Modeling
    8.Behavioral level Modeling
    9.Tasks&Functions.

    List of Experiments:
    Software : modelsim
    1.
    a.
    b.
    c.
    d.
    e.
    f.

    Design and Implementation of Combinational Circuits


    Basic Gates Using Dataflow, Structural, Behavioral Modeling
    Half-Adder and Full-Adder using structural Modeling
    Half-Subtractor and Full-Subtractor using dataflow modeling.
    Decoder and Encoder using case, casex and casez statements.
    Code Convertor & parity generators using reduction operators
    Multiplexer and De-multiplexer using nested if-else construct

    2. Design and Implementation of Sequential Circuits


    a. Flip-Flop using behavioral modeling
    b. Serial-In Serial Out, Parallel-In Parallel Out Shift register using Structural
    Modeling
    c. Serial-In Parallel Out, Parallel-In Serial Out Shift register using behavior level
    Modeling
    d. Ring Counter and Johnson counter using behavior level Modeling and
    structural level
    modeling.
    3.
    a.
    b.
    c.

    Design and Implementation of FSM


    Sequence detector using FSM
    Traffic Light Controller using FSM
    Vending machine problem using FS M

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