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  • Summary of Heteroepitaxial III-V-on-Si Integration Approaches (75) - Used With Permission From EHS, 2014

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    Vijay Vijju Saradhy
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    The document summarizes different approaches for integrating III-V semiconductor materials on silicon for photovoltaic applications. It lists the best path, merits, challenges, and reported efficiencies for each approach. The approaches include using graded buffer layers of GaAsP, SiGe, or strained layers for GaAs-on-Si integration as well as InGaN-on-Si, GaAsPN-on-Si, and direct GaAs-on-Si approaches. The challenges include lattice mismatch, material quality issues, and achieving high efficiency while allowing light to pass through to an underlying silicon solar cell. Demonstrated efficiencies range from 5.2% for two-junction GaAsPN//Si up to 27%

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    review of SOA III-V on Si

    Original Title

    Jain_N_D_2015

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    The document summarizes different approaches for integrating III-V semiconductor materials on silicon for photovoltaic applications. It lists the best path, merits, challenges, and reported efficiencies for each approach. The approaches include using graded buffer layers of GaAsP, SiGe, or strained layers for GaAs-on-Si integration as well as InGaN-on-Si, GaAsPN-on-Si, and direct GaAs-on-Si approaches. The challenges include lattice mismatch, material quality issues, and achieving high efficiency while allowing light to pass through to an underlying silicon solar cell. Demonstrated efficiencies range from 5.2% for two-junction GaAsPN//Si up to 27%

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    Summary of Heteroepitaxial III-V-on-Si Integration Approaches (75) - Used With Permission From EHS, 2014

    Uploaded by

    Vijay Vijju Saradhy
    The document summarizes different approaches for integrating III-V semiconductor materials on silicon for photovoltaic applications. It lists the best path, merits, challenges, and reported efficiencies for each approach. The approaches include using graded buffer layers of GaAsP, SiGe, or strained layers for GaAs-on-Si integration as well as InGaN-on-Si, GaAsPN-on-Si, and direct GaAs-on-Si approaches. The challenges include lattice mismatch, material quality issues, and achieving high efficiency while allowing light to pass through to an underlying silicon solar cell. Demonstrated efficiencies range from 5.2% for two-junction GaAsPN//Si up to 27%

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    TABLE II

    Summary of Heteroepitaxial III-V-on-Si Integration Approaches [75]. Used with permission from EHS, 2014.
    BEST
    PATH
    MERITS
    CHALLENGES
    EFFICIENCY

    GaAsP
    Graded
    Buffer

    SiGe Graded
    Buffer

    InGaN-on-Si

    GaAsPN-onSi

    Direct GaAson-Si

    Strainedlayers (SL)
    for GaAs-onSi

    Start with lattice-matched GaP layer


    GaP buffer could serve as a window
    layer for the bottom Si cell
    Possibility for no N- or Al-containing
    alloys
    Semi-transparent buffer for bottom Si
    cell

    Mixed anion As-P complex growth


    Thick graded buffer

    2J GaInP/GaAs 16.4% (AM1.5g)

    Low dislocation density


    Possibility to use Ge or SiGe as subcell

    Non-transparent buffer, ruling out


    bottom-Si cell
    Thick graded buffer
    Ge poses severe thermal-mismatch
    concern

    1J GaAs - 18.1%
    (AM1.5g) [13]
    &
    2J GaAsP/SiGe 18.9% (AM1.5g)

    InGaN material composition can span


    the entire useful solar spectrum
    Avoid the need for As, P or Al based
    materials
    Semi-transparent buffer for bottom Si
    cell

    Large lattice-mismatch between


    InGaN and Si
    Realization of In-rich InGaN bulk
    material (In>40%) challenging
    Difficulty in p-doping of In-rich
    InGaN layers
    Problem of phase separation in In-rich
    InGaN material and InN segregation.

    Only path for lattice-matched multijunction III-V solar cells to Si


    Transparent & relatively thinner buffers
    for bottom Si cell
    GaP buffer could serve as a window
    layer for the bottom Si cell

    Poor diffusion lengths in dilute nitride


    materials
    Challenging to control composition of
    quaternary alloys.

    Direct route for realizing record efficient


    dilute-nitride based lattice-matched 3J
    cells on GaAs substrate
    Path
    for
    conventional
    inverted
    metamorphic cells
    Semi-transparent buffer for bottom Si
    Lower dislocation density for SL
    approach

    High dislocation density


    Might use thick buffers to minimize
    dislocations in some cases
    Multiple thermal cycle anneals
    Growth could involves multiple
    super-lattice period
    Shutter sequence during switching
    could
    be
    challenging
    (eg
    InGaAs/GaAsP)

    27

    [14]

    [15]

    1J InGaN//Si
    heterostructure
    7.12% (AM1.5g)

    [22]

    2J GaAsPN//Si5.2% (AM1.5g)
    No ARC

    [17]

    2J AlGaAs//Si 21.2% (AM0)

    [41]
    &
    1J GaAs 21.3%
    (AM1.5d, 200-suns)

    [43]
    1J GaAs 20%
    (AM1.5g) &
    18.3% (AM0)

    [42]

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