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  • MIPS Reference Sheet (CS 241 Subset) : "Iii... Iii"

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    aamirkmq
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    The document is a reference sheet for the MIPS instruction set architecture subset used in CS 241. It contains: 1) A table listing the binary encoding for common MIPS instructions like add, sub, mult, div, lw, sw, slt, beq and bne along with their operands and function. 2) Notes about immediate operands being two's complement signed integers and how storing to address 0xFFFF000C prints the byte to stdout while loading from 0xFFFF0004 reads the next byte from stdin. 3) Explanations of the hi, lo registers used for the mult and div instructions and how branch instructions modify the program counter based on comparisons.

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    MIPS Reference

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    The document is a reference sheet for the MIPS instruction set architecture subset used in CS 241. It contains: 1) A table listing the binary encoding for common MIPS instructions like add, sub, mult, div, lw, sw, slt, beq and bne along with their operands and function. 2) Notes about immediate operands being two's complement signed integers and how storing to address 0xFFFF000C prints the byte to stdout while loading from 0xFFFF0004 reads the next byte from stdin. 3) Explanations of the hi, lo registers used for the mult and div instructions and how branch instructions modify the program counter based on comparisons.

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    Attribution Non-Commercial (BY-NC)
    Download as RTF, PDF, TXT or read online from Scribd
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    Download as rtf, pdf, or txt
    6 views1 page

    MIPS Reference Sheet (CS 241 Subset) : "Iii... Iii"

    Uploaded by

    aamirkmq
    The document is a reference sheet for the MIPS instruction set architecture subset used in CS 241. It contains: 1) A table listing the binary encoding for common MIPS instructions like add, sub, mult, div, lw, sw, slt, beq and bne along with their operands and function. 2) Notes about immediate operands being two's complement signed integers and how storing to address 0xFFFF000C prints the byte to stdout while loading from 0xFFFF0004 reads the next byte from stdin. 3) Explanations of the hi, lo registers used for the mult and div instructions and how branch instructions modify the program counter based on comparisons.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as RTF, PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 1

    .

    word i iiii iiii iiii iiii iiii iiii iiii iiii


    add 0000 00ss ssst tttt dddd d000 0010 0000 R $d = $s + $t
    $d, $s,
    $t MIPS Reference Sheet (CS 241 Subset)
    sub 0000 00ss ssst tttt dddd d000 0010 0010 R $d = $s - $t
    $d, $s,
    The
    $t immediate operands ("iii...iii") are two’s complement signed integers.
    mult 0000 00ss ssst tttt 0000 0000 0001 1000 R hi:lo = $s * $t
    Storing
    $s, $ta word to address 0xFFFF000C causes the right-most byte of the word stored to be printed to stdout.Loading a word from address
    multu
    0xFFFF0004 0000 the next
    places 00ss byte readssstfrom stdin tttt
    rightmost in0000 0000register.0001
    the destination 1001 R hi:lo = $s * $t
    $s, $t
    div 0000 00ss ssst tttt 0000 0000 0001 1010 R lo = $s / $t; hi = $s
    $s, $t
    % $t
    divu 0000 00ss ssst tttt 0000 0000 0001 1011 R lo = $s / $t; hi = $s
    $s, $t
    %$
    mfhi $d 0000 0000 0000 0000 dddd d000 0001 0000 R $d = hi
    mflo $d 0000 0000 0000 0000 dddd d000 0001 0010 R $d = lo
    lis $d 0000 0000 0000 0000 dddd d000 0001 0100 R $d = Mem[pc]; pc =
    pc + 4
    lw 1000 11ss ssst tttt iiii iiii iiii iiii I $t = Mem [$s + i]:4
    $t,
    i($s)
    sw 1010 11ss ssst tttt iiii iiii iiii iiii I Mem [$s + i]:4 = $t
    $t,
    i($s)
    slt 0000 00ss ssst tttt dddd d000 0010 1010 R $d = 1 if $s < $t;
    $d, $s,
    else 0
    $t
    sltu 0000 00ss ssst tttt dddd d000 0010 1011 R $d = 1 if $s < $t; else 0
    $d, $s,
    $t
    beq 0001 00ss ssst tttt iiii iiii iiii iiii I if ($s == $t) pc += i
    $s, $t,
    *4
    i
    bne 0001 01ss ssst tttt iiii iiii iiii iiii I if ($s != $t) pc += i *
    $s, $t,
    4

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