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  • Multiplier Bits Propagation Delay Power (MW) Area Utilization

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    Lokesh Gopinath
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    This document compares the performance of five different multiplier designs - Wallace Tree, Urdhva Tiryagbhyagam, Booth, Array, and Proposed - across bit widths of 4, 8, and 16. It provides the propagation delay, power consumption, area utilization, and memory usage for each design and bit width configuration. The proposed design has the lowest propagation delay and power consumption but higher area utilization compared to Wallace Tree and Urdhva Tiryagbhyagam for equivalent bit widths.

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    This document compares the performance of five different multiplier designs - Wallace Tree, Urdhva Tiryagbhyagam, Booth, Array, and Proposed - across bit widths of 4, 8, and 16. It provides the propagation delay, power consumption, area utilization, and memory usage for each design and bit width configuration. The proposed design has the lowest propagation delay and power consumption but higher area utilization compared to Wallace Tree and Urdhva Tiryagbhyagam for equivalent bit widths.

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    © All Rights Reserved
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    18 views2 pages

    Multiplier Bits Propagation Delay Power (MW) Area Utilization

    Uploaded by

    Lokesh Gopinath
    This document compares the performance of five different multiplier designs - Wallace Tree, Urdhva Tiryagbhyagam, Booth, Array, and Proposed - across bit widths of 4, 8, and 16. It provides the propagation delay, power consumption, area utilization, and memory usage for each design and bit width configuration. The proposed design has the lowest propagation delay and power consumption but higher area utilization compared to Wallace Tree and Urdhva Tiryagbhyagam for equivalent bit widths.

    Copyright:

    © All Rights Reserved
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    of 2

    Multiplier

    Bits

    Propagation
    Delay

    Power
    (mW)

    Area
    Utilization

    Wallace Tree

    4
    8
    16
    4
    8
    16
    4
    8
    16
    4
    8
    16
    4
    8
    16

    16.104ns
    36.904ns
    64.408ns
    15.025ns
    25.236ns
    60.327ns
    20.322ns
    46.740ns
    63.435ns
    22.741ns
    45.917ns
    68.868ns
    10.583ns
    28.270ns
    46.214ns

    221.93
    315.02
    402.38
    192.37
    287.90
    330.63
    225.15
    318.31
    337.92
    230.26
    329.11
    412.23
    150.45
    225.36
    303.21

    4%
    7%
    12%
    3%
    5%
    11%
    4%
    8%
    14%
    5%
    8%
    15%
    3%
    5%
    8%

    Urdhva
    Tiryagbhyagam
    Booth
    Array
    Proposed

    Multiplier

    Bits

    Wallace Tree

    4
    8
    16
    4
    8
    16
    4
    8
    16
    4
    8
    16
    4
    8
    16

    Urdhva Tiryagbhyagam
    Booth
    Array
    Proposed

    Propagation
    Delay

    10.583ns
    28.270ns
    46.214ns

    Power
    (mW)

    Area Utilization

    Memory Usage

    1%
    1%
    6%

    261888 kilobytes
    275904 kilobytes
    330688 kilobytes

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