IEEE Press «445 Hoes Lane, PO Box 1331 Piscatavay. NJ 08855-1331 Editorial Board John B. Anderson, Editor in Chief S.biiog De win 1M Moura sen S.V.Karalopoulos 1 Peden Mbt PLapane E, Since Sinencio Moline A. Lab Shaw F Hoyt M.Lighine Di. Wells Dudley R. Kay, Director of Book Publishing Russ Hall, Senior AcqustonsEitor Cari Briggs, Administrative Assistant Lisa S. Mizrahi, Review and Publicity Coontinator Valerie Zaborki, Praduction iltor IBEE Ciruits and Systems Society, Sponsor S'S Liaison o IEEE Press Edgar Sinchez-Sinencio Technical Reviewers Andress Andreu Stepon H Lewis Johns Hopkins Univesity Universi of Califor, Davin Sing Chin Po Lim National Semicondvctor Crome ne ek Cocoa Edgar Since Sinncio estig- Packard Laboratories “Texan A&M University Rote Jewett ‘Bang Sup Song Hewtit-ackard Laboratories University oF iis Aare Karanicols ‘Stan Tewsbury Masschusets Insitute of Tecnology West Vigna Unversity Principles of Data Conversion System Design Behzad Razavi ATAT Bell Laboratories IEEE PRESS TEBE Circuits and Systems Society, Sponsor ‘The Insti of Elected and leetoncs Engines nc, New York‘Ths book may be purchased at discount fro the publisher when ordered in blk quantities. For moe information contct IEEE PRESS Marketing ‘Am: Special Sales PO, Box 1331 4445 Hoes Lane Piscataway, NJ 08855-1331 ax: (908) 981-8062 (©1995 by ATCT. Al ight reserved Alsip reserved No pt his book may he rprodced in any form, ‘noe may the sored narra pte tansited ia a or, ‘without writen permission fom te publishes Prine inte Unto States of America wosT6s 4321 ISBN 0-7803-1093-4 IEEE Order Number: PC4465 rary of Canges Cage Pbleation Data aan Beha Anda phil frencs aides, 2, big ana oonerer”Doign ad count irate cr To the memory of my motherContents PREFACE xi CHAPTER 1 INTRODUCTION TO DATA CONVERSION AND PROCESSING 1 CHAPTER2 ASIC SAMPLING CIRCUITS. 7 21. General Considerations 7 2.2 Perfomance Metics 11 23 Sampling Switches 13 21 MOS Switches 14 232. Diode Swiches 19 233 Comparison of MOS and Dine Switches 23 2.34 Improvements in MOS Switch Performance 24 References 27 CHAPTERS SAMPLEAND-HOLD ARCHITECTURES 29 5.1 Comentonal Opentoop Architecture 29 3.2 Comantional Closed-Loop Architecture 31 13 Opentoop Architecture with Miller Capacitance 33Harries cuaerer s CHAPTER 6 34 Multiplexed-Input Architectres 35 355 Recycling Architecture 39 3.6. Switched-Capactr Architecture 40 37 Currentode Architecture 42 References 4 BASIC PRINCIPLES OF DIGITAL-TO-ANALOG CONVERSION 45 44.1 General Considerations. 45 42 Performance Metis 47 463. Reference Multiplication and Division 49 431 oage Division 50 432 Curent Division £8 433, Change Division 63 444 Switching and Logical Functions in DACs 70 “44.1 Suiting Fonction in Resistor Ladder DACS 4142 Switching Functions in Cutet Steering DACs 483 Switching Functions in Capacitor DACS. 74 {S858 Binay-toTemomeer Code Comersion 76 References 77 DIGITAL-TO.ANALOG CONVERTER ARCHITECTURES 5.1 Restantadder DAC Architectores 79 SLL" Laer Arciecte with Switched Suber 51.2 laemmeshed Ladle Archtstures RE 5.2 Curent. Stering Architectres 84 52.1 RaRNework Bised Awhitectres 522 Segmentod Archtetres 90 References 94 ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.1. General Considerations. 96 6.2 Perfomance Merics 99 6.3 Flash Architectures 101 631. Reference Ladder DC and AC Bowing 108, {632 Nonlinear lout Capacitance 106 ” bs CHAPTER CHAPTERS 64 65 66 67 68 633 Kickback Noe 107 634 Sparkes in ThemometerCode 108, 635. Metsability 110 636 Slew-Depedont Sampling Poin 12 637 Clock Jter apd Dispersion 112 638 Gay Encoding 114 Two-Step Architectures 116 G1 Elect of Nondalies 121 642 ‘TwoStep Recycling Achicure 124 G83 ‘Two-Step Sabunging Architecture 125 Intepolative and Folding Architectures 126 65.1 Inespostion 127 Pipelined Architectures 140 Successive Approximation Architectres 143 Inereavel Architectres 147 Reieences 149 BUILDING BLOCKS OF DATA CONVERSION SYSTEMS 152 7 72 Amplifier 453 TL Opee-Loop Amplifiers 153 212 Choseditonp Ampiies 160 7113 Operon Amplifier 164 714 Gain Boosting Testnigues TL 7.15 Common Moe Feedback 172 Comparators 177 721" Bipolar Compactors 1 722 CMOS Conparstors 188 723 BICMOS Comparten, 191 References 195 PRECISION TECHNIQUES 198 aa Comparator Offset Cancellation 198 S11" Input Orfe Stone 199 5.12 Ouipu Off Storage | 201 813 Mulistage set Storage 202 ALA Compara Using Offe-Canclled Lathes 206 6.2 Op Amp Ofiset Cancellation 208CHAPTERS 83 Calibration Techniques 211 831 DACCaliation Tehigues 211 832 ADC Calton Techniques 208 184 Range Overlap and Digital Corection 228 References 229 TESTING AND CHARACTERIZATION. 232 9.1 General Considerations 232 9.2, Sampling Circuits 234 93. DIAConverers 239 9.4 AD Converters 239 51 State Testing 299 942. Dynamic Testing 241 INDEX. 252 Preface Data conversion provides the link between the analog world and digital sys- ‘ems ands performed by means of sampling cireuits, analog-o-digital (ND) comerers, and digal(o-analog (D/A) converters. With the increasing use of digital Compating and signal processing in applications such as medical maging, inswumentaton, consumer electronics, and communications, the field of data conversion systems has rapidly expanded over the past twenty year. Monolithic integration, new architectures, and advances im integrated ‘iret (IC) technology have dramatically change the design style of these systems and created new ares for research and development. Asa result the body of knowledge related to this field, primarily in te frm of conference proceeuings and journal papers, has grown to sch extent thet stents and Practicing engineers typically spend more than a year on the learning curve after they have competed other IC design courses. The lack of systematic, comprehensive treatment the subject has made the task of learning dificult ‘nd nefcient ‘This book has been written as 2 unified text dealing withthe analysis and design of dat converters. Intended fer classroom apt 3s well as industrial practic, it methodically lead the reaer from basic concepts to advanced topics while explaining design issues at boh circuit and system level. In addition, to broaden the readers view of technalogy-dependent ‘design style, the text provides examples of CMOS, bipolar. ast BICMOS implementations fr various ctcuits and discusses the trade-ofs in eahcase.‘Thereader is assumed to have a solid understanding of analog IC design, preferably atthe eel of Analysis and Design of Analog Integrated Circuits by P-R Gray and R. G. Meyer and Analog MOS Integrated Circuits or Signal Processing by R. Gregorian and G. C. Temes. Some knowledge of digital ‘tet and th theory of signals and systems is also assumed ‘The book consists of nine chapters. Chapter | serves a an introductory overview, familiarizing the reader withthe role of data conversion in larger systems and providing the "big picture” Chapter 2 deals with basic sampling ‘Grits and analy es the behavior of MOS and bipolar switches with emphasis ‘on ther speed-precision trade-offs. Circuit echniques that relax such trade: fsa aso described, Chapter 3 extends these techniques to the architecture level by introducing various simple-and-hod topologies. ‘Chapter 4 suits basi digital-o-analog conversion viewing this ane tion as reference mliplication or division. Topologies in which the reer cence is voltage, curen, or charge are analyzed and the switching functions equiredin such cireuits are described. These concept are applied to system- level design in Chapter 5, where dgital-to-analog converter architectures are presented. Chapter 6 deals with analog-to-igtt converter architectures. Fash, two-step, interpolating, folding pipelined, successive approximation, and imerleaved architectures are sted and thee design issu and sources of| ‘eror are examined. Chapter 7 describes the design of building blocks of data conversion systems. ‘(Open-oop amplifiers, operational amplifiers, and comparators are discussed and means of improving thet performance are introduce. Chapter 8 focuses on precision techniques applicable to high-resolution «data conversion. Comparator and op amp offset cancellation, DIA and A/D calibration, and overlap a digital corection are covered in this chapter. Chapter 9 is concerned with the important topic of testing and character ization. Various approaches fo evaluating the static and dynamic performance ‘of sampling ercuits and D/A and AD converters are described in det act chapter is accompanied with an extensive set of references allow ing the reader to access the evil work olted teach topic, understand the intricate detail t more depth, and learn techniques not described in the text, Publishing a book isan elaborate, sometimes overwhelming tsk that can be cared out only with the support of great many people. During the two years I worked on ths ok, the stimulating environment st AT&T Bell Labs and the guidance of my supervisor, Robert Swartz, enabled me to efficiently interleave research and writing. When the Rist draft Wa f= ‘shod. numberof expert rom both industry and academia reviewed various parts ofthe msanusrip and provide helpful comments, In particu Brian Brandt (IBM), Sing hin (National Semiconductor) Robert Jewett (HP Labs), Andrew Karaicolas (ATT Belt Labs), Stephen Lewis (UC Davis), Peter {Lim (Chrontel, Krishnaswamy Nagaraj (ATCT Bell Labs), Marcel Pelgom (Philips), David Rich (AT&T Bell Labs), and Bang-Sup Song (University of ‘Minos, Urbana-Champaign) contibued with their meticlous reviews and swish to express my’ gratitude to all f them. Iam ofcourse solely responsible for any erors or inconsistencies that may have emained in the text, ‘During the publication process. | have henetited from the kind suppor ofthe IEEE Press staff and would like to thank especially Russ Hl, Valerie Zaborski, Denise Gannon, and Dudley Kay for ltr efor. Behzad Raza1 Introduction to Data Conversion and Processing ‘The proliferation of digital compating and signal processing in clecwonic 9- tems is often described a5 “the world is becoming more digital every day Compared with ther analog counterpans, digital circuits exhibit lower sen- ‘Skit to noise and more robustness to supply and process variations, allow casier dosign an est automation, and oer more extensive programmability But, the primary factor tht his made digital eiruis and processors Ubi ‘ous inal spots of our lives is the hows in their perfomance as a result of| advances in integrated circuit technologies. In paris. scaling properties ‘of very large seal integration (VLSI) processes have allowed every w2¥ gen- eration of digital circuits wo attain higher speed. more functionality per chip lower power dissipation. or lower cost, These tends have also been aug ‘nesied by cout and architecture innovations as well as improve analysis and synthesis computer-aided design (CAD) tos ‘While the above mers of digital circuits provide a strong incentive 10 _make the world digital. two aspects of out physical environment impede such slobalization: (1) naturally eocurring signals re analog (2) human beings perceive and retain information in analog fom (atleast on a macsoscopic Scale). Furthermore, when digital signals are corrupted by the medium sich that they Become comparable with nose, itis often necessary #0 teat them ssanalog signals. For example, acording to information theory fora digital ‘Sigal buried in ose, amplitade digitization and subsequent decoding (soft decision decoding”) can impeave the bi error rate2 India Das Comenion and Prcesing Ch. Inorderto interface digital processors withthe analog word, data aegu ‘ition and reconstruction creuts must be used: analog-o-dgital converters (ADCS) to acai und dite the signal atthe frontend, and digbal-o-anaog. converers(DACS) to reproducethe signal al thebackend. Thisisillstatein Figure 11 iA Imefice truce lg Weel and gil proces DDataconversion interfaces find application in consumer products suchas compact disc players, camera recorders (camcorders), telephones. modems, ‘nd high-definition television (HDTV), 2s wells in specialized systems such ‘ss medical imaging, speech processing, insinimentation, industrial conto, ‘nd radar. We study one ofthese applications to illstate tbe importance of both data conversion and digital processing in a typical product. Figure 12isa simplified block diagram of poable cameorer electron ies [1]. The imaging front end consists ofan ara of charge-coupled devices (CCDs that produce charge output proportional to the light intensity. The ‘charg packets fomall the CCDs are sensed serially und converted to voltage, ‘andthe resulting signals digitized the ADC. Subsoquentl, operations such ssautofocusng, image stabilization, luminance/chrominance (Y/C)process- ing and zooming are performed using one oF more digital signal processors (DSPs). The processed video signal is then converted to analog form and recorded onthe ape. Wihile adding many Features tothe recorder and improving its user in terface the signal processing functions in Figure 1. are far oo complex tobe implemented nthe analog domain, In fact, most of these functions have been ‘ukled to camcoder simply because the ADC already provides the signals in digital form. “The performance required of the data conversion circuits used in video systems sich as that of Figure 1.2 varies rom one application to another In portable camcorders, a conversion rate ofa few wees of mepahertz with 10-bit resoltion is adequate, but the power dissipation (and prefealy the (Chap. 1 natin Da Conenion nd Passing 3 toons ee? |[ oe tee ne Lal onc [+ Yio, see re precesing outa Fig 12 Siplited ack dng of porate camer eons. supply voltage) must he minimized. In HDTY, seeds as high as 70 MHz are esiable, whereas in high-quality studio recording, reslions of 12 (0 14 bits are necessary. ‘Since data conversion interfaces must deal with both analog and digital signals, their design becomes increasingly difficult if they are to maintain comparable performance with their coresponding digital systems, ie, not ‘appear asa bottleneck inthe signal path. This is because the primary wade olf in digital circuits is between speed and power, wheres tht in analog circuits is between any 180 of speed, power, and precision (including res olution, dynamic ange. and linearity). Furthermore, the operation of both analog and digital eiuis onthe same chip leads to coupling ofthe noise generated bythe digital section tothe sensitive signals inthe analog setoe. “This coupling occurs via shared supply lines, substrate currents, or eros lk between adjacent ins High-performance data conversion systems have often been bil sh ‘nd strates, wherein diferent parts ofthe system are designed in diferent technologies and pled and interconnected on a common (nonconducting) subsite, This flexibility usally allows hybrids to achieve a higher speed ‘han teie monolithic countrparts—sbe kv to ther survival. However. issues such x cos. reliablty. and power dissipation have seated a trend woward im plementing these interfaces in monolithic (VLSI technologiesand ultimately Integrating an entire data processing ysiem on a single chip Most ofthe a= chitecture and design concepts described in his book are used in both hybrid an! monolithic aplications, but the emphasis son the later ype ‘The integration of data conversion systems in VLSI technologies entails ifculties due to sealing, the very technique adopted t0 improve the per formance of digital circus. As supply voltages and device dimensions are reduced, many effects oocur tat ae not predicted by the ideal scaling theory. For example, dynamic range becomes more limite invinsi gan f devices egrades, and device mismatch increases. In ation to these problems, ‘many ther analog design issues suchas devi noise and accurate control‘ Innditon to Ea Comeion an Proesng Chap. of device characteristics ate usualy ignored in optimizing VLSI technolo ses, and modeling of devices i spically performed with litle concern for Parameters important w analog design. Consequem'y, oaining the required precision becomes the primary concer in analog and sexed analog-igal ‘routs, often necessitating conservative design and sacrifice in speed and power dissipation. ‘Lets now closely examine the data conversion interfaces of Figure 11 ‘The analogtowigital (WD) interface converts continvous-amplitude, continvous-time input to a discrete-amplitide, discrete-time signal. Shown in Figure 13 this interface in more det. Fist, an analog low-pas filter lim its the input signol bandwidth so that subsequent sampling does no alas any ‘uated noise oF signal components into the acta signal band. Next, the filter ouput is spl soa o produce adicrete-time signal. The amplitude ‘ofthis waveform is then “quantized” 4, approximated with level from a set of xed references thus generating a dseete-ampliudesgeal. Finally, a 38 ay AT. an ‘where 5) dnote the Dirac dela funtion, Tiscaus the signa specu to teconolved withatrainof impulses ithe frequency domain, hs repiating ad shifting the signal spe by integer males of nin= xe S B-fyan Lee TeX “This peta yields signals that are easy to analyze but sno practical because of thediicultiesin generating an del impulse or any reasonable approxima: tion thereof. Als, the samples produced his operation re often difcul to process because circuits following the Sampler usally requie thatthe sampled signal have a nonzero duration, ey S21 Genera Comision , In the second scheme [Figure 21] the value ofthe waveform atthe sampling instant is captured and eld until the next sampling instant. This equivalent to multiplying the waveform by a periodic tain of impulses ad ‘snvolving the result witha rectangle Function [ro Eaewofenge-p. eo mo) whote Flr/Ts~ 1/2) denstes single pulse with unity amplitude fom = 0 {or = Ts, the frequency domain. aspect similar that of Figure 2.1) is obtained bu iis mulipied by sine function: mn nian gy sete einen eet = yatn = fay $50 -ars- B] on es) te 2 Ts vane Sei os amy pert re Baw® ai Sampling Cis Chap. 2 In contrast with the ideal stmpler, the zeroorder-old and the track and-hold schemes yield ouput speeta that have sine envelope, ic. are “distored.” This problem mandates sine compensation techniques (1 f the sampler is wed atthe back end of a data processing system, Tor example following a DIA converter (Chapter 1). However, the zero-oner-hold and track-and-hold circuits ean be used at the fron end of A/D converters with no concer forthe sinc distortion. Thisis possible because A/D converters sense ‘he output of th front-end sampler only during the bold mode, and hence the digtied value corresponds to sampled points on the inpt waveform. In ‘other wows, the combination of the front-end tack-and-hold and the A/D jomerter operates as an ideal sampling circuit In high-speed systems, the distinction berween the outputs of the er0- ‘order hold and track-and: hold schemes bepins to diminish because the per ‘ure window width becomes comparable withthe sampling period. Asa esl except for special application where te aperture window is inthe picosecond ‘ange [2], most monolithic sampling circuits operate asin the wack-and-hold ‘Scheme. In this book, we consider implementations of his scheme, which are often called sample-and-hold amplifiers (SHAS) or wack-and-bold amplifies (THAs, Figure 22 shows a simple sample-and-hold circuit. Inthe sampling cqusion) mode, switch $ controlled by CK ison and the ouput voltage, Vo. tack the inp voltage, Vi. Inthe transition to the old mode, S turns cf and Vay remains constant until the ext sampling period. In this circuit, the switching operation ind the transient cuments drawn by Cy introduce ‘noise atthe input, often manting the use ofa front-end buffer. Furthermore, since the voltage stored on Cy daring the hold mode can be corrupted by any constant or wansientcurent drawnby the Following circuit, a buffer must also be placed atthe output resulting in the ciruit shown in Figure 2.3. cK es Fig. 22 Simple anpleans old Inpractice, the nonidealities ssocated withthe buffers andthe sampling switch in Figure 23 necessitate substantial added complexity to achiew a $66.22 Peformance Metie " aiven set of performance specifications. In act, as discussed in Chapter 3, Some SHA architectures are considerably different from that of Figure 23, Input Output Butter CK Butter Pte. iP. ig. 23 Sample nd ld hou with ip and tpt ters Before describing various nonidealities that accompany the building blocks of SHAs. we need to define performance specifications of sampling 2.2. PERFORMANCE METRICS In omer to characterize sampling cireuits thoroughly, a large number ofp rameters must be evaluated. The terminology and definitions adopted for SHA metrics by different manufacturers are not exactly the same anc an «cause confusion when dlferent designs ae compare. I his section we de fine a number of terms commonly used to describe the performance of SHAS ‘0 8 to establish a consistent set of metrics fr ths book. Fora more com prehensive set of definitions, the readers refered to the erature [3] and 10 manufacturer” data books, ‘The performance metrics defined below are illustrated graphically in Figure 24 and discussed using the SHA architecture of Figure 2.3 ‘Acquisition time, fg, the time after the sampling command re- ‘quired forthe SHA output to experience a full-scale transition and Sle within specified ertoe ind around its Gina vale. Acqui- Sivon ime is determined by the recovery delay of By and Bs the lon-resistance of 5, the valve of Cy, and the maximum allowable * Hold setting ime, ty, is the time after the hold command required for the SHA output to sete within a specified error band around its final value. This ime is given primarily by the seing ime of Ba. ‘+ Dynamie range isthe rato ofthe maximum allowable input swing and ‘the minimum input level that an be sampled with specified accuracyasi SamplingCreuis Chip. 2 Dynamic range is limited by supply voltage, sreshold or tum-on voltage of devices used in he eteit, and input-reered noise ofthe Nonlinearity errors the maximm deviation ofthe SHA inpavoutput ‘Ad in Figure 24(b)]. Usually specitied forthe held values of the i ertor originates fom nonlinearities in By and oan ‘ar dependence upon big ofthe charge injected by onto Cy and ‘aration ofthe sith on-esstnce wit the input voltage. Aperture iter isthe random variation inthe time requited for the sampling switch o turnoff after the hold command is asserted. Also called “aperture uncertain” this eor isa measure ofthe deviation of sampling instants fom equally spaced points in time and arises from the nose that afects the hold command assertion eter in transitions of CR. Pdestal ero voltage isthe errorintoduced atthe SHA output during the transition fom sample to hold, This eror sms rom the charge iupcted by § lo Cy when this switch turns of. Gain error the deviation ofthe slope of line AB from its deal value (usually unity), Tis eror results from the gain eror of By and Bs and input dependent pedesal volage Hold-mode feedthrough i the percetageof the input signal that ap- pears tthe output during the hold mode. This effet appears because ssc 5 usually ha a parasitic capacitive path between its input and ‘oviput terminals even in the off sae. This path conducts voltage ‘ariations and gives rise to input feedthrough during the hold mode Droop rate isthe rate of discharge of the capacitor during the hold mode. Droop rate is fuetion of the leakage curents draw by paras de paths from node X wo other nodes (eg, the substrate). the Input bias current of Bs, and the value of Cy, Signalto-noise aio (SNR) isthe ratio the signal power tthe noise poster atthe output inthe hold mode (usualy Toe sinusoidal inp) [SNR is limited by the noise contributions fom Ay, ahd San he aperture iter, Signal-to (noise + distortion) ratio (SNDR) isthe rato ofthe signal power tothe foal noise and harmonic power atthe ouput in the hold ‘mode (or sinsoidal input SNDR s limited by the nose sources ‘mentioned above nd nonlneariies resulting vom By, Ba, and charge Injection of 5. S063 Sampling Stces 2 i) < Vor co Fe 24 Sample sl psfrmace mis 2.3 SAMPLING SWITCHES ‘As noted in the previous secon, large number of SHA Timitation orgi- tat fom nonidealities of the sampiag Switch. Acquistion time, aperture jitter. nonlinearity, pedestal erro, feedthrough, and SNDR of these circuits te strongly inlvenced by the sampling switch performance Tn this section, we describe two types of sampling switches commonly ibiza in €MOS and bipolar SHAS. In Chapter 3, we will se that depending, fn the architecture, other switching techniques can be employed to improve the performance.4 ‘Basi Sumpling Cacais Chap 2 23.1 MOS Switches ‘AnMOS transstorcan be wed as an analog swith, wit is gate vollage controlling the resistance berween ls source and dean (Figure 25), For ‘square law NMOS device that operates in the linea (see) eegon, this resistance can be expressed as ' aC EVs — Vand" were isthe eestron mobility in the channel, Cs the gate oxide capac itane per unit fe, W and Lae the Tete with and length of the device, respectively, Vos isthe gate-source voliage, and Vr isthe threshold velage For a fixed sampling capacitor, the acquisition time can be deceased only by lowering Ry. ie. by increasing the tems inthe denominator of (210) 1m agiven CMOS process, Cx is normally constant and Vos sully ean- not exceed the supply voltage, leaving W/L as te only variable in (2.10) ‘Thus highspeed applications often incorporate MOS switches with a large wie. Rew ¥ oe E Vou Ym * q You @ o ig 28-0) MOS sling ces () equal owe te mpg In addition (0 a finite on-resistance, MOS switches exhibit channel charge injection and clock feedthrough. When on, a MOSFET caries acer tain amount of charge in i channel that, under strong inversion conditions, can be expressed as Oa © WEE Ves ~ Vr. eu ‘When the device tums ofthis charge leaves the channel through the soars and dean terminals, introducing an eror voltage onthe sampling capacitor (igure 26). This ewor appears aban offset if Qe is constant, again eror i (Qs incaly proportional othe inp sigh, oa nonlinear erm if Oy has 3 ‘nonlinear depenienc athe inp signal, While the isttwo peso errorcan be tolerated in some applications ee, data converters used in digital signal Se. 23 Sampling Shes processing), the thin type Tits se inearty ofthe SHA and contributes Frmonic distortion. The nonlneat component in Qc aes rimarily from the nonlinear dependence of Vig i (2.11) onthe input voltage through body cles. “The charge injection mechanism in MOS switches hasbeen analyzed ‘extensively [4 5,6), These studies show thatthe faction of de charge in jected onto the sree and drain terminals depends on both the impedance ‘een a these noes and the clock ans tne [6]. In ado, these stad ies have provided mathematical descriptions ofthe inet theoretical and experimental plots ofthe injected charge asa function of the impedanoes and clock tassiton time [6 In practice, however. itis dificult to accurately pret or contol these variables or apply the ero figures me ‘Sued fora given opology 1 anoereieuit. More importandy, most ofthe present circuit simulation programs do ot sodel this mechasism accurate! For these reasons, many citeut techniques have been inves © suppress charge injection ero eeardles ofthe exact valve of such prameters as ter- nial impedances and clock transition ies. These techniques ae described inthe context of SHA architectures in Chapter 3 "Amote soce of erin MOS switcesis cock feeiouh,causedby the nite overlap capacitance between he gte and source or drain terminals. ‘As depicted in Figure 2.6, when the gate contol voltage CX changes sate te turn the switch, Cw conducts the transition and changes the voltage sored fon Cu by at amount equal 10 Cu meu where Vex is the amplitude of CK. This equation insicees that clock Feedthrough is independent ofthe input signal if Cy is constant and thus “appears aan offset nthe inpuoupat characteristic ave ery6 ase Samping Cats Chap. 2 A frequency-dependest nonlinearity err in MOS sampling circuits arises from the variation of the switch o-tsistance with the input voltage, ite the dependence of Rag n'2.10) upen Vos. As shown in Figure 27 or high-frequency inputs this variation inroducesinputdependent phase shit an hence harmon distortion. Yin on igh Fig.27-Dstonion ced hy swith on estan aio inte hing Another eror that appears in high-speed MOS sampling circuits stems from the inpt-dependent sampling insta. Since the MOS switch turns off ‘only when it gate-source voltage has fallen below Vn. the time at which the device turns off and the cicut enters the hold mode) depends on the insantaneous level ofthe input. For example, if the switch fs an NMOS. ‘wansistor, then the circuit enters the hold made slighty later whe the input Signal is near ground potential than when its higher. Mlusraed in Figure 28, this phenomenon introduces iter and harmonie distortion and becomes noticeable when the cock transition ime s comparable with the inp signal slew rate. Fora sinusoidal input with ampliude A and frequency fi it has ‘been shown hi this phenomenon limits the signal-t-distrton ratio (SDR) ofthe SHA to Vor ai where Vx and ty are the clock amplitude and fllime, respect ‘An important aspect of sampling ereit is the hold-mode fedtvough because it can conibute noise o the output. As shown in Figure 2.9, for 44 MOS soit tis error results from the path through the soure-gate and gate drain overlap capacitance and canbe expressed 3s SDR po = 20boy See.23Sumping Swit: ” Fig. 28 Depends Sampling isnt ing ee Yat e1) Ve where Ryu denotesthe output esistance ofthe switch driver and itis assumed Cor & Cr The vale of Rou shouldbe chosen such that he feedthrough at ‘maximum input Fequeney i suficently small ke fee Coy... Vy AE ~ 3 Min I” Mout Fig 20 Hothnode Fediroush, “The sampling switeh input and output ange can aso mit he Fllseate voltage swing ofa sampling circuit. Fora supply voltage of Vin. the cir cuit of Figure 2.5 has @ maximum full-scale range of Vo — Via. Where Vi ncludes the body effet where appropriate. In practic, the input swing hardly exceeds (Vip — Vni)/2 because ofthe substantial increase in switch resistance and the resulting Fequency-dependeat harmonic distortion. This” Base Samoting Crees Chap. 2 range can be extended to supply rails ifthe swith i welized asa comple- ‘mentary pit. As depicted in Figure 2.10 ths s accomplished by controling the gates of a» NMOS and a PMOS devi with complementary clocks so thatthe two devices turn on and off simultaneously, I transistor conducts for 0 = Va < Veo ~ Vass while the PMOS device is on for [Viyol < Vn = Vo. thereby providing ait input and output range cK ma Fig 210 Complementary MOS anping ches In addition to an extended range, the circuit of Figure 210 has another important advantage over that of Figure 2.5: the equivalent on-esistnce of {8 CMOS switch, compared with that ofa single NMOS or PMOS device, ‘ares mach less a a funtion ofthe input voltage. Figure 21 plots the on- resistance of an NMOS, a PMOS, and a complementary MOS switch versus the input volage, indicating only @ small peak inthe CMOS on-esistance near the middle ofthe range. The relatively constant on-esistance across the entire inpuvoutput range allows reasonable sizes forthe switches and also ‘minimizes the harmonic distortion caused by variation of switch resistance ‘While it may seem that M and Af in Figure 2.10 cancel cach others charge injection if they have identical dimensions. equation (21 indicates ‘hat [Qual depends on [Vos — Vn and hence will noc be equal for Mf, and (Ma if Vg has an arbitrary vale. lohighspeed applications, the complementary clocks required for ‘CMOS switchescan pose timing problem. Unless the clock edgesare aligned such tha the two transistors tun off a prccsey the same instant ether one ‘cul be conducting weakly for short while, intodocing an input dependent pase shift or sampling instant An important feature of MOS switches stat they intodee 2x0 offset (level shit) fom ther source to their drain if the following circuit draws no 6.23 Sampling Sn » Pol Pus: os. 0 re foo Vin Min current, This isin contrast with the behavior of diode switches described below. 2.3.2 Diode Switches Semiconductor diodes exhibit sal on-esstanee, larg off-esistance, high-speed switching. and thus poental for the switching function in sam Pling circuits. simplitid diagram o typical diode switchs shown in Fig ‘e212 [8]. Here, four diodes form abridge that proves a low-impedance: Pat foo V0 Vay When eureet sources 7; and 2 are on and in the ideal ease) isolates Vg trom gehen fy and Js ae off, Nominal, f) = f= 1 For sonall signals a Vp and Vag, the equivalent on-resistance of the site, Ry equal tothe parallel combination ofthe resistance ofthe 180. branches consisting of Dy-Dz and Dy-Dy. Each diode exhibits an incremental resistance, I/gq, resting from its exponential -V characteristics, as well san oie resianee, 7, due to comet and material resistance. Thus, +0 es, Ineniero minimize Ry, gq canbe increased by raising the bias cureat ‘or ean be lowered by inreasing the area of each diode, The latter remedy, however, increases the junetion capacitance of the diodes, thus causing larger feeathrough inthe hold mode. This effet is quanied late. ‘Actual implementations ofthe diode sampling bridge often control only ‘one ofthe curtent sources, usually 1, while the other is always on. Tis js because i is ficult to tam off and Jp at precisely the same instant,” Base Sampling Crests Chap. 2 ig 212 Diode snp sch ‘especially if high-speed pnp or PMOS trunsstrs are not availabe, Figure 2.13 illstates such ab implemenation. Here, when CX is high, Qy is ‘off, Qs on, andthe circuit isi the acquisition mode, When CK goes ow. (0; tums 0a, O> and hence the bridge turn of, and the circuit enters the hold ‘mode. Note tht 1) need aot bea high-speed device frit operate asa passive ‘Component, but the capacitance i introduces at node X is etic Inthe creitof Figure 213g), when CX is low andthe bridge sof, Qs ‘may enter stuation because the voltage at node X isnot well-defined. Figure 2.1Mb> depicts a modification where clamp diodes Ds and Dg and current Ssowee Fy are added to the circuit. Typically. [2 ~ J) + /s and the clamp voltage Vpy is atthe midpoint ofthe inpot voltage range. When Cis high, (Q2 sink bosh f and, and Ds and Dg are reverse-iased if Vp} ~ Vo ion = Vin < Var + Vosgay. When CK goes low, Fs flows from node X, Ds turns ‘onand Vy iselamped to Vai ~ Voson. wile Fy lows through Dy and Vy is clamped © Vay + Vos "The variation ofthe on-esistanceof a diode switch function ofthe inpat voltage is differen from that of a MOS device. Inthe circuit of Figure 211, when the input voltage goes through a positive excursion, Cy draws turrent from Dz; therefore, Dy and Dy condvct les, whereas Dy and Ds conduct more. Ifthe change Inthe curents of Dy-Da isa smal fraction oF their quiesentcurent fo, then the increase inthe resistance of Dy and Dy is compensated by the decrease inthe resistance of Dz and Ds espetively. ® » Fig212_(Siplebiptr sampling ig; ( mated wihlany thereby yleking negligible variation inthe on resistance ofthe ove switch, ‘We can formulate the above condition by noting that Vin Ve Asin 216) ‘hen the maximum curent drawn by Cy occurs when = nx /eandisequalto Bog I = Conn cnet, ern Cube es) ‘This current must remain much les than. CwAw et. a9 ‘The charge injection and feedhrough behavior of diode switches is also Afferent from tht of MOS devices. Since a diode biased at a current Ip carries «charge equal to fo re, where tes the transit dime, the charge injection eroris relatively constant because, as expltned above, ina properly designed switch Jp remain atl constant. Thus charg injection inreduces ‘only a constant offset inthe inpuvourput characters. On the other han,2 a Sain its Chip 2 in the diode bridge of Fire 213(b) the change in Vy and Vy. which is coupled to the output srough the junction capacitance of Ds and Da, causes nonlinearity and gain eror (9. To understand why, note that in the tacking mode, Vix = B+ Vos ate Vy = Vn ~ Voge. whereas inthe hold mode, Vy = Yai ~ Viv and Vy = Vai + Vow). Consequenty inthe transition fram tracking 10 hold, Vy drops by Vie — Vai + 2Voqon ad Vy tses by Vp ~ Vn + 2Vine creating an inpu-dependent pedestal at Vo. Since the junction capacitance of D> and Ds is voltage-dependent, the pedestal has 3 significant nonlinear component In order to eliminate the input dependence of the pedestal, Va can be bootstrapped 10 the held output voltage (9). This is illustrated in Fate 214, where the unty-gain ber provides a clamp voltage equ tothe he evel. Now Vx and Vy change by ~2Vpje and +2Vians espetivel, Yielding substantially less nonlinear Pig 244 Sanpin ee wih ostppa tmp waa “Thehold-modefedthrough of sampling brides depends on the junetion capacitance ofthe ridge diodes and the on-esstnce of the elap deve Sec.23 Sampo niches » For example, when the circuit of Figure 2.13() isin the hold mod, it can be simplitiod as shown in Figure 215, where the aneton eapacitance of Dy 1D is modeled with C), and the on-rexistance of Ds and Dy with Req. FOr 6) Cys the feedthrough transfer function is expressed as Vo yyw 201, Reals 220) 1 ore og i Fen N Yi Yor Fen fm GG A ingress natn ty inpne on te inp an apr oage nig ine ce of Fg 1S) ‘Sen ae ply re ist OS in a hgh tt ingens he econ a 189) fe ene tat gs mothe Vere procs 03 Vo oe nt awd {SnC ge, Acs betunima slag ving sn gna SX pation 10 Roce eer fd chsh ft gt apt due rs msmacies, Forex nPgu2 130) f= yr 8 {Dyan Do ntact ei out fat lage vn Ven SE 4 MS Von Vein + SE 4 erste ela ish been te tin cen y my 2.3.3 Comparison of MOS and Diode Switches Following ur study of MOS and nd switches in the lst two Sections, we can now compare their properts. a2 * Diode switches generally have a Jower on-esstance than MOS sovtehes. IF each diode ina bridge is based a 0.5 mA and has aPy avi Sampling Crests Chap. 2 seri (ohmic) resistance of 40 2, then the equivalent onesitance ‘ofthe bridge i approximately 90 2. Ataning such a low resistance with « MOSFET sully requires very large widh-0-length ratios, 'ypically eeatr than 1000. This in turn exacerhaes charge injection an lock feedthrough problems ‘Thea resistance and charge injection of diode switches depend much Jess on the input voltage than do those of MOS devies, making the former moe attractive Tor high-precision open-loop applications, Diode switches suchas that of Figure 2.13 operate with clock vltage ‘wings roughly an order of magnitude smaller than those of MOS ci ‘cuits, allowing sharper edges and better definition ef sampling pots in time, For this eason and dacause of lower noise in ECL circuits than i» MOS cireuits, diode switches have a potentially lowe jer than their MOS counterparts ‘+ The input voltage ange of MOS sampling circuits is generally lager ‘han that of diode suites, thus allowing a wider dynamic range. MOS switches introduce node level shift (fst from the ips the output ifthe following citeut draws no curent. Diode bridges, ‘on the other hand, serra inte offset caused by mismatches in current sources and odes, *# Diode switches are ypieally mach more complex an dissipate much more power than MOS sampling cieuls. The circuit of Figure 2.1310), for example, quires atleast six diodes, a ditlerential pit, and hrc curten surces whose magnitudes and variations with fe. perature and process mast he well-contmiled. -& MOS sampling Site, on te ater hand consists af one of two transistors. While this dfterence in complexity and power dissipation may nt be sig nificant fora single SHA, i becomes important sf sampled-data system such as an A/D converter oa filter require a great number ‘of sampling switches. 2.3.4 Improvements in MOS Switch Performance ‘The simplicity of MOS switches has made them tractive frlarge-seale analog iigrated cireuits. However, as discussed in previous sections, MOS devices suffer from large on resistance and substantial charge stored in thet chanel. Infact, the strong trade-off between these two parameters imi the level of ypeed-acuracy that cap he achieved ina simple circuit such a8 that ‘of Figure 2.5, We can formulate this trade-off by detning a figure of meric F = {(pedesial enor acquisition ney}! 222 Se. 23 Sampling Swen s ‘The pedestal rors ay, 02) 2H WLCox(Vos — Vow) uy where we have assumed hal of the channel charge of te switch is injected ‘onto Cy and nesected clock Feetirough, The acquisition time constant is Rau 225) Cu Tab Ves = Vand Note that since tay depends onthe gate-source voltage and ence varies with input, modeling the acquisition Behavior witha single ime constant sony 3 rough approximation. from (2.24) and (2.26) i flows that 1 : em 026) pie a 4 (2.28) qs ‘This equation indicates tha, ina given CMOS technology the MOS sampling -sircat of Figure 2-5 doesnot achieve a spesd-accuracy product higher than roughly 2s,/L2, This producti further degraded by clock feedthrough, Tm onder to rela the trade-off given by (2.28), numberof circuit tech niques have been proposed, two of which ae illustrated in Fighre 2.16. In Figure 2.16(a) adummy device M; with half the wid ofthe spring switch 1M, (and he same length) is added and driven By CK, the complement ofthe Sampling clock CA [16 tnthis ireut, when A tues off ad injets charge ‘nto Ci Mo turns on and absorbs charge from Cy in is ehanne, This, itexactly half ofthe My channel charge is injected onto Cy, then complete ‘aneelation occurs andthe held voltage on Cy is nt corrupted by the charge injection, However, the fraction of channel charge injected by M; onto i source and drain depends onthe impedance seen athe input and eur nodes and the clock tanstion speed [6] indicating tat Cyr may not recive ball of the Af; channel charge and that this scheme may not provide accurate cexncocon Figure 216(b) shows another sampling configuration, where the cre 1s implemented jn differential form (11). Th ths topology. Vins and Van2 ane ferential inpats (Ve, they vary by the same amount bul in opposite6 Basi Sampling inate Co. _ cK cK t My Ma Vins Yours a tm y, Cy = io Fe. 216-Cansiton of MOS cg ition ig amy sui 0) tore operate iectons) and Vay and Vag? fe diferenta outputs (ie. thee diference is sensed by the following circuit), Charge injection and clock feedthrough fro at Vg aD V2 A tthe fist order equ ad hence appear ee ‘eommon- mode (CM) component athe output. Ap important ero, however, Still ents ere: since the chanze charge of Mand My isa function of their Vas apd since Vy # Vin2 the differential eld output ineludes an Input-dependent charg injection eror tr. This term introduces gin error and nontneariy limiting the usefulness of this topology only to applications Where Vig ~ V2 ich less than the Vos ~ Vi of the swtches, ‘Another MOS sampling technigue is depicted in Figure 2.17. tn the acquisition mode, Mi and My are on. Miso, Yau = Voov andthe capacitor ‘voltage tacks the input. fn the transition othe hold mode, rst & goes kw, turning off Ma, and after a small delay falls, wring My off nd #7 00 ‘Thus. Vi drops from Vj to 0 and ence the cage in Vag i 9 10 —Va atthe sampling instant."Since 4 always tur of fis, the channel charge ‘of Mya i input dependent—does not inroce any eno. Moreover, a te gatesoure voltage of Mr is independent of Vg. the channel charge injected by this switch spears 38a constant offset tthe output. ‘While suppressing input dependent charge injection. the circuit of Fig ‘re 2.17 sues from another source of nonlinearity that limits is spec. In the transition t hold, when Vg falls from Vp t© Vino ~ Vn 8 voltage d- vision occurs between Cy ad the rain junction eaacitance of Ms, siding nonlinear component it Vou Since this capacitance is properconal to the ‘device width, i iadesdirecly with the on-esstance and hence the acquis sition time. Nevertheless, illerental Yersions ofthis topology an provide _laively high speed and high linearity. p.2 Referees 2 am, Cn Betas (217 C0 wn hs Appendix2.1 Effectaf Aperture teron SNR. Considerasine wave ‘in 2x fit samples at ¢-= ATs +, where « isthe aperture iter. Since each sampling instant can deviate from ts ideal valve bye, the sampled amplitude fas an ror of €dVg/dt. Thus, the overall sampled waveform am be viewed asthe sum ofan ideal sine wave and noise component. To taleulate the SNR for an otherwise ideal sampling crit, we assume that € Jgarandom process uncomelied with Vand expres the poise power as al (haa padd, [Matera Q. aE 029) aaa. 2230) pu) denotes the mean squared value of ¢ (12). Thus, SNR = ~2010g(23 fing) 6B: ean This relation proves wef ifjteris the dominant source of nose in a system, Ina general ese, ther sources f nose must be taken ino account a wel REFERENCES 1} R. Gregorian and G. C. Temes, aloe MOS tntegrated Circuits for Signal Processing, Zohn Wiley and Sons, New York. 1986 (21K. Rush and D. J. Oldfield, “A Data Acquisition System for a 1-Gltz Digitizing Oscilloscope." Hewlen-Puckard J, April 1986, pp, 4-11 [31 S. K. Tewksbury, etal, "Terminology Related to the Performance of SIM, A/D, and DIA Ciscuits” IEEE Trans. Creuts Syst. vol, CAS.25, Pp. 419-426, July 1978= ase Samp Cuts Chap 2 Is] B. J. Shou and C. Hu, “Switch-Induced Error Voltage on Switched Capacitor” IEEE J, Sol State Crews, vol SC-19, pp 519528, April 198, [5] W.B. Wilson etal, "Measurement ard Modeling of Charge Feedthrough in.W-Channel MOS Analog Switch," IEEE J. Solid State Circuits, vo $C-20, pp. 1206-1213, Dec. 1985 (6) G. Weamann, B.A. Vitor and F Rahal, “Charge Injection in Analog MOS Switches” IEEE J. Solid State Cireuis, vol. 8C22, pp. 1091 1097, Dec, 1987, [7] B.A. Lim, Performance Limitsof Circuits for Analog-to-Digital Conver sion, PAD. disseation, Stavord University, March 1991 [8} J.R. Gray and S.C. Ktsopculs, “A Precision Sample and Hold Circuit With Subnanosecond Switching.” IEEE Trane Circuit Theory, vol. CF 1p. 389-396, Sep. 1964 [9] K.Poution J.J.Corcorar, and. Horak, "A 1 GHz 6-Bit ADC System,” IEEE J Solid State Cireuits, vol. SC-2, pp. 962-970, Dec. 1982 [10} C. Eichenberger and W. Guggenbuhl, “Dummy Transistor Compensa- tion OF Analog MOS Switches” /EEE I Solid-State Circuits, vol SC-24 pp. 143-1145, Aug. 1989, [1] K. C. Hsieh et al, "A. Low Noise Chopper Stabilized Differential Switched Capacitor Filtering Technique,” EEE J. Solid-State Creuts, ‘ol SC-16, pp. 798-715, Dec. 1981 [12] M. Shinagawa, ¥. Akazawa, and T, Wakimoto, “Biter Analysis of High: Speed Sampling Systems," IEEE J. Solid Stare Circuits, vol. SC-25, pp. 220.204, Feb 1990, 3 Sample-and-Hold Architectures Since the inodetion ofthe fist monolithic sample-and-hold amplifier in 1074 [1], a variety of architectures amenable to integration indifferent tech otoges have been propose. Owing to these architectures, as well 38 ad- ‘ances in integrated circu technology, the performance of SHAS his dr maially improved, proifing 12-bit acquisition times of less than 25 nse in 1091 [2] compared to 10sec in 1974 [1]. These architectures generally em play circuit techniques w reduce the pedestal err without sacrificing speed land linearity ofthe system, In thischaper, we describe a number of SHA architectures often use in ata acquisition systems. Upto the mid-1980s, most sample-and-hod ics Fel into either the “open-loop” ofthe “elose-oop” eategory [I], However, the configurations introduced in recent years cannot really be classified in {his fashion because the incorporate varius local and soba feodbuck pat, ‘obscuring the disinetion between open-loop and closed-loop topologies inthe ‘conventional sexse. For this reason, we deserbe each ofthese architectures individually 3.1. CONVENTIONAL OPEN-LOOP ARCHITECTURE “The open-bop architecture has been considered attractive because of its sim Plieity and potential speed. Used in Chapter 2 to ilustate SHA propentis land shown in Figure 3, this architecture consists ofan input Buller By,” Samolean Hold ciesnes Chap. 3 ‘Sampling circuit comprising $ and Cy. and an output buffer Ba. When Sis ‘on, the crit sin the acquisition mode and Vi tacks Vi When Sturas (of, the instantancous value ofthe input is stored on Cy and the circuit enters the hold mode, Input output Butter OK Butter Fe 3M Osu ample nol cite As this topology includes no global feedback, its unconditionally st ble (if and By are stable) and can therefore be designed fr high-speed ‘operation. For example, utilizing Schottky diode bridges, this architetare has achieved rates as igh as 2 GHz [3 “The speed of the citcut in Figure 3.1 is determined by is acquis tion time and hold setling time. The acquisition time depends onthe tack: ing speed and output impedance of By, the onresitance ofS, and the value of Cr while the hold seling time is governed by the seting behavior of By In adton to ther impact on the SHAS speed, B) and By also influence the linearity ofthe system, especialy because both experience full signal swingsat teint and output. As aconscquence, the linearity requiemeats ofthe overall SHA often impose resvctions an the design of By and Ba, thus limiting their speed. In acneral, these buffers can employ aper-00p ‘configurations with varius correction echriges [3] to achive linearis up to IOC, For higher linearity, they are usually implemsntd as bih-gain amplifiers with local feedback. Chapter 7 describes various ampliter sign ‘An important drawack of this architecture results fom the inpu-de- pendent charge injected by the simpling switch onto the hold capacitor, an feminent source of nonlinearity in MOS implementations. As explained in Section 2.3 this err is not reliably canceled by dummy devices or differen ‘ial configurations and hence limits the linearity of open-loop CMOS SHAS {o approximately bits. Diode switches, on the other hand, exhibit much less inpu-dependent charge injection and have been succesfully used for Tinearites upto 12 bis in bipolar technology (3) 6.32 omen Cad Loop Arte ” {in summary the open-loop architecture offers highspeed and eatvely high linearity when realized in bipolar SHAs with diode bridges but sufers from input-dependent pedestal ertor in CMOS implementations. 3.2 CONVENTIONAL CLOSED-LOOP ARCHITECTURE Inoner to suppres input-dependent pedestal errors in a SHA, the sam plingsvitch canbe included na feedback lop such hit texperences voltage swings moch smaller than the input and output swings. This concept the brass for the closed-loop architecture shown in Figure 3.2, which cousins of transconductance amplifier Gy, sampling devices and Cy, a a voltage unpliie Ap [1]. The circuit operates as follows, In the aquisition mode, S ‘son and the cteu functions asa two-stage opamp compensated by Cry and configured as a unity-guin bu. Thus, the output closely follows the input and, if Ap is large, X is vital ground node allowing the voltage across Ci w track the input. When 5 turns of, the instantaneous utp volage is stored on Cy and the feedback circuit consisting of ay abd Cy retains te sampled voltage atthe output, Fig A2_ Credo ampli, ‘An important feature ofthis architecture arises from the virtual ground propety of node X: since inthe sapling mode the output volage of Gis also close to ground poten switch $ always tums off with a constant volt ‘age at its inp and outpat erminas, hereby injecting a constant charge onto {Cy and introducing a pedestal errr tha is independent of the inp signa [Asa rest this error appears primarily as an offset voltage and contites ‘negligible nonlinear. In order t reduce the offset resulting fom charge in- {ection and clock feedthrough, asepica ofthe sampling network can be placed atthe noninverting iu of Apso that the pedestal appears equally at bath of its inputs, ies as a common-mode voltage, This techniqoef ilestated for MOS switches in Figure 3.36], where Ms and Cp ae idemical with My and Cy, respectively. nthis et, My and M turn of simultaneously injecting chanel charge onto Cy, and C:. However these charge packets may not be2 SpleanldlllAmtcres Chap. 3 Fig. Closet oop samplant od cece wt pes anes exactly equal because My sees the output impedance of Gy on onesie whi ‘Mf sees the ground, Nonetheless, clock feedthrough components ofthe ped- estalsare equal and cancel ou. More accurate cancelation ofthe pedestals ean be achieved through the use ofthis achtectare in uly differential form 6) “The main limitation of closed-loop architecture arises fom its stabil- ity ad speed considerations. Since the circuit of Figure 8.2 functions as ‘two-stage opamp inthe sampling mode, the dominant pole piven by the ‘output impedance of Gy and the Miler multiplication of Ci must provide a reasonable phase margin so tht the output quickly racks the input with thee ‘uired accuracy. Asin atypical two-stage op amp (Chapec 7, several Factors Alegre the phase margin and, more import, the ott seing behav Joe Size Gy, and Ag usualy conibute several nondominant pols, some of ‘which may not be siciendy greater than the dominart pole seuing to high ‘ecuraces mabe slow. Furthermore. the pole given by the output impedance fof Ag andthe loacapacitance olen causes lng sting times. Additionally, the magnitude ofthis ole may vary with Ve ifthe output impedance of Ay ‘depends on the load curent, thereby inroiing output-dependent sting components (6. This effects discussed in Chapsr 7. “The above stability issues often necessitate conservative compensation ofthe closed-loop architecture so sto avoid undenfamped setling despite ‘variations in process, load capacitance. and temperature. Consequenty, this architecture does nt usually achieve the naximum potential sped of given technology. ‘Another drawback of hisarchitectre stemsrom the signal path rom Vi, to Vag through the input capacitance of Gi This pth introduces significant hold-mode feedthrough ithe capacitance between the input terminal of Gg is large ei the input tage of Guiles large deviee. The feednough is attenuated bythe outpat impedance of the unity-zain amplifer comprising ‘Aga Cir. But this impedance typically increases with the inp frequency, allowing larger feedthrough of highspeed signals, Se33.Open-Loop Acie with Miler Cputace s In summary, the closed-loop architecture suppress the input dependent ‘component ofthe hold pedestal by ineoporaing the sampling switch na fed back lop. This architecture, especially ina fully diferntal configuration. is attractive fr high-precision systems but usally suffers fom sow time response, 3.3. OPEN-LOOP ARCHITECTURE WITH MILLER CAPACITANCE ‘The conventional open-loop architecture described in Section 3.2 sues from fundamental imitation de tothe speed-precision trade-off ofthe sampling site given by (2.28). This tade-off ess rom the relationship between the on-resistance and channel charge of MOSFETs, indicating tat the hold pedestal can be reduced only if slower acquisition is acceptable. However, noting that these limitations exist imply bacatise the same capacitor is used forboth acquisition and hold, we ean avid them by using diferent capacitors in the sampling and hold modes. The open-loop architecture with Miller ‘capacitor is based on this concept and illustrate in Figure 348) (7), ‘Te circuit consists ofa sampling switch Mand an a-coupled Miler mpliiercamprising Ao, Ma. Cand C2. Inthe sampling mode, both My and ‘Mare on, As conigured as aunity-gain cireuit, providing viral ground at nodes X and ¥, and capacitors C; and Co track the put voltage (Figure 3.4b)) Inthe wansiton othe hold mode, fy and Meum olf simultaneously and CC, and Ap form feedback amplifier that introduces a capacitance of approximately AoC2 from node Z to ground (Figure 3.4()). Thus, in this architecture the hold capacitor is roughly AyC2/(C + C3) times the scquisiion capacitor thereby relaxiag the speed-prevsion rae off described in Seetion 23 by the same factor. Nove that since M always turns off with {virwal) ground potential at its source ané drain is charge injection causes negligible nonlinearity In this architecture, eventhough Ay must be a high-speed amplifier to provide alos” eutput impedance at high frequencies it nonetheless des not ee a wide dynamic range because its output voltae swing results rom only the charge injected by Ma, This simplifies ts design allowing optimization for speed In practice, the topology of Figure 34a) suffers from second-order sources of ero. Fist, ving their input-dependent switching point, Mi and Mz do not always tun of simukaneousl, thus eeating Miller ect either inthe sampling mode (hich slows down the aquisition and introduces Inputdependent delay) or after Ay has turned off and injeted its charge ‘onto Cand C> (in which ease the amplifier will not suppress the e709),Py Samples Hol Ahiecures Chap 3 Vout @ Vou Ge ° Fig.34 Opening atc wh Mile capac, Be eit (pjeqenaen ceca ine con mol (quae cet Second, when tring off, M and My iteraet through Cy and influence each others charge injection, making the charge injected by Mz somewbat inputependent. Nonetheless, Lins and Wooley [7] have shown thatthe nonlinearity introduced by this interaction is neligibe fr resolutions up 10 Sis. in summary, the open-loop architecture with Mille capacitance em- ploys two differen values of capacitance inthe aequisiion an hold moves to achieve high speed and small pedestal enor. This is accomplished using Miller ampli that mulipis the effective valu ofthe sampling capacitor by a large number when the SHA enters the hold mode, SoS Muto pa Archies s 3.4 MULTIPLEXED-INPUY ARCHITECTURES {class of SHA architectures employs input multiplexing to reconfigure the ‘iret when it goes fom the acquisition tothe hol made. In his section, we ‘describe two variants of this aehtectar, igure 354) shows the single-ended version of « multiptexed-input SH originally proposed by Ryan [8] and later mosified by Petshacher et AL [9], Icons of wansconductance amplifiers Guay and Gro abd transre- sistance ampliier R. Nominally, Gn} R = Gyo R= 1. Amplifiers Gyy and Guz ae comrolled (...mlipexed) by CK and CR. Duringsampling, Gn isenabled, Gyz is disabled, and Gy and R operate aba unity-gan ampli, allowing Vqq to Wack Vy. Note that the acquisition time constant is given Primarily bythe output sistance of Rand te value of Cy, Inthe tansion tothe hold mode, Gn is disabled, Gy is enabled, and Giga and Rare figured as « unity-ain amplifier, thecchy eaiing the sampled vale of 6708 Cr. Vino Gy Fig 3S Mukiplest ipa sche, a ingle-nda ci) ‘uct ect ie ol mse. {n order to illustrate the hold-mode operation, we consider a simplified version of the circuit, shown in Figure 350), where A= Gyo (1) and Ru topresents the open-loop output resistance ofthe amplifier. Assuming“ Sample aml Archies Chip 3 that Cy is charged toa voltage Vp atthe end of the acquisition mode and neglecting the input bas current of A, we noe: on sand @2) Ths Mew as Where # = RsCu/(1~ A) andthe origin of time isthe beginning ofthe hold ‘mode. Equation 3.3) shows that f 4 = I, then ¢ = 90: he the droop rate is zero and Vag will emain at Vo indefinitely. If A= 1+, then Ve decays witha time constant equal to RyyCir/¢; i; the droop time constant i 1/¢ times the acquisition time constant ‘Several aspects ofthis architecture make it atractive for implementa tion in bipolar technology. Fist, Ge and Gyn ean be realized as simple sifferential pairs that are multiplexed by means of a thie diferent pai, ‘lding a fst sample-o-hold transition and lw aperture jitter. Second, i Gm ad Gra are identical the charge injected onto the input node of by Gn atthe endat the sampling mode is absorbed by Gy, ths giving a smal ‘pedestal eor. Tir the Gy and & stages ean be implemented as 1ow-23, High-speed circuits because GR and G2 ned only be unity, This is particularly important ifthe proces provides no vertical pap transistors and Thence prohibits the use of high ain Sage, ‘While achieving igh speed, the architecture of Figure 3.5 presents Sv cel dificultes if employed for high-resolution appisatons. Since the ac- ‘Guistion time constant and the droop rate wade off according the deviation ‘of A from unity, Gg. Gigs and Roflen require correction techies 0 e- ‘duce that deviation (9} and approach the desired combination of acquisition speed and droop rate. Note that since this correction should remain effec ‘ve forthe entre input range, the nonlinearity (i, variations inthe gan) ‘ofthe cizcuit must be as low asthe gain error. These correction techniques, however, normally consume a substntial portion of the headroom, limiting the input voltage swing andthe dynamic range. For example, GR can be implemented as shown in Fighre 36 (9), where resistive degeneration in the emiters ad diode compensation in the collector of Qs and Qz are tilzed to achieve gan close ro unity (Chapter). Considering the voltage drop across emit and collector resistors and the headroom requied forthe clocked taileurentsouree, we noe that the input range han exceeds IV with Vex 3y, Seo 34 Muon pe Acie ” Fig.36- Linz ampere nope hop SIA. Another input-mulliplexed SHA architecture isshown in Figure3.7 [10] ‘This topology consist of transconditance amplifiers Gu and Ga mul plexed by CX and CK, tansresistance amplifier R, and sampling devices ‘5.81, Chand C. Inthe sampling mode, Gg is enabled, Gu is disabled, and Sand Sy aon, Thus the icuits configured as shown in Figure 380, ‘Gi R operates 4s & high-gain op amp, and the closed-loop gain is e9Ual 10 1 Ra/ Ry In ter words, Vag = (1+ R2/ Ri) Fes Samples Hold Acces Chap. 3 « a x) y or ig 38 ae cif dl op pen np siete) In the transtondo the hold mode, Gn i disabled, Gq is enabled, and 5} and tum of, yielding the hold configuration shown in Figure 3.80). Here, Vs ieclose 0 zero and Gyo and C; funtion a a unity-gain amir, hereby maintaining an output voltage egal that stored on ‘Theprincial feature ofthis architecture sits input independent pedestal or, This is because 5 and 5; donot experience lage voltage sings. they tum off wth Vy nd Vy closet the ground potential. Consequently, the nonlinearity intiuced by charge injection is quite small, Furthermore, i the sampling eapactor and witches are identical and the impedance in series ‘with Si (Ge the output impedance of Gui R) is smal, then the pedestal ‘Produced a the two inputs of Gu are equa. yielding zero pedestal atthe utp 13s instructive to compare the two multiplexed: input architectures de scribed in this section. While the topology shown in Figure 35 sufers from teade-ff between acquisition speed and droop rate—necessitating a Ga ® of precisely I—the topology of Figure 3.7 has no such trade-off, Moreover, since the later employs closed-loop amplifiers, i can achieve smaller non= Tinearty, but a the cost oF a potently slower time response, On the other ‘hand, both architectures have limited input range due to the stacked devices required for muliplexing. 535 RECYCLING ARCHITECTURE “The recyeing architecture is another topology in which the sampling switch experiences smal swings and hence introduce ply constant pedestal ero. ‘Shown in Figure 39 in simplified fom, this arcitetare consist of two unity iain blfers fy and By, trarsconductance amplifier Gy, and sampling ‘Secu compaising $)-B, and C|-Cs [11]. Inthe sampling mode, 8-8 are ‘on, Sis olf, ar the circuit is configured as shown in Figure 3.10). Tn this mode, Gy operates a a unity-gain amplifier. providing vial ground ar nodes X and Y. and capacitors Cy and C2 track te input voltage. Un the transition tothe hold mode, fst Sums of, at which instante input voltage is sampled on C (and C2), and subsequently SiS tum off and Stam on [Now the cteut is configured as shown in Figure 3.1046), where C2, Br, Bi and C) form uniy-zain feedback loop around Gre, thus providing an ouput ‘voltage approximately equal tothe voltage stored nC ts instructive to study’ the sourees of charge injetion inthis archi- tecture. Since Sy turns off with virual ground at X and ¥. it intrdces a ‘pedestal eror independent of the input signal, The resulting ost s partially balanced by the pedestal due tothe charge injected by S; onto C). Switch Ss. onthe other and, experiences swings equal tothe input and fjecs an Input-dependent charge onto nodes X, and Y when it urs off. Since By provides slow impedance at X1the charge injected onto this node gives 90 foe. However, the charge injected onto Vy chingesthe voltage stored on Nonetheless, the negative feedback loop suppresses the effet ofthis change «at the ouput. Thi occurs because the pedestal across C3 propagates through Bs, By, and Cand appears atthe inverting put of Gy thereby causing the ‘output of Gy to change inthe opposite direction, As result, the change in Vari equal to the pedestal voltage across C2 divided by the valtage gain of Give Ga Rays WHERE Rae the Output resistance of Gy« ample Hols Archieces Chap. 3 s 5% Ye ce, fon x % e eo cs o o ig 310 Euan ius of eying ice) Samping ode ‘i summary, the recycling architecture achieves small pedestal error, high ner and relatively high speed. 3.6 SWITCHED-CAPNCITOR ARCHITECTURE Evolved for use in AID converts he swiched-capacitor architecture em ploys MOS switches extensively. Stawn in Figure 3.11(a in single-ended Sec.36 Suits Caper Achiete « form this architecture consist of input sampling capacitor Cy. tanscondue- tance amplifier Gy, and switches SS [12]. The cireit operates as follows, In the acquisition mode, 5) and S) are on. Sis off, nd Gry functions as 2 unity-gan amplifier, creating vital ground at node X (Figure 3.110) ‘Thus, the voltage arose Cy tacks the input voltage. In the transition othe hold mode, st 5; tens of, thereby sampling the instantaneous input volt ‘age on Cin ad subsequently $) tums off and Sy tens on. This results in the hold-mode configuration depicted in Figure 3.11(c), where Cy and Gy sustain an cut voltage equal 0 the sampled input come) o © Fig AA Sich cqactor HA.) Bac ea (axa Inthe seston md) gaat eu ne Bl ma ‘Since inthis topology 5: tums off fist, the (input-dependent) charge injeted by 8, onto Cy doesnot appear inthe ld output voltage. Moreover, as Ss connected viral ground its chanael charge does not depend on ‘he input signal, In a diferent circuit, this charge would simply cause a common-mode oft, "The simplicity of this architocrre has made it quite popular in applica tions such as pipelined A/D converters, uere a large numer of SHAS are required [12] Since the dominant poe of the crcuit is usually athe output, ‘sn nrease nthe load capacitance doesnot degrade ie phase min but may ‘overeompensate the amplifier, Furthermore, a single-stage transconductance ‘mplifierean be wsed to achieve lnearities up to 13 bts [13]a Samples Hol bestees Cp. 3 In the architecture of Figure 3.118, te input suite 5) experiences large voltage swings, nioicng an inpat-dependent delay inthe acquisition ‘mode and hence harmoni distortion inthe sampled signal. Furteene, 28 ‘he linearity and precision of the SHA strongly depend on the open-loop gain (the product oftrnscondictance and output resistance) of Gy the peor ‘mance degrades if he circuit drives resistive loads, thereby limiting the use ofthe architecture to.on-chip applications 3.7 CURRENTMODE ARCHITECTURE CCarent-mode signal processing has been proposed as an aleratve 10 the ‘more conventional votage-made technique. Current-mode data conversion systems require curen-npat,curent-outPut sampling circuits. However. «even inthis case the signal is stored as voltage raber than a curent because ‘capacitors ae far easier to fabricate than are inductors. "Thus, in these a ‘chitectres, fist the input current mast be converted 0 volage so that can he stored, and then the stored voltage mist subsequently be converted to an ‘ouput curtent "The closed-loop architecture described in Section 3.2 canbe easily mod ied to operate in the curent mode, as sown in Figure 3.12. A variant of this architecture has heen used in a cureni-mode A/D converter 4]. In this ‘cit the inverting input of Gig i grounded, th input current is summed withthe ouput current of Gy at node X. the signal is stored on Ci and the output current is produced by Gina. The closed-loop architecture isa natural choice fr curreat-meode signals because, inthe sequisiton mode, ‘vides a vintal-ground summing node (X) as well as an iteral current to-volage convener (consisting of Ap and Cy). Note that Gua i ouside the global feedback loop its distortion is directly added f0 the stored signal. Fg AID Care me HA dered fm coment op ah The architecture of Figure 3,12 i topologically identical with the con- ventional elosed-ooparchitectre and hence exhibits the same time response for both curent-made inputs and voltage-mode inputs. Consequent, the curent-nodearchiteetre faces the Sune stability issues a the vollage-mode chinese REFERENCES [1] K.R Stafford eral, “A Complete Monolithic Sample/Hold Amplifier” IEEE 1. Solid-State Circus, vol. SC9, pp. 381-387, Dec 1975 [2] MJ. Chambers and LF, Linder,“ Precision Monolithic Sample-and- Hold for Video Analg-to-Digita Convers," ISSCC Dig. ech. Pup, Pp 163-169, Feb. 1991, [3] K- Poulton, JS. Kang, and JJ. Corcoran, “A 2 Gsls HBT Sample and Hold," Tech, Dig, 1988 GaAs IC Som. pp. 199-202. [4] P-Vorenkamp and J PM, Verdaasdonk, “ally Bipolar, 120-Msample/s loch Track-and-Hold Circuit.” EEE J. Solid-State Cir, vol, S27, 1p. 987.992, July 1992, [5] R,Jewet, J.J. Corcoran, and G. Steinbach, “A 12 b 20MSIsee Ripple ‘Through ADC ISSCC Dig. Tech. Pp. pp. 34-35, Feb, 1992. [6] M. Nayehi and B.A. Wooley. 10 Bit Video BiCMOS Track and Hokd Ampliier” ISSCC Dig, Teck Pap. pp. 68-69, Feb. 1989, (7} P..Limand B.A. Wooley,“ High Speed Sample-and-Hold Technique Using a Miller Hold Capacitance," IEEE J. Solid-State Circuits, vol SC: 26, pp. 643-651, April 199] [8] C.R. Ryan, “Applications of Four-Quadrant Mulipli State Cireits, vol, SC-5, pp 45-48, Feb, 1970, [9] P.Peschacher etal, “A 10:D75-MSPS Subranging A/D Converter with Integrated Sample snd Hol." IEEE J. Solid-State Circuits, vol. SC-25, pp. 1339-1346, Dee. 1990, [10] F, Moraes “A. High-Speed Curent-Multiplexed Sample-and-Hold Amplifier with Low Hid Ste." IEEE. Solid-State Circuits, vol SC-26, Pp. 1800-1808, Dee 1991 [11] P. Real and D. Mercer, “A 14 b Linear, 250 nsec Sanple-and- Hold Sobsystem with Se-Calibyation;" ISSCC Dig, Teoh Pap. 99. 164-165, Feb. 1991, IBEE Soli“ Samples ol Accor Chap 3 [12] S.-H. Lewis and P.R. Gray, “A Pipiined S-Msamplels9-bt Analog ‘o-Digital Convere:” IEEE J. Solid State Crews, SC22, pp.954-961, Dee. 1987 (3) YM. Lin, B. Kim, and PR. Gay, "A 13-b 25-MEy Self-Calibrated Pipelined A/D Converter in 3m CMOS)" IBEE J. Solid State Circuits vol, SC-26, pp. 628-636, Ape 1991 [14] D. Robertson, P. Real, and C. Mangelsdorf, “A Wideband 10-bit, 20, Msps Pipelined ADC Using Current-Mode Signals." ISSCC Dig. Teo Papers pp 160-161, Fek. 190, 4 Basic Principles of Digital-to-Analog Conversion Digital-t-analog conversion is an essential function in dat processing sys tems. Asmentioned in Chapter I D/A converters (DACS) interface the ital ‘output of signal processors with he analog world. Moreover, as explained in ‘Chapter 6, mulistepanalog-to-dgital converters employ interstage DACS to ‘reconstruct analog estimates ofthe input signal. Each of these applications imposes certain speed, precision, and power dissipation equirnents onthe DAC. mandating a good understanding of various D/A conversion techniques and thei ade Tnthis chapter we study the basic concepts and operations related to DYA conversion. Following & definition of performance metres we describe DYA conversion in terms of voltage, curent, and charge division or mulipiation Aandillustat the merits and imitations ofeach approach. Finally, we discuss the switching functions needed to generate an analog output coresponding to digital input 4.1 GENERAL CONSIDERATIONS A digia-to-analog coaverter produces an analog output A thats proportional tothe digital input D: Azan. a“ as Pips fig o-Antog Cooeson Chap where a isa proportonaiy factor, Since D isa dimensionless quantity sets both the dimension andthe full-scale range of A. For example fe isa current quantity, Jy thea the output can be expressed as A= be, 42) In some cass, its more practical o normalize D with espect to is full-seale value, 2, where m isthe resoltion, For example fa isa voltage quantity, Vier: > An Very 4s e y From (42) and (4.3), we ean se that in a DUA converter, each code atthe git input generates a certain multiple or fraction of a reference atthe ‘analog ouput In oer words, DVA conversion canbe Viewed as a reference ‘multiplication or division fnction, where therelerence may be once the three clectical quantities: voltage, curent, or charg The accuracy of his funtion ‘etermines the linearity ofthe DAC, while the sped at which each multiple or fraction of the reference can be selected and established a the ouput gives the conversion rate ofthe DAC. Figure 41 shows the inpuvoutput characteristic fof an ideal bit D/A conver. The analog levels generated atthe ouput Follow a staight line passed through the engin and the fllscale point. 000 001 010 O11 100 Tor 110 111 Digital Input Fie lpaouput chris of a el DIA come ‘We should mention that in some applications such as “sompanding” DACs, the desired relationship between D and is nonlineae [1], bu in tis ‘book we discuss only “linea or “uniform” DACS, ie. those that ideally ‘behave according 0 (4.2) oF (43). S42 Perfrmne Mei ° ‘The digital input o 4 DAC can assume any predefined format but must, eventually be of frm emily converible to analog. Shown in Figure 4.2 are twee formats offen used in DACS: binary, thermometer, and Lof-n codes. The later two are shown in column form to make thei visualization eas: Decimal | 0 1 2 9 Binary oo wn mete | 8 9 8 fF ‘Thermor oe of 44 88 8 t ad oo 1 0 ee) ig. 2 Binary herons and of cs the binary format, an m-bit number D1 D>» Dy represents decimal value of D214 Dy-22"-2 4 + Dy Inthe thermometer code, number is represented by a column of j consecutive ONEs tthe bottom and k consecutive ZEROs ontop such tht {J+ kis consiant. For example, a shown in Figure 4.2 the decimal number 3 can be represented as three ONE and one ZERO. This code an be viewed 884 thermometer thats “illed” upto the topmost ONE in the column, and hence the name. We wil also se the trm “eight o refer the numberof (ONES inthis code, Inthe of code each number is epresented a a single entry of ONE. in a column of ZEROs, with the position of that entry showing the actual vale. In Figure 42, for example the decimal number 3is depicted asa ONE. {in the third postion from the bottom, ‘As seen fom Figure 4.2, the thermometer and -of-n cade are much Jess compact than binary. Nonetheless, as discussed later, these codes are essential in DIA and AD converter design 4.2 PERFORMANCE METRICS In this section, we define a numberof tems usualy used to characterize BYA comverers. Fara more complete st, the reader is refered 10 the literature“ asi Pitino igi Ansog Comenion Cup. (2, 3] and manufacturers" data books. Figures 43 sad 44 illustrate some of these metres, « Differential nonlzearity (DNL) isthe maximum deviation in he out pul sep size fom the ideal valve of one least significant bit (LSB), nat Outpt onter ise. r Dita Fig.A3 Siac amc of DA comer Fe.44 Dynamic pametes of DIA comer, Sec43 Referens Micon nd Divison ” + tntegral nonlinearity (INL isthe masimum deviation ofthe input put characteristic from a straight lie passed through its end points “The difference between the ideal and actual characterises wil be called the INL profile + Offset isthe vertical intercept ofthe straight ine passed though the end points, ' Gain error isthe deviation ofthe slope ofthe line passed through the fend pis rom its eal yale usualy unity) ‘ Seuling time isthe time vequired for the output t experience Full scale tansition and sete within a specified error band around is final value, Glitch impulse area isthe maximum rea under any extraneous glitch that appears at the eurput after te input code changes, Thisparameter isalso called “ght energy” in the literature even ough it does not have an energy dimension * Latency is the total delay from the ine the digital input changes to the time the analog output has Setled within a specified errr band around its fina value. Latency may inclade multiples of the clock Petiod i the digital logic in the DAC is pipelined. ‘ Signal-t-(nise + distortion) ratio (SNDR) isthe rato ofthe signal power tothe ttl noise and harmonic distortion a he ouput when {he input is a digital sinusoid. Among these parameters, DNL and INL are usually determined bythe sccuracy of reference mullipication or division, settling time and delay are Functions of atput loading and switching speed, an etch impulse depends fn the DIA converter architecture and design [Note that some of these garamerers may’ be more important in some applications than in thers. For example, many stand-alone DACSequire low hich rea but may tolerate long latency. Onhe other hand, DACS uilized in ‘AID converters usually reguite short latency but ay havea claively large eliteh tea, 44.3 REFERENCE MULTIPLICATION AND DIVISION ‘The linearity and SNDR of DIA converters strongly depend on the acc racy of the eference multiplication or division employed to generate the ‘output levels. The thee electrical quantities, voltage, current, and charge,«an be multiplied or subdivided using resistor ladders, cument-steeringcir- cuits, and switched-capaitor circuits, respectively. In this section, we de serie each of these technique and th eros tha aris in typed implemen- 4.3.1 Voltage bi A given reference voltage Vay cam be divided into N equal segments using alader composed of W identical resistors Rp = Ry =o" = Ry (Nis ‘ypically a power of 2) (Figure 4.5). An m-bit DAC requires a ladder with 2" resistors, manifesting the exponential growth of the numberof resistors a a function of resolution Yer my Fs : Aya Fg === Fy % R, % a ig. age vin wing reir aie ‘An important aspect of resistor ladders i the diferential and integral nonlinearity they induce When used in DYA converters, These eros est From mismatches in he resistors comprising the ladder In order to undeestand bow resistor mismatch affects the DNL. and INL ‘of a resistor ladder DAC, we fist considera simple ease where the ladder ‘exhibits incar gradient, i, a linear variation in doping or wih from one fend othe other: This sitvation is shown in Figure 4.6. The voltage at the jth {ap of this ladder is 43 Reeee Mapleton a re s Yer ewer % noaon % ean % n AS Lr patron Surkan Wee Ver an Desk am w=» nr EY ag - Oe Vi as) Net aR ‘The INL ple is he by he difeence beeen.) ante ea tp vag. “1 ye YD on Lie apn 8 aaya fs Pips of Dipisen-AmlogComenion Chup. Assuming R > (NV ~ 1)O./2, we noe that [WL reaches @ maximum of NViee(R/SR) at j = 1/2. or the linear grant depicted in Figure 4.6, the DNL is obtained by fing the deviation of V1 V fom the teal valve of 1 LSB (=Vian/ 9) Veer DNL = Vet 4s) hich can be simplified to AR Vue Dey = j- 95) SE a9) if we assume R > (N ~ 1) AR/2. For lmge N, the magnitude ofthis eror reachesa maximum of approximately Vagr(O R/2R) at j Nol ‘Not that ifthe maximum INL and DNL ound above are toemain below 1 LSB, then the assumptions made in arriving a (8.7) and (4.9) are justified, tis imeresting to note that the nonlinearities deserted above ae caused by perfectly linear resistors, This ofcourse does nt contradict any las of linear systems because the switching operations in D/A converters make hem inherently nonlinear systems. ‘While the ease of linear gradients is simple and intuitive, i reality resistors also exhibit random mismatch. This type of mismatch originates Primarily fom uncertainties in geometry definition daring processing, a well, asrandom variations in contact resistance. Consider two resistors laid outwith ‘dential geometry and dimensions Inthe ideal ease, the value of each resistor can be expressed as sae, a where pis the resistivity, L, W, and are the length, width, and thickness ‘ofthe esistors respectively, and Represents the additonal resistance due 19 each contact. In reality, these resistors suffer fom several mismatch com ponents: resistivity mismatch, Ap, width, length and thickness mismatch, ‘AW. AL. and Av. spectively. an conact resistance mismatch, Ac. Ina typical process, AW and A result fom limited edge definition capability lithography and etching or deposition ofthe resistor material AV arises from _raientsaross the die, and 4 is eaused by random variations in the finite resistance at the interface ofthe fsisto and the interconnect (usually meta) “Taking the total diferent of (4.10), we ean express the overall mis- match between the (Wo resistors 8 Lap pAb pLaW _pLar ara Eee, 28 2ARe. (4.10 wr * wr we * iy This value can be normalize tothe mean valu ofthe resistors, R, to yet the relaive mismatch. Since in (410) 2Rc is usally a mal fraction oF, See Reece Maipcatin and isn s th fit four terms 4.1) canbe simplified by substiting 9/1 fo AR 89 ab AW ar , ake Rpt EW rR Since cont resistance dereses athe eestor wid increases, we cam write Re-=r/W, where a proportionality facto, This, BRe ~ Ar/ W. suggesting tat 12) ean be writen as AR _ Ap, AL AW ar sar eae ae Ae at ine 43» Ina ypical process, panda give, leaving LW, and R asthe only variables under the designer's conto. To minimize the overall mismatch, each of these parineters mst be maximized OF course, larger dimensions tea to higher parasitic apacitance Between the resistor and the subst, a wellas larger chip area, Some props of commonly availble monolithic resistors are given in “To analyze the nonlinearity resulting from random resistor mismatch ve must (1) assume @ probability density funtion (PDF) forthe value of ach resistor, (2) calculate the resulting PDF forthe tp voltages along the ladder, and (3) examine the mean standard deviation of these vollages in terms of those ofthe resistors. Since random mismatch aries from a large number of random variables (eesponding wo many uncorrlatedevents uring fabrication) itis plausible o assume a Gaussian PDF forthe resistor ‘values. Using such an analysis, Kuboki etal. [S] hae shown that the ap voltages of a resistor Laer follow a nearly Gaussian distribution, wih 4 ‘eae 0 jVig/ Wan standard deviation eal o any puna (Tad, 8k hr ay Tis reach maximum of Lar Wha = EV Vin R oy at j = 9/2. We souldemphasie ta this vale is standard deviation and hecea ikelnond measre rater than adsterminstic number nae words itimplis atom the average, 685 of N-segment resistor adders exhibit an ‘ores than or equa to (Vgey/VAN)AR/R) at ther midpoint Figure 47 ‘depicts an INL. profile obtained by choosing cach esitor ofa 12¥-segment ladir fom a Gaussian dsttation with R= 100 and AR = 3 2. We bots that inthis proflethe mama err does na eer at he pin a is actualy rete than that predicted by 13).= Hse Pris of Digan AniogComeriny Cag 10 os 00 me (U8) os 2 2049-60 8) 100 120 140 Ladder Tap Number He? NLmalstssrcompie seeds Despite the counterexample of Figure 4.7, equation (4. (5) dees indicate rend: 0 long a6-2.2/ remains constant the maximum enor decreases if ‘increases. Thus, ladders wih alarge numb of Segments are more likely to achieve a small (absolute) nonlinearity than ae ladders with a small number ‘of segments, Inuitvely, this is because random errors inthe value of resistors tend to average out when many segments are connected in series "Walton to random mismatch, ladders made of difsed resistors ex hibitawistnet nonlinear eration. The chickness ofthe depletion layer under those resistors volage-dependent and Yates from one ed ofthe ladder (0 ‘he othe, thereby introducing a variation in the value ofthe esis segments ‘The suing nonlinearity can be caleulated by expressing the thickness of| the resists asa square rt Tunetion ofthe local voltage along the ladder Note tha asthe diffused resistor doping increases, this nolinerity decreases, ‘whereas the depletion layer eapacitance-—which appear al along te ladder to the substie—incease, This vade-off makes diffsed-resistr lade less attractive than pol)-resstor ladders in applications where the ladder ex: Periences transient and mos ecover quickly, ‘An important aspect of resistor ladder design isthe Thevein resistance seen at each tp along the ladder. This resistance determines how fast ca ‘active loads charge or discharge to each tap's inal voltage. coneribucing (0 the setling time ofthe BAC. For an N-segment ladder, the Theveni ress tanee reaches a maximum of 4 R/4 a the midpity, This resistance grows exponentially with the number of is but canbe reduced atthe cost of higher power dissipation, Several variants of the resistor ladder sbowa in Figure 45 have been used for D/A conversion. We wil desribetheve in Chapter 5, 43.2 Current Division A reference current fay can be divided into W equal currents using N ‘identical ansistors connected as shown in Figure-48(a) (The same principle applies to both bipolar and MOS devices) These cumeots cube combined 50. © provide binary weighing, ss depicted in Figure 4 8(b) for &3.it ‘example. this simple implementation, an m-bit DAC requires 2" — 1 transistor, resulting ina lage numberof devices form = 7 noth j Ww Incr f@ a 21 ty er e480) Union cur dvs Ny cnet son Wie conceptually simple, the implementation of Figure 4.8) has two. eawsacks: the stack of current viding transistors ontop of fe iit theBasi PiniplesofDipiatte Ansog Comenion Chap & ‘output voltage range, and gy must be Nimes cach ofthe output currents ise Fe equites avery lrg device itself “These problems ean be solved by curent replication (eater than dive son) as shown in Figure 491), where V current mirors generate N output ceurreats equal 0 Ir- In practice, to improve matching aod Hiner, d= enero resistors are placed in sever with the emir, yielding he clreut shown in gure 5b). This wll be discussed ltr, a AAs Figures 4.8) and (b) may suggest, current-steeringarays can be implemented in two diferent ways, using esl oF binary-weighted curent Sources. Figure 4.10 depicts these two cases in more general form, In the circuit of Figure 4.10(), ll eurent sources are equal and controll by thermometer code so that wien the digital input increases by 1 LSB, one ‘aiionaleuzrne source is Switched t the output. Inthe circuit of Figure 4.1005). the curteat sources are binary-weighted and controlled bya binary ‘ode s that each current source contributes to the ouput current twice that ofthe next less significant bit. The configurations of Figures 4.10) and (b) ane called “segmented” and “binary” arays, respectively "Animporant feature of segmented arays is their guaranteed monotonic iy: since irements atthe digital input simply cause an ative increment Se.43— Refeene Muipieson ad Dison a ‘mene Cot Ps Bo a boar cota ‘9 M660 (ener eg at the analog output, the sansfer characterise of such arrays sa monotonic une ofthe input, even if the maximum INL exceeds 1 LSB. In binary mays, on the other hand, when the MSB current source [ef in Figure 4.10(0) tums om anda the curent sources corresponding to lower bits ura ‘othe ourput may change by nore than LSB, As rest bigh-resoltion applications such as stain gauge sensors, where the nonlinearity ofthe cane cer tse large ad hence the converte linearis ot erties, segmented nays are more altactne Because their resotion (iffrentil linearity) is ‘elaively independent oftheir integral inert ‘The overall output curent ofa current steering array ean he converted ‘0 voliage using resisor ora transimpedance amplifier, shown in Figure= Basi Price Digha o-Anlog Cerin Chap 4 4.11. tn Figure 411), a single resistor Ry convents the curent to voliage “This resistor can be 2 5042 offchip load if the DAC is 10 drive exter circuits. In his as, the fllscale ouput eurent must be sufiintly large to produce reasonable vollige stings across Rj. Note that the output sting speed is limite dy the total parasitic capacitance Cp at node X hecause this node experiences the entre Output voltage sing. ‘ranlnpedonce "iner * [| Ce cept flow fea = Caren Satna Caen sing ‘hey ‘ir Fig AML Comer of ouput cet ofan ry volgen (a feta) sensed amir, In Figure 4.1100, resistor Ry isplaced ina feedback loop around op amp ‘A to establish a vinta ground at node X. Asa eeu, voltage variations at 1X are quite small and the output sein s determined bythe op amps speed. As discussed in Chapter 7, various trade-offs among sped. inary opt voltage swing, and driving capability of op amps often restrict the dynamic range and seting speed ofthis topology. Consequeat. the approach in Figure 4.11(a) is more common in hgtespeed applications Digitaly-anslog converters that employ curent-stcering arrays sufer fo ae ores of molar: are sore, mismath nie oa impedance of euret soures (othe nonlinearity ofthe following ransimpe nce ampli) and voltage dependence ofthe load resistor that converts the ‘output current to voltage, Current Source Mismatch. Tye cutent sources in an gray may ex- hibit mismatehes due to grens or fandom variations. The effect of grai- cents can be sued in the same fashion a for resistor ladders Seetion 4.3.1) Hence, we consier any random mistuatches her, ‘Consider two nominally identical eurrentsourcesimpemenedas shown in Figure 4.12, The output cuteas )and fs exhibit mismatch components Se) Relgene Maipison ad Divison - ue to mismatch between current gis and everse saturation eatents of Q) and Qs a well mismatch between Rey ad fy, can be shown [6 thet thetelaive mismatch between fy and fs At 1 als, sae au ate Tyee Ty at ewhc a Re M18 ‘where 1/5 and At are the standard deviation ofthe everse saturation eu rent and common-base current gain of Qy and Qs, respectively, Ay the ‘andard deviation of Rey and Rez and the same quantities wibout reps resent the mean values. "The wansconductance of Qy and Qs. Sw * 1/ Vrs where Ve = KT /g Fie AL Noninaly deca tga 1isinsetiew comin etree cases: (1) es Rea & Wm and) Ren Rrs> Hae ie tne, at, als TO i, the curent mismatch s determi by tani geometry matching. Since /sisprpotonal tthe cmiseratsof and Osean moma decease ger deve sed i tl Yas hs at fon the oder of $10 10% Tn the second case, an Al 1 Als, Aw ae Take ts a Re? ou Ae ARs (9) a Re 7d ‘ce. curent mismatch result from mismatch heween curent gains of Qy and (0: and between values of Re at Reo si Piles of Dita AtlogComesion Chap Since the common-emiter crn gain suse more commonly than swe note that = (8+ 1) and aa (420) Forge aetan oeF5 aan suggesting that relative mismatch ine is equal to relative mismatch in ivided by f. Fora typical 4/8 of 10% and 8 = 100, Aaja ~ 0.1%, As the second term in (4.19) also onthe order of 0.1%, we ee thatthe ourpat ‘urret mismatch nthe second case is only a few tenths of percent i. moe than an order of magnitade lower than tha in the ist case Tei imporant to note that in smal-zeometry transistors the emitter comic resistance (inhiding contact and intensie components is quite large und varies considerably from one device to another. This variation introduces Significant mismatch between the output cutens in the ist case, whereas itadds to. Rp—and hence is suppressed by a factor of Re~in the second ‘While increasing the sizeof the wranssiors reduces the ero in (4.17). also resis insubstantial collector substrate and collecor-bae eaacitance, thereby slowing down the switching For the above reasons, the second case is usually prefered, Another advantage of using emitter degeneration is higher outpu impedance, which ‘edces the integral nonlinearity as discussed ater, InCMOS technolog,curent sources are implemented using MOS tran sisiors [Figure 4.13()] Assume M; and are nominally iden and have square -V characters ew) To = ula Ws Vo a2 ‘where isthe carrier mobility in the channel, Cite gate oxide capacitance ‘erunit area, WV and Lae the device effective width and length respectively, Vos isthe gate-source voltage and Vey isthe threshold voltage” We ean find the relative ouput curent mismatch By taking the total ifferenial of (422) and dividing the rest by AL _2AVn TE Ves Yan 423) S43 Refence Matipicaionand Dison @ » ig 13-Nomily enc MOS care scan. Since 1C and Vip ae constant for a given pocess, W, Land Vas ae the only parameters under the designer's conte, and they ean be increased 1 lower AZp/Tp. However, lager W leads wo higher drain-substate and gate Aran capacitance and larger area, larger & requires higher Vis ~ Vi toatain a gen Zp, and increasing Vox ~ My limits the voltage swing atthe drain OF My and’ Ms, Asa consequesee, some compromise is usualy necessary to obtain a reasonable combination of accuracy. speed, and output voltage swing. Also, note tha a Wand L increase, both A(j¢Ca) and AV tend to werage out over the gate area ofthe transistors and hence become staller m1, Forshor-channel MOSFETS(L. < 2m), the/-Veharacteristies deviate from the square law because of velocity saturation, mobility degradation due to verical fel, and threshold voltage variation with drain-soure voluge. ‘Asan exteme case, let us assume very short channels and heavy’ velocity saturation, Then, I % Wal Vos ~ Vin (424 here ta isthe saturation velocity of carer (8). Thus ty _ a(Cara) , AW An To Gata W~ Vea Vn - inating the same weds (4.23) excep ht he mismatch sind oe For MOS urea sources, tis posible we sure degeneration ssn aah in Figure 150) [9]. However hme he chi Siento ao hese exer comple wth vere fe rancondcance ofthe MOSFET. To usa why oe that Figure 4130) wecan writee asc Pipes of Dial o-AmlogComension Chap. 426) ‘where all quantities te mean values. Taking the oa diferensal both sides and substituting gm = YTACWTOTL = 2o/(Ves ~ Vru)e We have Alp 1 ,AluCa) | AW AL _2AVy = To" UeaaRs! wat WE Vog— Vm 7 2831 427 ‘The frst four tems in the square brackets ar the same a8 those in (4.23), ‘but tei effect is divided by 1+ fs. The last term represents aoa mismatch contributed by £41 and Ro themselves. This equation indicates that source degeneration is effective only if gy Rs is comparable with (and preferably auch greater than) unity. Since fr given Ve and Jp the value of Rs cannot exceed (Ves ~ V>n)/Jox large ms meats a high kn Which in tum demands wide transistors ‘The effect of cutent source mismatch on integral linearity can be ana Iyeodin the same manner as nthe case of resistor ladders Seetion4.3,1), The itmportan results that asthe numberof current sources in the ata increases, ‘he relative nonlinearity decreases because random errors tend to average ou. Finite Output bnpedance of Current Sources. IF the output caren summing node oF currentsteeringaray experiences large vollage excursions [eg., Figure 411(a), then anaer type of integral nonlinear rises from the finite ouspt impedance ofthe current sources, Inrively We ote that, asthe output varies between 7 and Tulsa, different impedances are ‘Switched to the ourpr nae, therchy ntodacing variations inthe equivalent Toad resistance and hence nontinerity in the ouput voltage. As an example, we calculate tis noslnearity for a segmented ara. ‘Consider the small signal equivalent circuit shown in Figure 4.14, whore re feresens the output impedance of eachurrent source. Focathermomet code of eight j the sutpt voltage is HR. (4.28) “The dependence ofthe term in parentheses introduces integral nonlinearity ‘To obtain the INL profile, we ps straight line though the endpoints of Se43Refrease Makigiaton and Dsio « ‘hich has a maximum of REN? ro, Since he fullscale ouput ol approximately eval to N17, the maximum relative nonlinear sequal to [NR\/4r9.Asthis value must be very small, he asumption made in aiving 54.29) ali Fie d.6 Cureaonng ary inating ap ipa eh arn Load Resistor Nontinearity. Another ype of nonlinearity in caren steering arays stems from voltage dependence ofthe load resistor [4 in Figures 411(a) and (b)]. Poyslicon resistors exhibit a hyperbolic sine 7 ‘characters that becomes more lincar as the length of the fesistor increases {10}. In ditfsed resistors, onthe other hand, nonlinearity originates trom the Sariation of the width ofthe underlying depletion region ais primarily Function of doping levels, For lnearites above 10 bis, these effects and their temperature depen- ‘dence must be accurately measured and characterized foreach press 43.3. Charge Division A reference charge, Qtyy, can be divided into N equal packets using W identical capacitors configured asin Figure 415, In this circuit, before §, ‘ums on, C; has a charge equal t Qn. while Cs... Cy have 2er0 charge ‘When 5) tums on. Qn is disuibued equally among Cy... Cv Yielding charge of Oper N on each, Further subdivision can be accomplished by Aisconnecting one ofthe capacitors fom he arta andredistibutng ts charge among some other capacitorso ‘ai Pics of Digs o-Anlog Comerson Chap 4 wwf ted rpot Fig AS Simple chze ion While the cicuit of Figure 4.15 can operate a8 a DIA converter if a separate aray is employed foreach bit ofthe digital input, the resulting ‘complexity prohibits use foreslutions above 6bis. A mediod version of this circuits shown in Figue 4, 16(a). Here, identical eapacitrs Cj = += (Cy = C shaethe same tp plate and their bottom pats canbe switched trom ground toa reference voltige, Vas, acording tothe input thermometer code Im other words, each capacitor ean inject a charge equal t0 CVger onto the ‘output node. thereby provucng an output voltage proportional to the height ofthe thermometer code. The circuit operates as follows. First, Sp is on and the Botom plates of Cy...., Cy ae grounded, discharging the array t0 ze [Figure 4.16(b)]- Nex. Sp rms off, and a thermometer code with eight j ‘is applied at Dy... Dy. thus connecting the bottom plate of Cy... C) 4 Veur and generating an output equal 0 Vaan) N [Figure 4.16()) ‘The circuit of Figure 416i, i the src sense, oliage divider eater than a charg divider. In Fact, the expession relating its oun! vata to jure the value ofthe capacitors i gute smart hat of resistor ladder. Nonetheless, in easiering nonlinearity and loading effects i is helpful to remember that the circuit's operation is hased on charge injection and reds. tnbation ‘As with currentstessing DACs, capacitor arrays ean be configured in cither segmented or binary form, ‘The example considered in Figure 4.16 Js.a segmented array, with the important property of having a monetonic inpovoutput characteristic, Shown in Figure 4.17 binary version, where the digital input assumes binary format and unit capacitors are groupe 48 to provide binary weighing. ‘The operation is similar 0 that of Figure 416, [Nonlinearity of capacitor DACs arses from three sources: capacitor ‘mismatch, capacitor nonlinearity, andthe nonlinearity ofthe junction capac. itance of any switches connected to the output node Capacitor Mismatch, Mismatch in an stay of capacitors rises fom both gradients and random variations. Te effect of gradients canbe fora Seo 43 Relea Mulipicaton nd Divison « ° Fig. 416 a) Matis rs ssn conga: (cit of in shrge mse) hoof nae ae lated inthe same manner as inthe case of resistor ladders (Section 43.1), ‘Thus, we discuss only random erations here. ‘Consider two nominally identical monolithic capacitors. Du to di mension and oxide thickness mismatch, these capacitors exhibit a relative“ Base Pies f Digi Ang Conversion Chap ¢ iA? Charge dso wih iy tli risa of ac _aw a Cow Te where AW/W, A/C, and Atay ae elatve mismatches inthe with Tenth, and onde tikes, espectely. This expression indicates that i ‘Seas W.oc improves the matching. In pate, a constant athe pres, leaving W and Ls the oly variables, However, increasing Wand docs nt reduce AC/C indefinitely Beats aliens become more significant tlre dimension and ruse the hed term in (4.30. AS ‘Teamsequence, AC/C reaches a minimum at cenain optimum dimension {12} Although proces-dependent, these denon ae usally inthe ange 1201030. Toimpove the mating between large capacitors common- Cento germs canbe se 1) “Me eet fandom capacitor nsnatch on the veal inert can be analyze in shin sir otha for resistor ladders in Seton 43.1. We ove tat th ines linearity improves as the mum of eapaciors in the tay iceases because random errs end 0 average out 420) Capacitor Voltage Dependence. Another source of nonlinearity in capacitor DACS is capitr voltage dependence (11). Figure 4.18 shows the Structure of a typical monolithic eapcitor consisting of to (oped) poll icon plates separated by a dcletic (usually silicon dioxide). The voltage dependence originates rom te variation of bot the dielectric constant, Sec43Refeense Maipicon nd Divison o and the thickness of the depletion region within each pate (11, 13). Since the ‘actual expressions fortis dependence ae often quite comple, is commen practice to model the nonlinearity with «polynomial (Taylor expansion) Sch as C= Cyt Coan + Cute? aan where a i the jth-order voltage coefficient ofthe capacitor. Is important to noe thatthe representation in 431) does or mean tha the tal charge ‘ona nonlinear capacitor is equal othe product ofits voltage andthe value of the capacitor at that yttage. Rather (4.31) simply shows that ifthe eapacitor has. voltage then an increment of voltage. dV, requires an increment of charge, given By a Coll Hen Hav? +a. 432) ‘Consequently, the toa charge needed to change the voltage of a capacitor from Vj to Vas sone fd tavsartsow, aay potyeieon 7 [nnd eotiog Fig 418 Tyla mooie cpan sete. For most applications, the fist dee terms in (4.31) represent the ea pacitor nonlinearity with reasonable accuracy. n single-ended crus, a is ‘sully the dominant factor, whereas in differential configurations the effect ‘oft is significant because the even-onder nonlinearity components resting from ay are suppeessed, [Asanexample of computing INL due to capacitor nonlinearity, we ana Iyzethe effect ofa ona segmented capacitor aray. Foran input thermometer cove of height jth equivalent cteuit of Figures. 19 canbe constructed. Here, the charge on C) must equal that on C2, and asthe output goes from zex0 (0 its fnal vale, the voltage aross Cy changes fem 7e0 10 Vary Vea that 267085 C> from 20 t0 Vi. follows fom (4.33) that [0-000 senna =f jeua seiner, 430* Basi Pips of Digtao-Anog Cmeniso Cha. Vout w= ewv) ig 419. Equi io of seed capaci aay with a ep Ibemoraer code of Ba CCarying out the integration and solving for jVqe/N (he ideal inpuvourput characteristic), we have Von 2 2 a Waar — 24 Vag + 2a Vir Vir For typical values of) < 100 ppavV and Vaya Vou = $ Vth las three opi % terms in the denominator of (4.35) are uc Tes than 2 ad hence i veer = fa 435) 4 4s) i ai ova ae Vou = nor — Wan + 43 Fleer Naw = Ty — Want Gt 430) ‘This equation canbe ewriten as Jive, 4 tomy avi 4 2 w= Veer + 2S (Ve — Mo asn “The second term vanishes Vg = Od Voy = Vass and it represents the nonlinearity in the transfer characteristic, This term reaches a maximum of i Barve as) 36 430 INL at Vag = GVM. ‘The above analysis can be peated for binary ars na similar fashion 14. Switch Junction Capacitance Nonlinearity. The third source of INL in capaciter DACS isthe nonlinearity of the junction capacitance of the ‘sich(es) connected 1 the output node (eg, Sp in Figures 4.16 and 4.17), ‘The variation of source of dein junction capacitance of MOSFETS can be expressed as % Sm = TH FOP aay) Sec.43 Referens Mikipicaon ad iiss ° where C) isthe zero-bias capacitance, V8 the voltage across the ution, isthe built-in potential, and m;istypically between 0-3 and 0.5. For analysis purposes, we can appraximate (4.39) with an empirical polynomial such as % vy, Con Cal 0.1m jC)? = 063,072) + 1 aan) ‘Thisrelationean be used io estimate the nonlinearity fora given voltage swing tthe output. The analysis i simi that performed above In capacitor DACs, the sp plate parasitic capacitance of the ara in twodces gain error As shown in Fighre 4.20, this capacitance resis ftom electric eld lies tht emanate fom the top plate ad terminate on te substrate ater than the botom plate. With his component, a segmented » Fig420 6) Topline of acacia aay inl ppt prs,7» ‘asc inp of Dita to-Anog Comverson Chap 4 capacitor DAC, for example, canbe represen asin Figure 4.20, with Cp ‘modeling the cota top pat parasitic. Here, he ouput voltage corresponding toa thermometer code of height js mace “NCHG Since typically NC >> Cr, (4.41) is simplified as % aay, ac WEIS CANON cr wae fo-&> ay vi aay indicating that the ain devites from unity by Cr /(NC) ‘While in many stand-alone DYA converters gain err nota serious ‘drawback (and can often be uled by extemal means). in DACS used in sltstep A/D converters it becomes eral because it leads t differential nonlinearity, This issue i discussed in Chapter 6 44 SWITCHING AND LOGICAL FUNCTIONS IN DACs In order to produce a the output of a DAC an analog quantity proportional to ‘the digital input, some switching and logieal functions are required. Ta this ‘section, we describe a numberof these functions often employed inthe design ‘of DIA converters. In Chapter 5, we see how these fuetions ae chose in sitloren architectures. 4.4.1 Switching Functions in Resistoradder DACs In resistor ladder DACs with binary inputs, the switching function ean ‘be implemented a an analog mukplexer [15]. As depicted in Figure 4.21 (a, the binary input selects one ofthe Ladder taps providing a resistive path from that tp to the ouput. Thus, if no eaten is drawn fiom the output, Vg ‘equal fo the voltage of the selected tap. Note that for an m-bit DAC m MOS ‘itches appear i Series betwen each ladder tap and the output node. The total channel resistance of these switehes often limits the seting speed at he ‘output and raises concer forthe thermal noise alded to Vy. Futerore, the output node must be blfered by a high input impedance amplifier because resistive loads directly connected to Vj, cause attenuation and nonlinearity {asthe on-esstance of switches varies with the output voltage). In addition, Sods Switching ad Lp! Psion BACK n 2, By Os Ds Oy o foal” ) Fig 421, Resear DAC wih (Bn nat a hon2 Bas ince so-Amlog Comer Chap 4 if Ve 8 comparable withthe gate overdrive ofthe switches, the topmost soithes in Figure 4.21) exhibit substantial on-resistance unless they use ‘complementary devices For resistor adder DACs with thermometer code inputs—such as those ‘tlied in A/D converters—the switching can be relic as show in Figure 44.21(b) Here, NAND gates are used (o compare every two adjacent Bits of| the thermometer code, thereby detecting the topmost ONE and generating & [Fofen code. This code then tims on the corresponding switch, making Vy ‘sual ladder tap voltage. In contrast with the multiplexing coniguation of Figure 421(a, this DAC uses only one switch between each ladder tap and the output, thus achieving a lower overall channel resistance and move ‘modularity in layout. However for an m-bit DAC with thermometer code ‘input, 2" switches are connected tothe output node, introducing considerable _jetio and overiap capacitance at that node. Forte same DAC with binary pts on the other hand, the capacitance of only 2m sites appears in the path fom ladder tps to the output Other ladder switching topologies are described in the context of DAC sarhitctures in Chaper 5 4.4.2 Switching Functions in Curtent-Steering DACS Currentsteoring DACS conigued as segmented or binary aay of ten use a unit curentsteering cell, Figure 4.2 illusteates diferent curent- ‘witching cll in bipolar and CMOS technologies. Note tha these cites can naturally provide ufferential outputs ‘A conparison ofthe speed and precision of these cells can reveal thet merits and drawbacks. The exponential /- characteristic of bipolar transis toysallows complete switching of current with only few hundred millivolts ‘of diferental swing at D and D in Figure 4.223). On the other hand, the [MOS pair in Figure 4.2200) ypically requires diflerenial swings of more han 1V at Dad D to ensure that onesie uns off completely. This iference in swings indicates two advantages for bipolarswitches over MOS devices. Fist. the input voltage transition is aser. Second, the voltage swing at node X in Figure 422(a) is smaller and bence the feedthrough to the bis line Vp is es. ‘An important aspect ofthe above curen-stering celles thee outp impedance because i contributes to the overall integral nonlinearity (Section 4432), For the bipolar coll his impedance is [6] Leake Ry = aE posggizronn, aaa) 14 Sane B here gus isthe transconductance of Qs, and gy dro ae the tanscon- SecA Switching ant opel Functions in DACS n « Fe.A22_ Curette clk a (para) MOS techno. dctance and output impedance of Q, or Qs (whichever i on), especie “This equation can be rewriten as Vag + Vr foe Vag + BYE eae BrostuisFos as) where Vu: denotes the voltage drop across Re. In atypical ease, Vr < Vie « BVr. yielding: Var Rog = HE roreantore oa = Eros 446) ‘Thus, emiter degeneration increases the output impedance hy factor of Ve Vrs making desirable to maximize this ration the presence of wotage headroom constants. Note that a explained in Section 43.2, ncresing tis ratio als lowers mismatch between cells by suppressing the effet of emitter rea mismatch For the MOS curren-stering cel the ouipt impedance depends on ‘whether Mf) and My are inthe saturation or the linear region when they are fn, If these devices are in station then Raw ® rostaszrors aan For a given curent, this value can be increased by increasing the length (of My-As or the width of My and Ms. To maximize speed, My and Ms ‘usualy employ minimum length and M; is sized to provide adequate output impedance.4 ‘Bas inp of Digiate-AtlogComesion Chap. 4 1 My and Mo in Figure 4.220) enter the deep linear region, then Rog = ort Rat as) where Re isthe ontesstance of My and Ma, This value is much les than that in (44) and often inadequate for euret-stering DACs. ‘Another consideration in high-esoution DACS i hat the sting time atthe ouput noe usually dominates the conversion speed. Consequently, the furrent switching delay is only a small action of the ttal conversion time ‘making the difference between ssitching speeds of bipolar and MOS pairs realize 4s importa to note tat the output voltage swing of DDACS is quit limited, whereas it can extend to both supply Ind and capacitor DACS, making the ater two more stable when & wide dynamic range is necessary ‘Other variants of curent-stceing cells are discussed in (16,17. 4.4.3 Switching Functions in Capacitor DACS Figure 4.23 illustrates the implementation of switching function in a 'ypical capacitor DAC. Depending onthe digital input format chinaryo¢ thet mumeter code) the devices inthis creit have uniform o binary weighting. ‘Tre digital input controls the MOS devices that switch the bottom plate ofthe apactors between ground and Vjgs. The top pat is discharged vo ground by Sr ring reset. ts instructive to eaeulate the setting ime ofthis DAC as funetion ofthe sizes ofthe capacitors, dhe switches, and the loa capacitance, AS an example, we consider a segmented aray, shown in implied form in Figure 4.24 fora thermometer input of height). Here. Ry represents the on resistance ofthe th switch and C, denotes the load capacitance. Assuming Ry By = B,C) =--- = Cy = C. and NC > Cy, the reader ‘an easily show that she output setling behaviors deseribed bya single time xonstant equal RCL rw ay) Note that ra independent ofthe vale ofthe capacitors in he aray. This is ‘because al the devices in the aray were assumed denial thereby resulting in cancellation of higher-order terms ofthe complex fequency s. In reality ‘he capacitors and switches donot match perfectly yielding ational com- ponents inthe seting waveform, Equation (4.49) nonetheless shows that the Swing Lop anton in DACE Yee hte Fig:A24 Sipe salsipml modelo a sepmeidcpatr ay6 Base Pils of Digi AniogComenioa Op. ‘ime constant canbe quite sal because the on resistances of all the switches ‘appear in parallel when the irut drives Cy "Another issue inthis DAC relates the size ofthe reset switch Sp. In ‘order 0 suppres both the nonlinearity of source o drain junction eapacitance and the offset caused by charge injection of Sp, its size must be minimized, However this wold result ina very slow rset if Sp were to discharge the centre aay w ground. This problem can be avoided ifthe botiom pats of ‘xpactors are grounded during reset so thatthe aay capacitors remove the charge that they previously injected onto the output ae in the conversion ‘mode [8 Inthe capacitor DACS used in succesive approximation A/D converters the voltage ofthe Cop plate ofthe aray always returns to zero atthe end of comnersion (Chapter 6). Thus, in such applications the noalinearity of the jneton capacitance of the tp pate switch is nelle. “The switching operation in capacitor DACS often draws very large ran sient currents from Vagr. For example, if 64 capacitors in 128-unit array ‘wite fom ground to Vay = 2 V ad ieach capacitor has a value of 0.5 pF and each switch anon-resistance of KO, then the initial eurent dawn Bon Vjqr exceeds 5O mA andi teaches this peakin only few nanosecoms. I Vasr is Supplied externally the lead and trace inductance ofthe package give se ‘to substantial transient volage drops aya result such a large curent spike, thus increasing the outpu senting time dramatically. If Vis generated on the chip the reference generator ast exhibit low output impedance even for highspeed transients a equrerent often dificult to meet with reasonable power dissipation, 44.4 Binary-to-Thermometer Code Conversion Various features ofthe thermometer code have made iatractive for use in DIA converters. Sinee in stand-alone DACS the digital input i typically binary, binary-thermometer code conversion is usualy necessary. ‘Shown in Figure 4.25 are the binary and thermometer codes correspond ingo docimal numbers 0107 along with logical expressions that perform this Vrs and (52) provides reasonable approxi S552 Cet Sesing Arties ‘The above diseussion indicates that the base-miter voltage of Qy im Figure 5.6) is Vr nd wots les han it ideal value for proper sealing, This error can be canceled by inserting voltage soure equal Vr In? hetwoen the bias voltages applied tothe bases of Qy and Q> [Figure 5.66)}. This volage diffrence can be established by passing & current of (Vp In2)/Rix through a resistor i, interpose between the bases of Qy and Q> [Figure 5.7a)]- The curreatis proportional absolute temperature (PTAT) and ca be generated by any of the various band gap reference circuits (9.10). AS an example, consider the eieit in Figure 8.7, where the emiter area of Q: Js twice that of Oy: ie, fs2 = 205, The Feedback loop established by the tiference amplifier & ensues tht fy = fea. Consequently. te fos 2 Vict = Vein Ze? — vp tn ZC sy ° In Ts ° =Vrin2, 60 % Fg. $7 a implneaton of Hosting wlge of lng = Ve 2b)s Dig w-Anlog Comer Anitesh. “This voltage difference is sustained across Rz_ (= Ry), giving fe> (V5 1n2)/R. The ouput current Fes is generated by a curent source con- “sting of Q and fs, which are replicas of Q> and Rs, respectively. Nowe that the base cutent of Qin Figure 5-7a) introduces an additonal voltage ‘drop across. degrading the accuracy of correction igh [Another &-27- network-based architecture isshown in Figure 58, where device scaling does not exoved a factor of 2 10 1. thershy reducing the ‘circuit area substantially [7]. This circuit consists of identical transistors (Qo.-s+» Ox-1 With equal emer resistors and sm R-2R network that per forms the binary division ofthe collector caren ‘To see how this division is aecomplished, we consider a 3-it example ‘having the equivalent circuit shown in Figure $.9(a) (wth all the currents sovitced othe output, I'he cect inside the dashed box is replaced with ts Norton equivalent the circuit shown in Figure $46) is obained. Combining the parle devices inthis cgeit and substituting the result with another Norton equivalent, we arrive at Figure $.9(¢ Thus, the output curent i a binary-weighted sum of /), 3. and f- This derivation also shows that i an extemal resistor i te from the output node to ground it merely affects the full-scale output voltage swing and has no influence on the accuracy ofthe binary weighting “The architectures described inthis section canbe employed to achieve igh resolutions. The small numberof resistors—1Wice the number of its— Sec52 Canon Acces » ig 89 Eqn cis of caret ttng DAC with an 2 use in these circuits makes it possible 0 lasertim these resistors, thus cor recting mismatch erors. However unlike segmented arays, these archi- tectres do no exploit er averaging due © a large number of nominally identical devices and hence require tighter matching ofthe components ‘Another draack ofthese architectures isthe potentially large gl sea. To study this effect. consider the simplified circuit of a 4:6 DAC shown in Figure 5.10. Fist suppose the digital binary input sequal © 108), tnd hence only the MSB current source is stehed to Ihe ouput. Now, if the digital inpat goes 0 0111, the MSB eureat source turns off while the fther tree turn on and the output changes by 1. In practice, however, the digital signal diving the switches ser from inte ristime a flltine as well a timing skews. For example, during the tratsition fom 1000 to (11 all four switches may be parially off fra shor time. Thus, the output cutrent momentarily reaches a vale different fom either BF or 77, causing slit ‘Timing skews can be suppressed through the use of on-chip latches sample and align the incoming digital signals and aply only the sampled val: ‘est the current switches. Finite ansition ies and clock skews, however, sul resul in outpat glitchesig, 510 lich inguin acuet-ssing DAC, 5.2.2 Segmented Architectures [AS mentioned in the previous section, architectures based on simple binary weighting suffer from (wo important drawbacks. First, they require tight device matching to achieve monotonicity (DNL ~ | LSB). Second, they ceahibit age slitch impulses. Segmented architectures are commonly used to alleviate these problems Figure 511 shows an m-bit segmented current steering architecture which i based on the segmented array deserted in Section 4.3.2. In this Irchitcetue, N— 2" ~ | nominally idendeal curent sources are controlled hyathermomstercode. Ina stand-alone DAC, a binary-thermomete encoder precedes he array. In Figute 5,11, as dhe digital input increases, dhe DAC switches more current sources to the output without turning off any ofthe curent sources “hava already switched to the output. Thus, the inpuvoutpt characters is maotonic and the glitch impulse is small. Note that while monotonicity {ypicallyesults in a small DNL, the INL may be quite large ifthe devices do ot match accurately. "The circuit of Figure 5.11 is called a “Ylly segmented” architecture bocatse it employs 2” ~ 1 equal current sources form bits. Fork > 8, the ry Thermometer Decoder oa Binary input ig S11 Sepmened tent tering DAC number of devices inthe array becomes quite large, leading toa high 63 pctance atthe euput node. Furthermore, the binaryshermometer decoding Fogie occupies lage area and requires substantial power dissipation. Even ‘hough fully segmented architectures have been used for resolutions high 3810 bits (11) ( minimize te glitch impulse, ii often more ficient 1 Patton the DAC into a segmented coarse sub-DAC and a binary-weighted Fine sub-DAC whose output currents am simply added. Im other words. for ‘resolution of m = £ +, the most significant bts ae converted to ther rmometer code and dive a anit segmented ara, while the remaining is ar directly applied tan n-bit binary array. Called te partially segmented architecture, this topology is illusrated fork = 6 and » = 4 in Figure 5.12. Here, an R-2R ladder performs the binary weighting i the sme manner as escrbed in Section 5.2.1 "The choice of k and in general depends onthe matching of the eueent sources and the tolerable itch area, TYpicl valves fork range from 4t7 In the architetare of Figure 5.12 tbe complesity ofthe binary-thermo- meter code conversion, the large numberof curentsoures, and the issues related to routing signals place stringent requirements on floor planning and layout, Am efficient approach is to arange the current sources and part of ‘he decoding na matrix a8 shown in Figure 5.1¥a) [12]. Here inary-ther- ‘mometer conversion is performed in two steps: ow an column decoding Followed by loeal decoding within each cell ofthe matrix. Inthe first step the2 Diao Ang ComenerArchtees Cap. ig. SA7_ 4 100i parity segnmattcoresetiag DAC ‘input binary word (Dy... Ds) spatiioned ito two subwords (DyDsDy and DyDsD;) eae of which is converted toa thermometer code. ‘The resulting codes are disrbuted eros the mari as depicted in Figure 5.13(a). In the Second sep the rowan column thermometer codes are combined locally to determine the required status of each curent source. To implement local ‘decoding, we note that for any digital input, each row falls in one of three gore [2]: (1) rows in which all current cells are on (2) rows in which Curent cellar olf, and (3) certain row in which some of the current cells ‘aren, To determine the tatu of each cel, the ow and column thermometer ‘oes are leally combined around each curren source. Figure 5.13(b) shows “srexample where two adjacent bits of the row thermometer code and one bit ‘ofthe column thermometer code are used 10 generate the contol signal for the eurent source. ‘While providing asimple, modular layout, the matex configuration must deal with to cficais. Fist, ‘great deal of coupling from the digital signals that low in both horizon and vertical directions within the matrix. In bipolar implementations, th effect is minimized trough the use of elatvely small (= 0.5 V) difleretial Signals for column and row thermometer coes. In CMOS circuits, on the ‘other hand these signals are typically eil-to-al and single-ended, resulting in substantial coupling to the analog output ‘The second ise stem from the wiring capacitance of the analog ouput line. This ine mast each al the cells, and it oval length is given primaiy bythe size of each call Since the cells must be larg enough to accommodate local decoding (anda curent source), the total Iength ofthe analog ouput line and hence the output seting are quite long S52 Cut Siesing Aniectaes 8s DB: o >> » Pig S13 (0) Mas xrlanfor sgn DAC, aa desing ‘Theideaof segmented DACs was orginally proposed by Shoet and used ina 12.tu converter to achieve monotonicity without trimming [13] Shown in Figwe 5.14 sa simplified 5-bit version ofthis architeture consisting of segmented ary’ rand a inary-weighed array f-1y. The sie principle of tis architecture isto switch each ofthe equal cutent sources f+; tothe ‘ouput in an adie fashion and use their subvisions to provide finer steps sad hence higher resolution, To ustrate his principle, we examine the ouput current asthe digit (inary) input, = Ds--- Dy varies fom zero to fl scale. For 0 = Da = 2) sthecuren source fs switched to nade P and subdivided to generate Ih-fo, Tous, s-y are switched tothe output node acconing to the Value of Dox while exer currents ae switched 10 ground, Noe tha for oa = Le I ‘When the digital input is equal w 2, J is switched 1 the out node, {some Pad the remsining cen ground, "Ths, the dileence between the output curentsconesponding to Dg = 2° — Vand sual indicating tha this transition always monotonic Bocas Ip his inte positive vale For2! = Dy, = 241, fs is subdivided to generate FF, and the ous currents equal to the sum of a proper combination ofthese curent nd.o Digiat te Ang Comores Arches Cha. 5 or, HH outeecer [12 ‘Seu Loo ee ee For Dy =, sich et tothe op a = H+ Asin ‘eigenstates pat caren coef W De 2 and Dy = 2 is equa of, thereby preserving monotonicity. The same switching algorithm is used fr larger digital inputs, “Theintegral linearity ofthis architecture depends primarily on the match ing of f-1,. Lasersrimming or sel-calibration techniques suchas those de- scribed in Section 83.1 can be employed to achieve a small INL, Despite the above features, this eituit faces an import limita ‘when implemented intday’s technologies. Thestackingof devices in curent sources J-fo on top of one of fer severely limits the eurpt voltage sing ifthe supply voltage i only 5 V. The segment decode uilized i this architecture is more than a binary- torthermometer converter because it must also determine which one of -f inswitched to node P. A compact implementation is possible ifmuliple logic levels are used (13). REFERENCES 1] H.U.PostandK. Schoppe, “A 14Bit Monolithic NMOS D/A Converter TEBE J. Solid-State Circus, vl. SC-18, pr. 297-302, June 1983, (np 5 References 8 {2} A.G, Dingwall and V.Zezz0, “An §-MH2CMOS Subranging -Bit A/D ‘Converer” JEEE J. Solid-State Cire, vl. SC-20, pp. 1138-143, Dee 1985 [3] M.A.M. Pelgom, “A 10-Bit S0-MHiz CMOS DA Converter with 75-2. Buller” /EEE J. Solid-State Cieits, vol SC-28, pp. 1387-1352, De, 1990 [4] P.Vorenkamp eta,“ 1 Gys 10 Digital-to- Analog Converter" ISSCC Dig. Tech, Pap. pp. 52-53, Feb. 1994, [5] W.T. Sagun etal. "A 125-MHz 12-Bit Digital1o-Analog Convener System?” Hewlett Packard J pp. 7885, April 1988 (6G. Kelson, H. H. Stelrecht, and D. S. Perloff, “A Monolithic 10-5 Digital-to-Analog Converter Using lon Implantation.” IEEE J. Sol Stare Cire vol SC, pp. 396-408, Dec. 1973. (7) D.4, Dooky. “A Complete Monolithic 10-b DIA Converter IEEE J. SolidStte Circus, vl, SC, pp, 404-408, Dec. 1973. [8} P.Hotoway and M. Norton, “A High Yield, Second Generation 10-Bit Mosoithie DAC.” ISSCC Dig, Tec. Pap, pp 106-107, Feb, 1976 [9] A.P. Brokaw." Simple Taree-Terminal IC Bandgap Reference" IEEE J. Solid-State Ciruits vol. SC, pp. 388-393, Dec. 1974 [19] R. J. Widla, “New Developments in IC Voltage Regulators” IEEE J Solid-State Cireuits vol SC-6, pp. 2-7, Feb. 1971 [11) H. Takakura and M. Yokoyama, “A 10 Bit 80 MHy Giteless CMOS DIA Converter” Pre. CIC, pp. 26.5.1-26..3. May 1991 [12 1 Mits,"An S0-MBlz 8-Bit CMOS DIA Converter” IEEE J. Sol-State Circuits, vol, SC-21, pp, 983-988, Dec. 1986, [13) J.A.Shoef."An Inerently Monotonic 12 BitDAC" JEEE J Solid-State Circuits, vol, SC-14, pp, 904911, Dee. 1979,6 Analog-to-Digital Converter Architectures ‘Analog-o-digital converters provide the link between the analog world and digital systems. Duetotheir extensive use of analog and mixed analog digital ‘operations, A/D converers often appear asthe botleneck in data processing applications, liming the overall speed 0 pression, Following a definition of performance metrics, we describe inthis chap- ter a number of A/D converter architectures commonly employed in high- performance sysiems, These architectures can be broadly clssifed 2s one ‘ep or multistep, with fash, nterpoative, and ating topologies inthe fist category and tw step, pipelined, and successive approximation configura tions inthe second. However, two-step ADCS (and the concept of reside) are discussed before interpolate and folding atchitecures to simplify the ‘escrption of the later. Also, flash and tworstep converter ae studied in great deuil because a good understanding of these two architectures proves help in analyzing other ADCS a ell In addition o the ADC architectures coveted here, several others are sometimes used in specialized applications. Gordon provides a comprehen- sive study of sich arhitectures (1. 6.1. GENERAL CONSIDERATIONS: An AUD converter produces a digital ouput, D, a a function of the analog input Dasa ny While the input cam assume an infinite numberof values, the output can be selete from only a finite set of codes given by the converter’ output word length (ie, resolution). Thus, the ADC must approximate each input level with one of these codes, This is accomplished for example, by generating & set of reference voltages coresponding to each code, comparing the analog input with each reference and seletng he reference (and its coe) closest 10 ‘he input level. In most ADCs, the analog input isa voltag quantity because comparing routing. and string are easier for voltages han for curren Figure 6.1) depicts a simple ADC inpavoutput characteris where ‘he analog input is approximated with the nearew smuter reference level. If the digital ouput isan mbit binary number, hen a! e omen 2) ‘where [] denote the integer par of the argument and Ve is dhe inp fll scale voltage. Note thatthe minimum change in he inp that causes change in the ouput is = Vygp/2" and corresponds (0 the least significant it of| th digital presentation, SO ST ae BS 6a FE Aas me ® SBA BL BT alg Tt © Fe 61) putt eae: (gunn ere a a ADos Analog-Dii Convener Aciesues Chap. 6 ‘The approximation or “rounding” effect in A/D converters is called “quantization an the diference between the egal input and the digitized ‘output sealed the “quantization ear” and is denoted hereby &y. For the characteristic of Figure 6.1(a), # varies as shown in Figure 6.1(b), with the maximum occuring before each code Wanstion. This error decreases 25 che resolution increases, and is effet can be viewed a6 ative noise {called “quantization noise") appearing atthe output. Thus, even an “idea” ‘mbit ADC introduces nonzero noise inthe converted signal simply de to ‘quantization. ‘We can formulate the impact of quantization noise onthe performance as follows. For simplicity. considera lightly diferent inpaVoutpat character isi, shown in Figure 6.2a), where code transitions occur at od rather than ven) multiples of 4/2. time domain waveform therefore experiences both hogatve and positive quantization errors a8 ilustated in Figure 6.200). TO ‘aula the power of the resulting noise. we assume that is(1) random ‘arable uniformly distributed beeen ~ 4/2 and +A./2, and (2) indepen: ‘ent of the analog inpat, While these assumptions ae nk strictly valid the genera cae, they usally provide a reasonable approximation fr resolutions above'd bits. The quantization noise power an hen be expressed as the mean square of: psa wh feta 63) io (ay 2 1 the analog input i a sinsoid with amplitude Ye,/2 (peak-to-peak Veo) it total poser is qual Vi/'8 = 2°"87/8. Thus, the peak signa tori ratio SNR atthe out amg? a 5 san, = «s) Sm 6 which when expvedia eel, eames SNe = 60am 478 on ‘Thisequation soften used to compare the performance ofa given m-bit ADC ‘with that ofan ideal oe. For example, the peak SNR may he measured inde pendently to attain an efecive vale form. This discussed in more detail Tate. Dig © e.62 a) Molied ADC sharers fle apd uti ization characteristics described above sre “uniform”: Le. points are equally spaced Je some applications. ther types ‘uch as logarithmic quantization are desirable 2]. In this book, we consider ‘only niform quantization more extensive analysis of quantization canbe found in [2 and (3, 6.2. PERFORMANCE METRICS ‘As with sampling circuits and DIA converters ull spectiation of the per- formance of ADCS requires lage numberof parameters, some of which are100 Ame gal Comer Ahr — Chap 6 defined differen by different manufaturers. Here, we define @ number of| “important meas frequently use inthe book. For a complete st of speci ‘cabins, the sader i eered 10 the ieature [4,5] and manufacturer data books. Ilustrated in Figure 63, the Following definitions describe the static behavior of ADCS, Digit DNL +1 LS8 ‘Analog Input ‘+ itferemial nonlinearity (DNL) isthe masimam deviation in he di ference between two consecutive code transition points On the inet ans from the ideal value of 1 LSB, ‘Inept nonlinearity (INListhe maximum deviation of the inpuvoutput ‘harass from a straight line passed through its end points (line ABinFigure6.3). The overal difference plotiscalledthe INL profile ‘Offset isthe vertical intercept of the straight ine through the ena pins, # Gain errors the deviation ofthe slope of line AB from tidal value ‘asually unity, ‘Often specified as fonction ofthe sampling and input frequencies, the following terms are used to characterize the dynanic performance of| ‘Signal-o-noise ratio SNR) isthe rato ofthe signal power tothe oa noise power atthe output (usually measured fora snasoidl inp ‘Sipna-o-(noise + distortion) ratio (SNDR) is the ratio ofthe signal power tothe total noise and harmon power atthe output, when the Input is sinusoid oe,63 Fn Arcee 7 + Esfectve numero bis (ENOB) is defined by the following equation: SNDRp 1.76 . a Nop = SWPP (68) ‘where SNDRy isthe peak SNDR ofthe converter expressed in dec tele ‘+ Dynamic rangesthe ratio othe power ofa fll-sale sinusoidal input to the power ofa sinusoidal input for which SNR= 0 dB, eis important oot hat since A/D conversion ents signal sampling ‘many ofthe sampling circuit metres deserted in Chaper 2 ean beaded to [ADC parameters. For example, aperture ier is crucial parameter because iu direcay impacts the ouput SNR. (63 FLASH ARCHITECTURES ‘Conceptually the simplest and potentially the fastest, ash architectures em- oy paralletisnt and “eistribated” sampling © achieve a high conversion speed. Figure 6.4 isa block diagram of an m-bit fash ADC. The circuit consists of 2" comparators essior ladder comprising 2" qual segment and a decoder. The ladder subivides the main feference into 2" equally spaced voliages, and the comparators compare the inp signal with these voltages. For example. if the analog input is between Vj and V, Om farators Ay trough A) produce ONES at their outputs while the rest generate ‘ZEROs, Consequently, the comparator ouputsconstte a thermometer code ‘Chapter 4), whichis converted wo binary by the deve. ‘As explained in Chapter 7, comparators often incorporate clocked re- ‘enerative amplifiers to achieve a highspeed. Ina flash architecture, clocked ‘comparators offer another advantage as Well they act as “polarity sampling” iret. We iste this by considering a simple Block diagram of & om parator (Figure 6.5). This ereuit consist ofa preamplifier A and a latch ‘When is high, A amplifis the difference between Vi, and V2 while the Inch is sabled. When ® goes low and ® goes high, Ais disabled and the latch begins to amplify the citfeence established a ts input hy the preass- plier, thus generating logic levels a he output. In other words, when & ‘high, the comparator wacks the input and When @ goes low, it ores the instantaneous polarity of Vy ~ Vn Thus, if all the comparators in Fig- ture 6 are stobed atthe same time, they’ collectively store the polarity of the difference between Vy and each V;, thereby operating as a “distributed” sample-and-nld eireuit1 Ang to-Digl Comener Artistes Chap. 6 Digital Output Fe.64 Black daa of am fash AD come Vins }— A Laten Vou Vaz = ® o Fe.65 Sil compar bis Ik follows rom the above discussion hat fl-slsh architectures, in prin- a go 6.3.5 Metastabilty Since fash archtectres employ comparators, they are susceptible to retastability errs [16]. As explained in Chaper 7, metastabilty occurs when the diference atthe input ofa comparator i mal, making the ieuit take a ong time to produce a well-defined logi output. ifthe instantaneous ‘lve ofthe input signal toa lsh ADC i close to the reference voltage of fone ofthe Comparators, that comparator wil have am indeterminate output for ' Tong ime, possibly causing an erroneous digital ouput for that particule [As an example consider the decoding circuit in Figure 6.15, where ‘comparator Ay is metastable. NAND gates G and G1 sense the caput ofthis comparator and are to provide logic levels for to rows of the ROM, ‘somesponding o binary outputs O11 and 1000, spectively Ifthe output of 44s indeterminate, iis posible that Gy interprets a8 ZERO while G) + interpeets it as ONE, thus causing the ROM io generat a binary ouput of | Hand hence a gross error inthe digi outp Vin 4h me Binary ouput Me “ Yan I Pees [Note that when metastability occurs, the final logical Value ofthe meta stable comparator output isnot critical. it ean be either ZERO or ONE, because the difference between the analog input andthe comparator reference voltages very mal, However, itis the tardnes of the comparator in teaching ‘logical vale that causes substantial errors. From the example in Figure 6.1S, we can see that ia metastable level {is applied to more than one gate atthe same tie (i. iit “splite), tean be incerpreted ferenly by dierent gates and hence introduce large eres, Di So long as iis sensed by only one input. its likely to appreach comet logic Teves In order to lower the probability of metastable states. the thermometer: binary decoding can be pipelined so that potenisfy indeterminate outputsmm Analog Dipl Comener Arter Chap. 6 ae allowed more regeneration time, This is ofcourse possible only if each potentially metastable level is sensed by no more than one input, an unsu- ‘mountable issein the decoder of Figure 6.15. A simple butpower-consuming “approach would be to follow each comparator with more latches 10 allow a longer regeneration time forthe thermometer code. more eiciny ech nique employs Gray coding as an intermediate step between the shermomete and binary codes. This i discussed in Section 6.38, 6.3.6 Slew-Dependent Sampling Point Another typeof error in the presence offast-varying analog inputs is slew-dependent sampling insat of comparators [12]. This errors Jue to the finite switching time fm tacking Wo latching, We llustate this eect sing re 6.16, whet simple comparators shown along wih is waveforms. ‘CA goes high o switch the ctcut fom tracking to latching. A odes X and ¥ regeneratvely, while the input diferental pir begins totum off Fam the time the latch begins to tar on uni the me the input pair earns ‘off completely, the input signal can sill inuence Vy though Qj and Q>. For example, as depicted in Figure 6.16). ifthe input signal varies lowly although the polarity of Vj, ~ V, changes after =, the effect snot song {enough to overtide the polarity of Vzy. On the ter handy a shown in Figure 6.16). if Yq ~ V changes eaply ican reverse she polarity of Vay and generate a diferent logic output. This phenomenon canbe viewed as 3 ‘aration in dhe sampling instant ofthe comparator asa function ofthe input Slew eate and intiuces ot harmonics because it cccurs for both negative and positive slopes (12), “The above eror can be lowered by making the clock transition rates salcintly higher ¢han the maximum slew rate ofthe analog input. On & large chip, is requires careful distribution ad buffering ofthe clocks wih ‘particu tention to their Hoang 6.3.7 Clock jitter and Dispersion Asexplained in Chapter2 all sampling ctcuts suffer fom SNR degra- dation as the jter ofthe sampling command increases, a pariculaly critical Jssue when the analog input has high slew rates. Fash (and other types a) ‘ADCs are no exception because they incorporate sampling. ‘To ative at a simple relation between maximum tolerable iter and an ADC's sped and resolution, we can say that iter das negligible effet on the overall SNR ifthe analog input varies by ess than | LSB during jer induced time deviation nf the sampling point. Thus, fra full-scale analog Atr {he iatch turns on, it Begins to amply the intl diferental voltage Soe 63 Pas Archies us rol da” © Fig616 a) Aipolarsonprtr wih) how nk) gh sew tape. int Y= Assn those maxima ue fcnge i eq ©2074 ehhote coin ences afar < 1150 a) where A represents the clock jter and m is the converters resolution. tt follows that was)m4 Asp Dig Comer Anse Chap. 6 Je Nyquistrate converters, f approaches half ofthe ADC conversion speed. ‘Tis esl is only rough estimate, but allows a quick ealelation of jer requirement “The distributed nature of sampling in Bash converters gives Hse 10 a ‘unique timing problem that doesnot exis in architectures with Single frnt- end sample-and-hold amplifier. Since the analog signal andthe elock mus! travel long distances ona large ADC chip. they experince differen delays ‘de to dtferet loading [16] Furthermore, even with wena loading, the ‘lock waveform—ideallyasquare wave changes (s“sspersed”) its tran sitions are slowed down by the distributed resistance and capacitance of i terconneets. Thus the exact time diference between the analog signal and the lock edge varies from onesie ofthe chipto the other, causing harmoaic Aistontion inthe sampled waveform. 63.8 Gray Encoding ‘Two of the potenti errors in fash converters, namely, metastability and sparkles, ean be suppressed using Gray encading a an intermediate step ‘between thermometer and binary codes. The probability of metastable slates inbe lowered ecausein Gray encoding n signal isappliedto more than one input allowing the use of pipelining to increase the time for regeneration, The lfc of sparkles is reduced because the accuracy of the Gray code degrades ‘ety gradually as more sparkles appear inthe thermometer code. ‘We illustrat these points with the aid of @3.bitexampie, depicted in Figure 6.17, From the correspondence show here we aot thatthe Gray code ‘tpt G GG can be expressed interms ofthe thermometer codes Follows Gy =nh+nh 616) G2 = BT (6.17) (28) ‘They poinin these equations is that each T; appears inony one expression and hence no signals in the logic split, AS ares, metastable errors can be reduced by pipelining the encoding, for example, as showa in Figure 6.18. [Note that, fo esoutions of bits and above, the mumber of aches decreases by roughly a factor of 2 afer every level of logic ‘Toseethe robustness of Gray encoding with especto sparkles, consider ‘he eases illustrated in Figure 6,19. We note tht wile the numberof spaces Increases, the Gray ouput remains fairly close tothe top ofthe zhermometer code, providing reasonable approximation ofthe sampled value, The performance of fash converters is determined primarily by that of their constiuent comparators. Thus, the alizabilty ofthis architecture ina Thermometer Gray Binary Te Ta Th Ty To Tr | GaGa Gy ig 617 Conepenene sone hemo Gin nf ay ales 5 i a — ame PDs ed baer 5 EqD[ee}—__fma % ae aa} -o, Tamer Gaye Gase”_Gada onan Oat Twospanie: sHintniiHHH00 1010 ny encoding nthe presence of spe. iven technology depends on the speed and accuracy with which comparisons ‘ean be performed, Asa esl the high speed and superior matching of bipolar transistors have mad them the dominant technology for Nash ADCS, CMOS ‘devices with their lw transconductance and large mismatch, have noe yet ‘provided competing performance. Nonetheless, highspeed CMOS ADCSa Analg igi Comer Aciectaes Chup. 6 ‘are sillindemnandbecausethey can be integrated n'a CMOS signal pressing ‘envionment 6) 64 TWO-STEP ARCHITECTURES “Theexpanential growth of power, rea, an inp expacitance of Mash conver rsa function of solution makes them impractical fr resolutions above 8 bits allng for other topologies ha provide a more elaxed trade-off among ‘hove paumeters, Tworstep architectures trade speed for power, area, and inpot capacitance Iva tworstep ADC, fst a coarse analog estimate of the input s ob ‘ajned to yield a small voltage range around the input level. Subsequent ‘the input level is determined with higher pression within this range. Fig tie 620 illustrates a two-step architecture consisting ofa front-end SHA a ‘coarse flash ADC sage, « DAC, a subractor anda fine Mash ADC stage. We ‘describe its operation using the ming diagram shown in the same igure an the waveforms of Figure 6.21 ; wf LE Bh 4 tse 5, Satna | Sikcamerson Pie 620-wo.sey ADC cies ‘Fort < the SHA teacksthe analog input, ALY = stheSHA ener the hold mode adhe ist Mash stages strobe to perform the coarse conversion, The fist stage ther proves digital estimate of the signal held by the SHA (Vand the DAC convert this estimate to an analog signal (V). which is Sec 64 Two-Step Atte wn coarse approximation ofthe SHA output, Next, the subtractor generates an ‘output equal wo the difference between Vand Vy (Wo, called the "residuo"), “whichis subsoquenly digitized by the fine ADC. each ofthe rwo Hash stages resolves m/2 bts. the digital utp isan representation of the analog input. In practice, her combinations such ss (n/2-+ 1,m/2~ 1) may be use for the two stages. Also, as discussed in Chapter ifsigial erretion s employed, some redundancy is added to one ofthe ash stages, he sum of thee resolutions is lightly greater than “The front-end SHA plays »=rucal ole in the performance of ostep ADCS. Withoutthe SHA, the maximum sowable stew rate of the inp il 's severely limited. This acurs because ifthe asic input varies pil in the conversion made, then the sina level digitized by the fs tage is D0 ‘equal to that sensed by the subtactor immediately before fine conversion. Figure 6.22 illsrates this timing issue, which fundamentally arises fom the nonzero delay ofthe fst stage and the DAC. Fo eror-fee conversion, AV = 1 LSB. To quantify the resulting imitation, we assume a full-scale input V, = Asin 2a Ith analog estimate, Vp, sets to is proper value Ta seconds after the fis Stage is stobed (ie, Ty = fe ~ f)) then the analog Input must vary by less than | LSB during 7 Since the maximus slew rate ‘tthe inputs equal to 2 f, we have anf Aly < 1188 19) <3 (620) Ina typical ease. Ty is roughly one-fourth of the tal conversion perio, 1% 1/(4fs), where fis the conversion rue, and henee ye fs ee 20us Anop Dipl Comener Aires Chap. 6 “The limitation imposed by (621) is substan tighter than its tbeoreieat ‘counterpart in a Nyquist converter (f= J/2h, For this reason, wo-step architectures usually roguizea font-end sampe-and-hold ampli ‘The above discussion als reveals another timing isue inthe presence of SHAS: sino the ouput of atypical SHA fakes a finite ime to sete aher ‘the wansition from the sampling to the hold mode, the coarse conversion ‘ean begin immediately aftr that transition ifthe subtract i 1 sense the same level. Figure 6.23 repeat the timing diagram of Figure 6.21 with ‘more realistic waveforms. We noe that if the coarse conversion occurs x = fythen the fvel digitized by the coarse sage substantially deviates Som that sensed by the subiactor before the fine conversion. A simple way of voiding this enor sto beg he case conversion only afer the SHA output has sete’ eo within 0.5 LSB ofits final value, OF course, during this time the ADC is ile, the conversion time increases by the SHA hold sting time. A beter approach isto strobe the frst stage before complete setling an comect the eror digitally, a subject discussed in Chapter 8. Pip 623 Reais wats {In addition to this problem, the Font-end SHA raises other concerns that do not exis in fll-fash converters. The ineavty and dynamie range of the SHA diretyafect those f the overall system, hile the speed-precison SOA Two Sup Actas w ‘trade-offs described in Chapters 2 and 3 limit the conversion ate. Futher- ‘more, the input capacitance and Kickback nose ofthe coarse stage compara tors dezrade the SHA ouput seting behavior. tis instructive to compare the sequence of operations in full-ash and two-step architectures (Figure 624). Inthe foemor type, the comparators track the inp signal for approximately half ofthe clock cycle and peetorm ‘he conversion inthe other half. nthe ater, while the SHA racks he input the esto the system is idle (with the exception of cris tat perform offset cincelation or lines calibration during this time). After the SHA oes ‘go the hold mode, course A/D conversion, interstage DYA conversion and solvation, and fine A/D conversion must be cari! out, This comparison suggests number of speed limitations i two-step architectures that do not exist in Mash converters. Fst, the foat-end SHA is typically much slower ‘hana comparator, i.e. requires longer tracking and hold peri. Second, several operations must be performed inthe conversion peri, each of Which entails speed-precision tade-ofls. Even though the coarse conversion ean he as fas as a flash ADC, the DAC output must see suciondycfose ty its ‘inal value, and te subtractor and fine converter quire additonal ine Fash_—_samplng | Conersion neces we ba i ‘rwo-Step sampling cafeion | Contflon | subtastan! coftraon i624 Comparnon of io ead stp eta Anodher ise relates to the interface hetwoen the subtrator and the fine stage, IF this interface doesnot entail any amplification the input to the fine stage js equal to the difference besween the SHA ouput and the DAC output, thus demanding aesoltion beer than 1 LSB in the fine age Since two-step architectures are usually used for resolutions of 10 bits and shove, this implies that the compator inthe fine tage must correctly re Solve small voltages. On the other hand. if the subtacior is followed by an amplier of gin A, the resolution required of the fine stage i eyed by the same factor. While easing the design of comparators, this amplifier now adds finite delay’ he conversion period and eonrbutes nonlinear iy: More importantly. since the Fine ADC must compare the amplifier ou ut against a set of reference voltages, the gain A must be well-contolledv0 Anges Diu Comener Actes Chip 6 so that the flsale output ofthe subsactor matches the full-scale refer: cence voltage of the second stage. This issue is discussed in more deal Tater “The presence ofthe BAC and the subesctorin he ert sgna ath i ‘les tha their inearity must be commenserae with that ofthe overall system, teil heirsped must be as igh s possible, These requirements have mot ‘aed the invention of various etcit techniques wo improve the performance ofthese functions in two-step architectures [7 8,29) ‘Wile the front-end SHA ina two-step ADC suppresses many ofthe ming inaccuracies often present in converters that have np SHA i sit ‘cannot avoid one type of ein: meassbiy. IF the SHA ousput voltage is ery close to the reference volage of one of the cause stage comparators, ‘hen that comparator wil ave an indeterminate logical output fra ong tie. Depending on the typeof subsequent decoing ad the interstage DAC, this ‘er may severely corrupt the analog estimate produced by the DAC, hence imtrdocing large errorsin the overall digital ouput. Asan example, consider a section of a T.bit two-step ADC as depicted in Figure 6.25, where the ‘coarse sage diretly drives a Segmented cutrentstering DAC (Jee Ry = 32 LSB). tf comparator A is metastable, then it ferential output sal and the iferentil pair QO: ters only half f Ys. tthe DAC put ode, X. [Asa rest, Vy deviates from its ideal valu () by approximately 16 LSB. ‘The subtractor generates the diference between Vand Ve, dee ie stage Aigizes ths diference. Thus, emor of 16 LSB. appear i the fine stage tpt ad hence inthe overall ADC output (assuming the frst stage produces correct digital ouput. seit ‘Segmented Coarse ADC DAC Subtrator Fe 625 Soon of Wi posep ADC. 64.1 Effect of Nonidealites We now study the effect of various nonidealities on the inpavoutput compare the analog input with Vx and Vn, respec tively. In Figure 6.3206), the inpuloutput characteristics of Ay and Ay are shown, Asseming zr fst for both preamplifiers, we note that Vy = Vr iC y= Nat Va = Vy if a= Va More importa, Va = Vit Via VaN/2; ie the polarity ofthe difference between V3 tnd Vyy is the same 2 that ofthe difference betwcen Vi and My Mp Vey Vn Ven Ve @ » p62 nsrolin betwen tpt f ro amis “Tne above observation indicates that the equivalent resoktion of fash suge canbe increased by “interpolating” between the outputs of peampliters. For example, Figure 6.33 shows how an additional latch detect the polity ofthe difference betwccn single-ended outputs of two adjacent preamplifier [2UT. Note that in contrast with a simple Mash stage, this approach halves the numberof preamplifiers but maintains the same nuaber of latches. “The imerpolaton technique of Figure 6.33 substantially reduces the inp caacitanee, power dissipation, and area of fash converters, while pre1 Analog to-Digis ComenerAntestnes Chap. 6 atch | Ve 1 Lateh ww = Latch Latch serving the one-step nature ofthe achitectore. This is possible because all ‘ft signals arrive tthe input ofthe lathes simultaneously and henoe ean ‘be captured on ane Sock elge. Since this configuration doubles the efective esoliton, we sa it hasan interpolation factor of 2 "Another interesting property that accompanies this interpolation eh- ‘nique isthe impreved differential nonlinearity due o dsebution of eros [2 23], Figure 6 lstrates this point by comparing the effect ofa I-LSB offset in ful-fosh and interpolate architectures. While inthe ist case (Figure {634a)] the ast gives rise ta DNL = 1 LSB (as wel asa missing cde), in the second case [Figure 6.34()] tyes a maximum DNL of only 05 LSB, Digit a tout | 2 @ » ie. 634 Dileep ina) hand (ieee cove ‘The above interpolation approsch i posible only Because the front- ‘end preamplifiers of comparators havea finite pain. To investigate this pint fuer, et ws consier the diference between V2 and Vp in Posted in Figure 6.35 is this difference foe severl values of Vj2~ Vy. As Via Vj, exceeds the range across whicheach preamplifier eshibits 2 nonzero in, a “dead band” appears around Vie = (Veit Vr)/2 where the gai is quite small and Vyy ~ Via. Ite analog inp evel falls in this band, then Vax ~ Yin tay’ not be sificien to overcome the offset of the flowing latch, thereby yielding incorrect polsity (or the diference between iq and Wat Vane igure 6.32 ® o © ig. 65 Ispolion wat ies vaso Ys ~ In reality, the transition of inpavourpt characteristics fom high gan to low gain snot as abrupt as indicated in Pogue 6.35. If the preamps are implemented as bipoa differential pais then the dead band begins to appear When V2 ~ Vp exceeds approximately Sk7/4. Ifa wider range s required, ach differentia par can incorporate emiter degeneration.be Analog -Digia Comener Aoes Chap. 6 ‘The concept of interpolation canbe extended S0 a8 to produce mame ‘quantization levelsherweenevery two consecutive reference vollagesina ash comerer, further reducing the numberof input preamplifiers. For example, consider the creuit of Figure 6 36a, where the outputs of two sweaters ae interpolated sing two uniform resistor strings (22, 23]. As illustrated in Fire 6.36(), since dhe inpulonrput characteristics of the two preampliins aeoflsetby ¥7.~ Vj, a8 Va goes rombslow Vs toabove Va, the differential ‘output volages Voy... Vos eros zeo at Vg = Ves + (U2 — Ver), foe 0.00.4, vespectively. Thus, if latches are used to detect the polarity of Vos. this configuration provides an interpolation factor of 4. Note I-ash architecture and Via — Vo asthe same upper bound (0 avoid dead bands) as described above 44 Lil Fg. 636 Higher oer mpotin (Ilene () ningpt ‘hares ‘The technigue of Figure 6.36(2) must deal with several design issues ‘that limit the interpolation factor Fist the resistor strings and the input capacitance of the following latches ioduce a ie constant inthe signal path, thereby edacing the bandwidth. ‘This reduction is proportional tothe Square othe interpolation factor ad hence becomes substantial if his factor exceeds ~ 4, Second, inthe circuit of igure 63618) as Voy and Vos varythe bis current of emiter followers that dive the resistor strings so Varies, this changing their hase-emiter voltage and causing nonuniformity between 200- ‘ossing points ofthe output voltages. This nonuniformity is equivalent to Aiferenial nonlinearity when refered tothe input. Note that the ist problem can be alleviated by redacing the value of interpolation resistors. Eat a he cost of exacerbating the second problem a increasing the power dissipation. “The nonlncaity ear described ahove decreases markedly if a large ‘umber ofampliiersarcuscin the interpolation [23], Asillusirated in Figure 637, most of the current flowing through the ressioe strings is provided by the ampliiers whose reference voltage i far from the input voltage. Thus the amplifies whose reference voltage is close to the input Tevel nce nt provide the resistor string current. In ofr to create this fect a the 180 ends ofthe merpolation ara, afew dummy preamplifiers and interpolation resistors ean be added to both ends (23), Fe 637 Resor eng caret nan ‘maolane ADC = Interpolation teciiques can also be applied to the design of CMOS ADCS. Since, a explained in Chapter 7, simple CMOS differential pais sulle from larg offset snd small gain, the interpolation scheme is better ‘implemented using autozerocd amplifiers and capacitors, ilusttated in Figure 6.38 isan interpolatvearhitoture employing a= tozeroed CMOS inverters as amplifiers [20]. The cireuit has (0 modes of ‘operation. In the samplingesee mode. Feedback switches Ss and S, are on, ‘ving he ivertersinto her high-gain region, and sampling switches Sandim Ang Digi Comer Aniecies Chap. 6 ‘Sy ae also on allowing the analog input to be sampled on C) and Ca. ACHE end ofthe sampling mode, 8.53, Ss, and 5, um af and Sand S, turn on, ‘hereby changing the volag st odes Xy and Xo by Vg Ver and Vi ~ Ver respectively, This ollage change is amplified by each inverter and combined ‘with ajiacent ones by the interpolation capacitors, yielding an interpolation factor of 2 In practice, the sampling and evaluation modes canbe pipelined sas to inerease the conversion rate [20] 4 ie * a a Vat ete be erate out Ss 5 6 Ve cots. Yor S z 1638 tna CMOS ADC 6.5.2 Foliing Architectures Folin architects tae ead from fash a vote topologies, As expen Secon 63, ash reste pie on sep operation ‘Sih med foram poxeesing. bt ty afr age pe Pasta are power pti and severe ting otc ed ad ‘clin ines Twostop arcies, on heer han, ve mach ies arvare bt equa nen smplcan-hl vat as ell ean toe poipceting. Faking schtecesperorm solog preprocessing fo tech hardvae wie minting he onesep nat fash ae “Te basic rnp nel st genre a esi vohage tov analog reponse ip ht ese oo est ‘significant bits, The most significant bits can be resolved using a coarse flash Sag operas n paral th fing cat and bene sales he Sigua etapproxinatly sane neta he restne sampled. Fg 539 {pics pencraton free nwa fling acest. ‘wovep arte cease A/D conenon, erage DA cones, stheacton mst comps foe he rope este osm sale ee 65 Isle nd Fling Acie a Incontas, folding arhitectures generate the residue “onthe ly” using simple wideband sages. Ly ome ‘pac |= ‘Residue ‘oe @ ‘ Sp— oy Fg.639 Cescraonofidc in 0 ep an nga, “To illustrate the above prizcigle we fst describe a simple, ideal ap- proach to folding. Consier two apis: Ay and A withthe inpuvouipt ‘Characterstis depicted in Figure .40(a). The ative region of one amplifiers ‘entered around (V2 ¥s)/2and that ofthe ther around (Wn. Via)/2. ad Vw Via Va Vy. Each amplifier has gain of Yin the active region and (bin the Saturation region. If the outputs ofthe two amplifier are summes the “fling” characeraic of Figure 6.4000) resus, yielding an output equ 10 Vg = Vo for Vy. < Vi = Veg and Viet Via for Vea = Vie < Ve where ‘Nhe valuc ofthe summed characteristics a Vg = Vo. IV, Vaan Va sr the reference yitages i an ADC, then these (wo regions can be viewed {hthe reside characteristics ofthe ADC for Vj Vg = Ves. Tounderstand wnhy, we compare this characteristic wid that ofa to-step architecture, 3 Thown n Figure 640(c. The two characteristics are similar except fora nea itive sign anda verical Sift inthe folding ouput for Va = Ve = Ves Ths ifthe system accounts forthe sign eersal and lve shit, the Folding output fan be used asthe residue for fine diitizaticn “Shown in Figure 611 isan implementation of folding, Her, four di- Feresial pairs proces the difference between Vo and ¥ ‘and their ‘ouput curensaresummedat nodes X and ¥- Note that the outpursofadjent Stages are added with opposite polarity: eg, a8 Vy increases. Q1 pulls node 5X tow while Oz pulls node ¥ Tow, Current source fy shits Vy down by 1.Analog Digital Cmener Aries Chap. 6 o Fie 64 0 nplegt traces of wo apis (su eas Fig 6At Fading ios, ‘Tocexplain the operation ofthe cirri, we consider its inpuoutpchar- acteristic, ploted ip Figure 62. Foe Ve well below Vey. Qi-Oa ars off, (Qs-Q ate on, fy and fy flow through Rey, and 1.1, ad Js ow through Rex. As Vi increases. Q) begins 10 umn on, while Q3-Qs remain off Gf Vetoes Vr ate sufciently far trom each other). Fot Vg = Ve Qi and Os stare 1 equally, yielding Vi = Vy. As V,exoseds Vor by several ¥y, Qs ‘ums off. allowing Vy and Vy to each Vag and Vpn. respectively. AsV, approaches V2, Qs bess to turn on and the etcuit behaves ina similar mane ner as before. Considering the diferent output, Vy ~ Vy eae tha the resulting characteristic exhibits folding point at, +Via)/2(W+V3)/2. etc. AS Vi goes from below 1, to aboxe Ve slope of Vy ~ Vp changes sign fours; hence we say the icuit asa folding factor of 4 Fig.642 Flag shancersicof he cic in Fee ‘The simplicity and speed of folding crits have made them quite pop larin A/D converters, particularly because they eliminate the ned for sample and-hold amplifiers, D/A converters, and subtractrs. Nevertheless, these irc safer from several drawacks that Timi their ase expecially for res- ‘lutions above 6 bits, We describe a aumber ofthese drawbacks here In the folding characteristic of Figure 642, ifthe input eves rom 2.0 {fl sale once the outpat gos rom Vs 0 Vu four times, folding factor of results ina frequency mulipication by n. Thus the handvwidth r= quired of the folding eieut is imes that of the maximum input frequency. thereby imposing trong trade-offs among speed, etn, and Power dissipa- tion. Asa consequence in high-speed system the fling factor i tpically| between 2 and 4 [24], “Another property ofthe folding characteristic shown in Figure 642 sits sobstandal nonlinearity. This can be beter scen fy comparing this character istic with an ideal folding ation ts depiced in Figure 6.43. The deviation ofthe aaa characters rom seight ine translates into difeental no neat ands plotted inthe same igure. Fora typical design the maximum «ovation can be as high as several tens of millivolts, prohibiting te use of| simple folding even fr resolutions as low a 8 bits ‘The diflerence between Vand Vey 1) in Figure 61 fas significant impact on te inpavoutpat characteris. In analyzing the foltingeitcut of Figure 641, we assumed that as Vip approaches Von the ditfereti ait having that eference switches while gers retain th same sae. This holds only V1) ~ Vi issuliciendy dg. On the other hand as wath interpola tion this ierence cannot be arity large because dead hand with low sain appears in the characteristic. The optimum difference is approximately fal 05V (22 ‘The nonlinearity emors in folding characteristics also depend on the Frequency of operation, At high speeds, the rate of change of signals be ‘comes Comparable with the intrinsic ime constants ofthe circuit, ths causing‘Actual nel nt Fling Actes 1 Folding t ' ccaracertos w nw %; oT oO Nontnesty : la ia fot) OGIO GG ria a7 CT . - 7 L “younding”of the characte atthe folding points and hence inereasing the nonlinearity ven though some converters solely based on the above folding tet- nique have been designed [26. 27, 28. ater mbethods have been devised sO ast exploit the features of Folding without incuring excessive nonlinearity. In particular folding and interpolation can be combined to achieve efficent, bigh-speed A/D conversion. 65.3 Folding. Before deserbing architectures this combine folding and interpolation, we should make twa important observations. Fis, nthe folding characteris tic of Figure 6.42, the nonlinearity falls o toa zero-crossing pis. Thus, iTony these poins are considered, the polarity ofthe difference between Vn and V can be determined correctly. To resolve the lower bis, ational ‘ewo-crossing points can be produced using interpolation [22], Second, if the folding creun Figure 6.41 isreplicated adits reference voltages are shifted by (Ways) ~ Vo/2 [Figure 64(0) then a second folding characteristic i obtained as shown in Figure 6.4400) [281 We cal the original characteristic the “in-phase” (7) output and the second the "quadratie” (Q} ourpt [29] Note that in fully differential implementation, the inverted versions of these ‘outputs (7 and Otespetvely) ar also wailable For simplicity. we call each ‘ofthese characterises a Yolding signal” ‘Wenow describe how J and Q outputs ofa doubl-folding circuit canbe ‘sed in an inepaation network to generate additonal zeo-crossing points corresponding to lower bits. Consider the ciruit of Figure 645, where the 1 and’ Q euputs of folding circuit are apqlied t four emiter Followers and a resistor network, providing an interpolation factor of 2 by generating ‘ukliional ferential voltages Vand Vg. Note thatthe symmetry Of he imerpolaion network suppresses aration of Vge ofthe emitter followers as the input varies [29] th Interpolation « 1 648 Imeplaton cit for phase and unasas Analg Digi Coon Achieses Chap. 6 “Theintspolation factor of the above circuit canbe increased by inreas- ing the umber ofthe interpolation resistors, ba at the cst of increasing the ‘output ime constant. In pratce, interpolation factors as high a 8 have been uilized [29 ltisiteresting to note that while the idea of folding was originally con «ceived to produce a residue signal whose amplitude could be finely digitized (as in vest architecture, the combination of folding and interpolation extrac information only from zero-crassing points ofthe reside with ite ‘cones about its amplitude For interpolation factors greater than 2, the deviation of folding signals ‘rom anideal tiangular waveform sill invoduces diferent nonlinearity. As sown in Figure 646 for an interpolation lator of 4, while the zeo-erossing point of Vax coincide with ther ideal values, those of Vig and Va devite from thee ideal values because the top (or bottom portion of folding signal (were deviation from an ideal ramp is maximum) linearly combined with ‘he middle portion of anoher folding signal (where deviation is mim), Yue Nye ‘The above observation may suggest that he DNL canbe reduced if the fotaing signalsare brought closer together ie, thediffeencebetween V, and Vj is reduced) because te interpolation is then performed on the linear portions ofthe folding signals. However, tis violates one othe assumptions ‘originally made in deriving the folding signals of Figure 6.42: when one lifeental pair begins to turn on its adjacent stages are not completly off and contribute tothe output variation [2], Thus. the difference between, and Viusiy must be chosen soa to minimize the overall DNL, Simulations Indicate that hiseror teaches a minimum for Vj) —V; © SV [22]. Tes ‘or can als be reduced by nonlinear interpolation [29], using unewsl resistors the interpolation network, Sec. 65— Ielatie ad Flag Ashita 0 Several diferent implementations of folding and interpolation architec tures have been reported (22,24, 29]. In addition othe circuit of Figure 6.4, the topology shown in Figure 6.47 sfequentl used This circuit consists of four diferetal pais whose outputs are combined using fur emitter follow ‘es. The two sets of interconnected emiter followers in essence consttte two “analog wied-GR” circuits o that thei outputs go high i the collector voltage of one of te diferental pairs goes high, While in the folding cir ‘ait of Figure 6: several colletor ae connected tothe same node, this contributing subsantal capacitance at that noe, the circuit of Figure 6.47 does no suffer fom this drawback and drives the summing noe by emir follower. i 67 Fling ic wit anal wie.0R, ‘A critical issue in foing ADCs isthe iming eror between the coarse stage and the folding amplifier. Since these «wo eiteits ae inherently if ferent, they intoduce unequal delays in the analog signal, thus presenting Sliehily different poins of the input to the subsequent latches. AS a es the coarse stage may “point othe wrong cycle inthe folding characteris ies. Various conection techniques ar often ulized to eliminate this ertor (24.25) Folding architectures have been implemented primarily in pola tech nology. The smal offset, highspeed switching. and exponential -V charac teristics of bipolar transistors allow solutions of $bits in inherently one-step architectures, achieving conversion rates above 600 MHz (24), In CMOS, technology on the eter hand, large offsets, low transconductance, and short channel effets make it dificult to achieve resolutions above approximately 6 bits withour offset cancellation. For example. CMOS interpolating ADC twiltinaI-pm technology requires an 8-V supply to msigain an LSB voltage _reater than the inp offset of ts constituent comparators 19},