1.

Circuit Diagram

2. All MOSFETS in saturation

Vgs(M1)= Vgs(M2)=V1-Vgnd= V1
Vgs(M3)= Vgs(M4)=V2-Vgnd= V2
3. Drain Current during saturation region of operation, for NMOS
ID(sat)=kn(Vgs-Vtn)2
where,kn=nCox

( 2WL )

4. V1=VDC1+0.5id1
V2= VDC1-0.5id1
V3= VDC2+0.5id2
V4= VDC2-0.5id2
5. Current through
M1(NMOS)=ID1,
M2(NMOS)=ID2
M3(NMOS)=ID3
M4(NMOS)=ID4
M5(PMOS)=ID5
M6(PMOS)=ID6
M8(PMOS)=ID8
M9(PMOS)=ID9
6. ID1=ID2 = kn(Vgs-Vtn)2
= kn(V1-Vtn)2
ID3=ID4 = kn(Vgs-Vtn)2
= kn(V2-Vtn)2

7.

D1

D4

D2

D4

(V1-Vtn)-

(V2-Vtn)

(V1- V2)

[(VDC1+0.5id1)- (VDC1-0.5id1)]

id1

8.

9. ID1 is injected to be the bias current of the differential-FVF M5M7 and, similarly, the bias
current of the differential FVF M8-M10 is obtained by injecting I D4 into the drain terminal of
M8. This results in
ID5=ID1
ID8=ID4
10. V3- V4 =( V3-Vx)-( V3- Vx)
= Vsg6-Vsg5
V3- V4 =( V3-Vy)-( V3- Vy)
= Vsg9- Vsg8
V3- V4=Vsg6-Vsg5=Vsg9- Vsg8
11.

V3- V4= id2=Vsg6-Vsg5=Vsg9- Vsg8

12. ID(sat)=kp(Vsg-|Vtp|)2
where, kp=pCox

( 2WL )

13. ID6 = kp(Vsg6-|Vtp|)2

= kp(V3- V4 +Vsg5-|Vtp|)2
= kp( id2+Vsg5-|Vtp|)2
= kp(id2-|Vtp|+Vsg5)2
ID8 = kp(Vsg8-|Vtp|)2
= kp(V3- V4 +Vsg8-|Vtp|)2

= kp(id2+Vsg9-|Vtp|)2
= kp(id2-|Vtp|+Vsg9)2
14. Consider |Vtp|= Vtn
|Vtp|= Vtn= V1-(ID1/kn)0.5
|Vtp|= Vtn= V2-(ID4/kn)0.5
15. V01=Vc3+(ID6 - ID2)R
V02=Vc3+(ID8 - ID3)R
16.Vout

= V01- V02
=(ID6 - ID2)R-(ID8 - ID3)R
=( ID6-ID2-ID8+ID3)R
=( ID6-ID8+ID3-ID2)R
=( ID6-ID8)R+(ID3-ID2)R
=