TRAP ;

this interrupt is a non maskable interrupt . it is unaffected by any mask or interrupt

enable. Trap has the highest priority . trap interrupt is edge and level triggered . this
means that the trap must go high and remain high until it is acknowledged . this
avoids false triggering caused by noise and transients.
As shown in the figure the positive edge of trap signal sets the D flip flop however
due to the and gate it is necessary to sustain high level on the trap input there ate
two ways to clear trap interrupt.
1- By resetting microprocessor i.e. giving a low signal on resetin pin ( external
signal)
2- By giving a high trap acknowledge (internal signal)
After recognition of trap interrupt . 8085 internally generates a high trap
acknowledge which clears the flip flop . once the trap is acknowledge the 8085
completes its current instruction . it then pushes the address of the next instruction
i.e. return address onto the stack and loads p c with the fixed bector address 0024 H
. due to this 8085 starts execution of instruction from address 0024 H which is the
starting address of an interrupt service routine for trap.
RST 7.5
The RST 7.5 interrupt is a maskable interrupt . it has the second highest priority . as
shown in figure it is positive edge triggered . and the positive edge trigger is stored
internally by the D flip flop until it is cleared by software reset using SIM instruction
or by internally generated ACKNOWLEDGE signal.
The positive edge signal on the rst 7.5 pin sets the D flip flop. If the mask bit M 7.5
is 0 i.e. RST 7.5 is unmasked then 8085 completes its current instruction . it then
pushes the address of the next instruction onto the stack and loads PC with the
fixed vector address 003CH . Due to this 8085 starts execution of instruction from
address 003CH . which is the starting address of an interrupt service routine for RST
7.5 .