POLITEKNIK SULTAN HAJI AHMAD SHAH KUANTAN

DEPARTMENT OF ELECTRICAL ENGINEERING

DEE6113 CMOS IC DESIGN

Practical Work 3

Layout Design and Simulation of

CMOS Inverter
Practical Work
Report
(Cognitive)

Practical Skill
Marks
(Psychomotor)

Total
Marks

1.

/ 30

/ 70

/ 100

2.

/ 30

/ 70

/ 100

Registration
No.

No

Name

CLASS

LECTURER NAME

: PN. NOORFOZILA BINTI BAHARI

DATE SUBMITTED

(Note: Submit this page along with the practical skill rubric after each Practical Work is completed)

Practical Work Report Marks Distribution

Report format:
1.

Title and Outcomes

/4

2.

Result

/ 12

3.

Discussion

/ 10

4.

Conclusion

/4
TOTAL :

/ 30

DEE6113 CMOS IC Design

PRACTICAL WORK 3
3.1 TITLE: Layout Design and Simulation of CMOS Inverter.
3.2 LEARNING OUTCOMES
At the end of this practical work session, the student should be able to:
1. design the layout of:
a) vertical inverter layout.
b) horizontal inverter layout.
c) inverter with dual contact and substrate.
d) IC 4069 (CMOS inverter gate IC).
2. simulate CMOS inverter and obtain voltage transfer characteristics (VTC).
3. measure propagation delay.
3.3 EQUIPMENT/TOOLS
PC Set & Microwind 2.6a software.
3.4 PROCEDURE
Part 1 : Designing and simulating vertical CMOS inverter layout

Open the Microwind Editor window.

Select the Foundry file from File menu. Select cmos012.rul file.
Draw the CMOS inverter layout as shown in figure 3.1.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
Make sure to obey the design rules.

Figure 3.1: Vertical CMOS inverterLayout

Run DRC by selecting:

>Analysis>Design Rule Checker
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DEE6113 CMOS IC Design

Save your layout.

Apply a clock to the input. Click on the clock icon, and then click on the metal at the gate. The
clock menu appears, change the name to <<Input>>.
Set the value of the input pulse as the following:
Time low = 0.2 ns
Time high = 0.2 ns
Rise time = Fall time = 0.001 ns
Click OK.
To watch the output, click on the Visible icon, and then click on the metal that connects the
Drains. Change the name to <<Output>>. Click OK. The Visible property is then sent to the
node.
Simulate the inverter layout by selecting:
>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.
The timing diagram of the inverter appear, as shown in figure 3.2.
Measure the optimized area of the layout (the unit is lambda2).

Figure 3.2: Timing diagram of vertical CMOS inverter layout

Theory:
Propagation delay
From figure 3.2, when the input rises to logic 1, the output falls to logic 0, with a 5ps delay
(tpHL). When the input falls to logic 0, the output rises to logic 1, with a 15ps delay.
The propagation delay (tp) of the inverter is determined by using the following equation:
tp = ( tpHL + tpLH ) / 2 = ( 5 ps + 15ps ) / 2 = 10 ps where
tpHL = the fall time or the time it takes to change from logic 1 to logic 0.
tpLH = the rise time or the time it takes to change from logic 0 to logic 1.
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DEE6113 CMOS IC Design

Layout optimized area

The optimized area of the layout is determined by the following:
Area = Layout Width x Layout Length = 33 x 54 = 1782 2
View the Voltage Transfer Curve (VTC) of the inverter by clicking the voltage vs. voltage tab
as shown in figure 3.2. The VTC of the inverter is shown in figure 3.3.

Figure 3.3: VTC of vertical CMOS inverter layout

Theory :
When the input voltage is low (logic 0), the output voltage is high (logic 1). As input voltage
increases, the output voltage decreases, and at the input voltage = VDD/2 boundary, the output
voltage decreases abruptly. At that point, the value of input voltage is the commutation or
interchange point of the inverter, designated as Vc. As input voltage is further increased towards
VDD, the output voltage decreases to 0 V, which corresponds to the logic 0 of the inverter.
From figure 3.3, it is determined that VDD/2 = 0.6V, which resulted in Vc = 0.541V.

Part 2 : Designing and simulating horizontal CMOS inverter layout.

Open the Microwind Editor window.

Select the Foundry file from File menu. Select cmos012.rul file.
Draw the CMOS inverter layout as shown in figure3. 4.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
Make sure to obey the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker
Save your layout.
Page | 3

DEE6113 CMOS IC Design

Figure 3.4: Layout of horizontal CMOS inverter layout

Simulate the inverter layout and get the:
a) timing diagram of the inverter
b) VTC of the inverter
c) Propagation delay

Part 3 : Designing and simulating CMOS inverter layout with dual contact and substrate.

N-Well

Figure 3.5: Layout of vertical CMOS inverter layout with dual contact and substrate.

Open the Microwind Editor window.

Select the Foundry file from File menu. Select cmos012.rul file.
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DEE6113 CMOS IC Design

Draw the CMOS inverter layout as shown in figure 3.5.

Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
Make sure to obey the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker
Save your layout.
Simulate the inverter layout and get the:
a) timing diagram of the inverter
b) VTC of the inverter

Part 4 : Designing the layout of IC 4069 (CMOS inverter ).

Design the layout of IC 4069 based on the CMOS IC logic gates shown in figure 3.6.

Figure 3.6 : Internal Structure of IC 4069

Do the DRC to ensure that your design conforms to all design rules.
Measure the optimized area of the layout (the unit is 2).

3.5 RESULTS
In your report, include the following:
1. Part 1: Vertical CMOS Inverter
a) inverter layout.
b) input / output timing diagram
c) switching threshold voltage, Vc
(3 marks)
2. Part 2: Horizontal CMOS Inverter
a) inverter layout.
b) Input / output timing diagram
c) switching threshold voltage, Vc
(3 marks)
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DEE6113 CMOS IC Design

3. Part 3: CMOS Inverter with dual contacts and substrate

a) inverter layout.
b) input / output timing diagram.
c) switching threshold voltage, Vc
(3 marks)
4. Part 4: IC 4069 (CMOS inverter gate IC) and its layout size.
a) IC layout
b) The optimized area of the IC layout
(3 marks)

3.6 DISCUSSION
1.

Make a comparison between the optimized area of the layouts in Part 1, Part 2 and Part 3.
(2 marks)

2.

Make a comparison between the values of Vc for the inverter in Part 1, Part 2, Part 3 and
Part 4.
(2 marks)

3.

Calculate the propagation delay of each layout design in Part 1, Part 2 and Part 3.
(3 marks)

4.

From the comparison in Question 2 and 3, determine which layout design is the best.
Explain your answer.
(3 marks)

3.7 CONCLUSION
Give TWO(2) conclusions for this practical work.
(4 marks)

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DEE6113 CMOS IC Design

PRACTICAL SKILL ASSESSMENT RUBRIC

DEE6113 CMOS IC DESIGN
PRACTICAL WORK 3
Student Name :

Class :

Student ID# :

Date :

ASPECTS

A.

Technology feature

B.

Design rule

C.

Transistor size

D.

Metal layers

E.
F.

No DRC error
display
Layout Design
input / output /
floorplan

EXCELLENT
4-5
Use correct technology feature
for ALL parts of the layout.
Follow lambda design rule for
minimum width and spacing for
ALL polygons.
Use correct PMOS and NMOS
transistor size.
Use correct number of metal
layers and width.
Able to produce No DRC error
display for ALL layouts.

SCORE DESCRIPTION
MODERATE
2-3
Use correct technology feature
for parts of the layout.

POOR
1

SCALE

Use other technology feature.

x1

Follow lambda design rule for

MANY of the polygons.

Follow lambda design rule for

ONLY a few of the polygons.

x1

Use acceptable PMOS and NMOS

transistor size.
Use correct metal layers but
incorrect width.
Able to produce No DRC error
display for some of the layouts.

Use incorrect PMOS and

NMOS transistor size.
Use incorrect metal layers and
width.
Not able to produce No DRC
error display at ALL.
Produce acceptable floorplan
and input / output layout
design.
Not able to produce any
simulation for ALL of the
layouts.
Produce large layout size (end
product).

Produce good floorplan and

input / output layout design.

Produce appropriate floorplan

and input / output layout design.

Layout simulation

Able to produce the simulation

of ALL layouts correctly.

Able to produce the simulation

for some of the layouts correctly.

H.

Layout size (end

product)

Produce small layout size (end

product).

Produce acceptable layout size

(end product).

TOTAL

SCORE

x2
x2
x2
x2

x2
x2
/ 70

...
Supervisor Name and Signature