Doria, Jess David A.

CPE101L A11
Experiment 2
Universal Gates and Simplification of Boolean Functions

Interpretation of Results
In Table 1: NAND Implementation, logic gate functions were expressed in terms of
NAND gates. Truth tables were then generated from the logic diagram and were found that it is
the same the original logic gate. The logic equations were also formulated. Some diagrams
require longer equations since two or more NAND gates were used. The same goes for Table
2: NOR Implementation. In simplifying the given expression, the Karnaugh Maps (K-Maps) was
used in order to express the expressions into its desired form. As for finding the minterms and
maxterms, several theorems and axioms were used during the process.

Conclusion
Logic gates can be expressed in NAND or NOR gates, or what we call the universal
gates. A simple XOR gate can be expressed in one gate, but in using NAND or NOR gates,
several gates are used and the connections are rather complex. It may seem a bit complicated,
but it has its own advantage. NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic families. Karnaugh Maps (KMaps) may be regarded as a pictorial form of a truth table. This map method provides a simple,
straight-forward procedure for minimizing Boolean functions. In dealing with longer expressions,
it is tedious to generate truth tables wherein it only encompasses a single gate. On the contrary,
K-Maps can deal with such complexity and can longer expressions.