FULL CHIP LEVEL IMPLEMENTATION OF REED

SOLOMON ENCODER
1

AMAR NARAYAN, 2SHEETAL BELALDAVAR, 3VENKATESHAPPA

M.Tech Student, Dept. of ECE, MSEC, 2M.Tech Student, Dept. of ECE, MSEC, 3Associate Professor, Dept. of ECE, MSEC

Abstract- Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital
communications and storage .The Reed-Solomon encoder takes a block of digital data and adds extra "redundant" bits. The
number and type of errors that can be corrected depends on the characteristics of the Reed-Solomon code .The Reed-Solomon
Encoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject
to errors before reception . In this paper Full Chip level Implementation of Reed Solomon Encoder has been carried out. In
Full Chip Level Implementation, in order to optimize the area of the design, SIPO and PISO shift registers are implemented
and also the I/O pads, VDD and VSS pads are added in to the design. The timing, area and the power values which are
obtained during Synthesis are as follows: Timing=0.0(Met), Area=9965.160037 and Power=2.33878mW respectively and the
physical design steps such as Floor Planning, Placement, CTS, Routing and Verification are carried out in the design.
Index Terms- RS Encoder, SIPO, PISO, Floor Planning, Placement, CTS, Routing.

I. INTRODUCTION

II. IDENTIFICATION OF NUMBER OF I/O

SIGNAL PINS

The Reed-Solomon encoder takes a block of digital

data and adds extra "redundant" bits. Errors occur
during transmission or storage for a number of reasons
(for example noise or interference, scratches on a CD,
etc). The Reed-Solomon decoder processes each block
and attempts to correct errors and recover the original
data. The Reed-Solomon Encoder is used in many
Forward Error Correction (FEC) applications and in
systems where data are transmitted and subject to
errors before reception. The following figure 1 shows
the typical Reed-Solomon Encoder and Decoder
System.

In order to optimize the area of the design, i.e, the

number of I/O pins, SIPO and PISO shift registers are
implemented. The SIPO and PISO shift registers are
as explained below.
III. SIPO ( SERIAL IN PARALLEL OUT)
A serial-in/parallel-out shift register is similar to the
serial-in/ serial-out shift register in that it shifts data
into internal storage elements and shifts data out at the
serial-out, data-out, pin. It is different in that it makes
all the internal stages available as outputs. Therefore,
a serial-in/parallel-out shift register converts data
from serial format to parallel format. The following
figure 2 shows the 4 bit SIPO shift register.

(Source: Martyn Riley and Iain Richardson)

Fig 1 Typical Reed Solomon Encoder and Decoder System

The concept of area optimization plays a very

important key role in the determination of
performance of the system. In this paper in order to
optimize the area of the design, SIPO and PISO shift
registers are implemented. The Full chip level
integrated circuit consists of core (logic circuit) and
I/O PAD circuits. Logic cells (standard cell) and
macros are placed inside the core area and I/O PAD
circuits are connected to core for signal
communication with the external world. The I/O Pad
containing I/O circuit and clock circuits protects the
design from any external hazards such as Electro
Static Discharge (ESD) and noises.

Fig 2 4 bit SIPO Shift Register

PISO ( Parallel In Serial Out):A four-bit parallel in - serial out shift register is shown
in the below fig 3. The circuit uses D flip-flops and
NAND gates for entering data (ie writing) to the

Proceedings of IRF International Conference, Chennai, India, 20th April. 2014, ISBN: 978-93-84209-07-0
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Full Chip Level Implementation of Reed Solomon Encoder

register. D0, D1, D2 and D3 are the parallel inputs,

where D0 is the most significant bit and D3 is the least
significant bit. To write data in, the mode control line
is taken to LOW and the data is clocked in. The data
can be shifted when the mode control line is HIGH as
SHIFT is active high. The register performs right
shift operation on the application of a clock pulse.

So from the Table 2 it can be concluded that the total

number of I/O signal Pins after adding SIPO and PISO
shift registers are 32 Pins.
IV. CALCULATION OF NUMBER OF VSS AND
VDD PADS
The following figure 4 shows the arrangement of the
VDD and VSS Pads on the four sides of the design.

Fig 4 Arrangement of VDD and VSS Pads

The following table 3 shows the total number of VDD

and VSS Pads and it can be concluded that the total
number of VDD and VSS Pads which are arranged on
the top, bottom, right and left sides of the design are 8
Pads.

Fig 3 4 Bit PISO Shift Register

The total number of Pins used in the Block level

implementation of the Reed Solomon Encoder design
is as shown below in the table 1.
Table 1 Total Number of Pins Used in the Block Level
Implementation

Table 3 Total Number of VDD and VSS Pads

From the table 3 it can be seen that the total number of

VDD and VSS Pads which are arranged on the top,
bottom, right and left sides of the design are 8 Pads.
V. DESIGN OF TOP DESIGN FILE (TDF)
So total number of Pins used initially in the design of
the Reed Solomon Encoder including the VSS (4 Pins)
and VDD (4 Pins) are 267 Pins. During Chip Level
Implementation of the design the Verilog code is read
after adding SIPO and PISO shift registers into the
design. Therefore the total number of Input/ Output
Signal Pins obtained after adding SIPO and PISO shift
registers are as shown below in the table 2.

In this step the .tdf file is uploaded into the compiler

using the following command:Source -echo rs_encode.tdf file is used to get the Input
arrangement of I/O cells. It contains pin and port
information and also contains information regarding
all the pads which are placed on the four sides of the
design ie. On the right, left , top and bottom.

Table 2 Total Number of I/O Pins in Chip Level

Implementation

After reading the .tdf file next step is Floor Planning.

Floorplan is carried out which includes the following
steps: Floor plan initialization
Creating power and ground rails
Pre routing Standard cell
After Floor Planning next step is Placement, during
Placement the two more files are created in the
synthesis process.

Proceedings of IRF International Conference, Chennai, India, 20th April. 2014, ISBN: 978-93-84209-07-0
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Full Chip Level Implementation of Reed Solomon Encoder

They are
SDC Synopsys Design Constraint read_sdc
./<path/filename.sdc>
DEF Design Exchange Format read_def
./<path/filename.def>

extraction, optimization, and hold-time violation

fixing on the design. The following figure 7 shows the
CTS summary report after applying clock_opt
constraint.

Once the SDC and DEF file has been read, the macros
and standard cells are added into the design.
The following figure 5 shows the placement of macro
and standard cells.

Fig 7 CTS Summary Report

The following figure 8 shows the clock signals in the

design after CTS.
Fig 5 Placement of Macro and Standard cells

Next step after Placement is Clock Tree

Synthesis(CTS)
CTS is the process of distributing clock signals to
clock pins based on physical/layout information.. The
following figure 6 shows the clock signals in the
design before CTS.

Fig 8 Clock signals in the design after CTS

After CTS, the next step is Routing.

Routing is the physical realization of all those
interconnects between pins which are connected by an
electrical circuit.
The constraint Route_opt is used to do routing
optimization for the design. The following figure 9
shows the Routing Summary report after applying the
command route_opt.

Fig 6 Clock signals in the design before CTS

The constraint Clock_opt is used during CTS, which

performs clock tree synthesis, routing of clock nets,

Proceedings of IRF International Conference, Chennai, India, 20th April. 2014, ISBN: 978-93-84209-07-0
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Full Chip Level Implementation of Reed Solomon Encoder

after adding the I/O, VSS and VDD pads in to the

design).
Table 4 Comparison between Area, Timing and Power
Before
After

Fig 9 Routing Report

Route optimization can be done by reducing wire

length and number of vias, and also by removing
unnecessary jogs. The following figure 10 shows the
final routed design.

Area

134181.71

9965.160037

Timing

0.74

0.00(Met)

Power

12.5113mW

2.338786mW

CONCLUSION
In this paper Full Chip level Implementation of Reed
Solomon Encoder has been carried out. During the
design implementation SIPO and PISO shift registers
are added in order to optimize the area , VDD and
VSS pads are also added in to the design. The timing,
area and the power values which are obtained during
Synthesis are as follows:= Timing = 0.00(Met),
Area=9965.160037 and Power=2.338786 Mw
respectively and the physical design steps such as
Floor Planning, Placement, CTS, Routing and
Verification.are carried out in the design.

Fig 10 Final Routed Design

REFERENCES

After Routing, Physical Verification is carried out and

which checks the correctness of the layout design.
VI. POST LAYOUT TIMING CHECK
In Post layout timing, it is necessary to carry out the
timing check (delay value) in order to meet the timing
specifications. Along with timing it is also mandatory
to carry out the power and area report checks on the
design in order to meet the given specifications. The
following table 4 shows the comparison between
timing, area and the power values which are obtained
during the synthesis process of the design (before and

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Proceedings of IRF International Conference, Chennai, India, 20th April. 2014, ISBN: 978-93-84209-07-0
126