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Analog Elec EDB2034 Jan 2016 - MOSFET - Intro Biasing PDF
Analog Elec EDB2034 Jan 2016 - MOSFET - Intro Biasing PDF
Analog Elec EDB2034 Jan 2016 - MOSFET - Intro Biasing PDF
EDB 2034
Analogue Electronics (Jan 2016 Semester)
MOS Field-Effect Transistors (MOSFET) Intro & Biasing
Lecturer:
Phone:
Email:
Page 1
Introduction to MOSFETs
MOSFET Circuit at DC
n-channel MOSFET
When vDS is increased to the value that reduces the voltage between gate and
channel at the D end to VT (or vGS vDS = VT), the channel depth at the D end
decreases to almost ZERO. Channel is said to be pinched-off.
Increasing vDS beyond this value has little effect of iD. iD becomes constant
(saturate).
The voltage vDS at which saturation occurs is denoted as vDsat = vGS-VT
Cox ox
tox
[F/m2]
Q CV
Effective voltage
The electric field produced by vDS in the negative x direction can be written as
E x
dv x
dx
The electric field produced causes the electron charge dq to drift toward the drain
with velocity of
dv x
n - Mobility of electrons
dx
n E x n
dt
dx
Finally the resulting drift current, i can be obtained as follows:
dq dq dx
dt dx dt
i nCoxW vGS v( x) VT
dv x
dx
iD i nCoxW vGS v( x) VT
dv x
dx
iD dx nCoxW vGS v( x) VT dv x
vDS
iD dx
nCoxW vGS v( x) VT dv x
1 2
W
iD nCox
L
1 2
V
v
vDS
GS T DS
2
iD Triode region
To obtain current in the saturation region, we substitute vDS = vGS VT into above
equation which yield
iD
1
W
2
nCox vGS VT
2
L
kn' nCox
Therefore iD vDS can be rewritten as
1 2
W
iD kn' vGS VT vDS vDS
2
L
1 W
2
iD kn' vGS VT
2 L
Aspect ratio
(Triode region)
(Saturation region)
Solution:
a)
Cox
ox
tox
3.45 1011
8 10
4.32 103 F / m2
iD
100 106
1 ' W
2
kn vGS VT
2 L
1
8
2
194 106
vGS 0.7
2
0.8
W
iD kn'
L
1 2
V
v
vDS
GS T DS
2
W
iD kn'
L
vGS VT vDS
v
rDS DS
iD small _ v
DS
1000
W
kn' vGS VT
L
vGS 1.22V
- CUTOFF:
vGS VT
- TRIODE:
vGS VT
(Induced Channel)
vGD VT
In terms of vDS,
vGS vDS VT
Rearranging above equation will result in
vDS vGS VT
W
iD kn'
L
1 2
V
v
vDS
GS T DS
2
W
iD kn'
L
vGS VT vDS
v
W
rDS DS
kn' vGS VT
iD small _ v
L
DS
VOV VGS VT
Which will lead to
W
rDS kn'
L
V
OV
- SATURATION:
vGS VT
(Induced Channel)
The pinched off at drain end occurs by raising vDS to a value that results the gateto-drain voltage, VGD falling below VT,
vGD VT
(Pinched-off Channel)
In terms of vDS,
vDS vGS VT
(Pinched-off Channel)
The boundary between the triode and the saturation region is given by
vDS vGS VT
(Boundary)
iD
1 ' W
2
kn vGS VT
2 L
Channel-Length Modulation:
- Previously we assume that increase of vDS beyond vDSsat has no effect on channels
shape.
- In reality, as vDS is increased beyond VDSsat, the channel pinch-off point is moved
slightly away from the drain, toward the source.
- This is due to the additional voltage applied beyond vDSsat which accelerates the
electrons that reach the drain end of the channel and sweeps them across the
depletion region into the drain.
- With depletion-layer widening, the
channel length effect is reduced
from L to L - L.
- This phenomenon is known as
channel-length modulation.
1 ' W
2
kn
v
GS T
2 L L
1 ' W
1
v V 2
iD kn
GS
T
2
L 1 L
L
iD
iD
1 ' W
kn
2
L
L
2
1
vGS VT
L
and
L ' vDS
Where is a process technology parameter (m/V).
Previously assumed
L L
iD
1 ' W
kn
2
L
'
2
1 vDS vGS VT
L
1 W
iD kn'
1 vDS vGS VT 2
2
L
A typical set of iD-vDS characteristics showing the effect
of channel-length modulation is as follows:
From the plot, when the straight-line are extrapolated,
they intercept at the point vDS = -VA (Early Voltage).
Due to VA, the output resistance, ro can be derived as
V
ro A
ID
vDS VGS VT
(2) vGD VT
i-v Characteristics:
W
iD nCox
L
1 2
V
v
vDS
GS T DS
2
v
rDS DS
iD small _ v
DS
C
v
n ox L GS T
vDS VGS VT
i-v Characteristics:
1 W
iD kn'
1 vDS vGS VT 2
2
L
iD
1 ' W
2
kn vGS VT
2 L
Since,
1 ' W
W
2 1
2
kn vGS VT kn' VOV
2 L
2 L
1
32
2
0.4m 100 VOV
2
1
iD
VOV 0.5V
3.25k
ID
0.4m
From D region,
V V
2.5 0.5
RD DD D
5k
ID
0.4m
vGD VD VD 0 VT 0.6V
NMOS transistor is operating in Saturation region.
iD
1 ' W
W
2 1
2
kn vGS VT kn' VOV
2 L
2 L
1
4
2
80 200
VOV
2
0.8
VOV 0.4V
VGS VG VS VG 0 1.0V VG VD
From D region,
V V
3 1
RD DD D
25k
ID
80
W
iD nCox
L
1 2
V
v
vDS
GS T DS
2
2
iD 1m 5 1 0.1 0.1 0.395mA
2
V V
5 0.1
RD DD D
12.4k
ID
0.395m
V
0.1
rDS DS
253
ID
0.395m
VG VDD
RG 2
10M
10V
5V
RG 2 RG1
10M 10M
VGS 5 I D 6k
Using
iD
1 ' W
2
2 1
kn vGS VT 1m 5 I D 6k 1
2 L
2
2
18I D
25I D 8 0
I D 0.89mA; I D 0.5mA
Since we have two solution for ID, check the first solution yield
VS I D 6k 0.89m 6k 5.34V
VS VG
VS I D 6k 0.5m 6k 3V
VGS VG VS 5 3 2V
VD 10 I D RD 10 0.5m 6k 7V
Since VD > VG - VT, the transistor is indeed operating in saturation region.