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Pic16f631 Microcontroller
Pic16f631 Microcontroller
Data Sheet
20-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Program
Data Memory
Memory 10-bit A/D Timers
Device I/O Comparators SSP ECCP+ EUSART
Flash SRAM EEPROM (ch) 8/16-bit
(words) (bytes) (bytes)
PIC16F631 1024 64 128 18 — 2 1/1 No No No
PIC16F677 2048 128 256 18 12 2 1/1 Yes No No
PIC16F685 4096 256 256 18 12 2 2/1 No Yes No
PIC16F687 2048 128 256 18 12 2 1/1 Yes No Yes
PIC16F689 4096 256 256 18 12 2 1/1 Yes No Yes
PIC16F690 4096 256 256 18 12 2 2/1 Yes Yes Yes
VDD 1 20 VSS
RA5/T1CKI/OSC1/CLKIN 2 19 RA0/C1IN+/ICSPDAT/ULPWU
RA4/T1G/OSC2/CLKOUT 3 18 RA1/C12IN0-/ICSPCLK
RA3/MCLR/VPP 4
PIC16F631
17 RA2/T0CKI/INT/C1OUT
RC5 5 16 RC0/C2IN+
RC4/C2OUT 6 15 RC1/C12IN1-
RC3/C12IN3- 7 14 RC2/C12IN2-
RC6 8 13 RB4
RC7 9 12 RB5
RB7 10 11 RB6
VDD 1 20 VSS
RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF/ICSPCLK
RA3/MCLR/VPP 4 RA2/AN2/T0CKI/INT/C1OUT
PIC16F677
17
RC5 5 16 RC0/AN4/C2IN+
RC4/C2OUT 6 15 RC1/AN5/C12IN1-
RC3/AN7C12IN3- 7 14 RC2/AN6/C12IN2-
RC6/AN8/SS 8 13 RB4/AN10/SDI/SDA
RC7/AN9/SDO 9 12 RB5/AN11
RB7 10 11 RB6/SCK/SCL
VDD 1 20 VSS
RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF/ICSPCLK
RA3/MCLR/VPP 4 RA2/AN2/T0CKI/INT/C1OUT
PIC16F685
17
RC5/CCP1/P1A 5 16 RC0/AN4/C2IN+
RC4/C2OUT/P1B 6 15 RC1/AN5/C12IN1-
RC3/AN7/C12IN3-/P1C 7 14 RC2/AN6/C12IN2-/P1D
RC6/AN8 8 13 RB4/AN10
RC7/AN9 9 12 RB5/AN11
RB7 10 11 RB6
VDD 1 20 VSS
RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF/ICSPCLK
PIC16F687/689
RA3/MCLR/VPP 4 17 RA2/AN2/T0CKI/INT/C1OUT
RC5 5 16 RC0/AN4/C2IN+
RC4/C2OUT 6 15 RC1/AN5/C12IN1-
RC3/AN7/C12IN3- 7 14 RC2/AN6/C12IN2-
RC6/AN8/SS 8 13 RB4/AN10/SDI/SDA
RC7/AN9/SDO 9 12 RB5/AN11/RX/DT
RB7/TX/CK 10 11 RB6/SCK/SCL
VDD 1 20 VSS
RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF/ICSPCLK
RA3/MCLR/VPP 4 17 RA2/AN2/T0CKI/INT/C1OUT
PIC16F690
RC5/CCP1/P1A 5 16 RC0/AN4/C2IN+
RC4/C2OUT/P1B 6 15 RC1/AN5/C12IN1-
RC3/AN7/C12IN3-/P1C 7 14 RC2/AN6/C12IN2-/P1D
RC6/AN8/SS 8 13 RB4/AN10/SDI/SDA
RC7/AN9/SDO 9 12 RB5/AN11/RX/DT
RB7/TX/CK 10 11 RB6/SCK/SCL
20-pin QFN
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
VSS
VDD
20
19
18
17
16
RA3/MCLR/VPP 1 15 RA1/AN1/C12IN0-/VREF/ICSPCLK
(1) 2
RC5/CCP1/P1A 14 RA2/AN2/T0CKI/INT/C1OUT
(1) PIC16F631/677/
RC4/C2OUT/P1B 3 685/687/689/690 13 RC0/AN4/C2IN+
RC3/AN7/C12IN3-/P1C(1) 4 12 RC1/AN5/C12IN1-
(2)
RC6/AN8/SS 5 11 RC2/AN6/C12IN2-/P1D(1)
10
7
6
9
RC7/AN9/SDO(2)
(3)
RB6/SCK/SCL(2)
RB5/AN11/RX/DT(3)
RB4/AN10/SDI/SDA(2)
RB7/TX/CK
Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only.
2: SS, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F690 only.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
STATUS Reg
8
PORTC
RC0
3 RC1
MUX
Power-up RC2
Timer RC3
Instruction RC4
Decode and Oscillator
RC5
Control Start-up Timer ALU
RC6
OSC1/CLKI Power-on RC7
8
Reset
Timing
OSC2/CLKO Generation Watchdog W Reg
Timer
Brown-out
Reset
Internal
Oscillator
Block
INT
Configuration
13 8 PORTA
Data Bus
Program Counter
Flash RA0
2K x 14 RA1
Program RA2
RAM
8-Level Stack (13-bit) RA3
Memory 128 bytes
RA4
File
RA5
Registers
Program 14
Bus RAM Addr
9 PORTB
Addr MUX
Instruction Reg
Direct Addr 7 Indirect RB4
8 Addr RB5
RB6
FSR Reg
RB7
STATUS Reg
8
PORTC
RC0
3 RC1
MUX
Power-up RC2
Timer RC3
Instruction
Oscillator RC4
Decode and
Control Start-up Timer ALU RC5
RC6
OSC1/CLKI Power-on 8 RC7
Reset
Timing
OSC2/CLKO Generation Watchdog W Reg
Timer
Brown-out
Reset
Internal
Oscillator
Block
8 256 Bytes
2 Data
Analog-to-Digital Converter Analog Comparators EEPROM
and Reference
EEADR
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
INT
Configuration
13 8
Data Bus PORTA
Program Counter
Flash RA0
4K x 14 RA1
Program RAM RA2
8-Level Stack (13-bit) RA3
Memory 256 bytes
File RA4
Registers RA5
Program 14
Bus RAM Addr
9 PORTB
Addr MUX
Instruction Reg
Direct Addr 7 Indirect RB4
8 Addr RB5
RB6
FSR Reg
RB7
STATUS Reg
8
PORTC
RC0
3 RC1
MUX
Power-up RC2
Timer RC3
Instruction
Decode and Oscillator RC4
Control Start-up Timer ALU RC5
RC6
OSC1/CLKI Power-on 8 RC7
Reset
Timing
OSC2/CLKO Generation Watchdog W Reg
Timer
Brown-out
Reset
Internal
Oscillator
Block
Ultra Low-Power
Timer0 Timer1 Timer2 ECCP+
Wake-up
8 256 Bytes
2 Data
Analog-to-Digital Converter Analog Comparators EEPROM
and Reference
EEADR
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
STATUS Reg
8
PORTC
RC0
3 RC1
MUX
Power-up RC2
Timer RC3
Instruction
Decode and Oscillator RC4
Control Start-up Timer ALU RC5
RC6
OSC1/CLKI Power-on 8 RC7
Reset
Timing
OSC2/CLKO Generation Watchdog W Reg
Timer
Brown-out
Reset
Internal
Oscillator
Block
8 256 Bytes
2 Data
Analog-to-Digital Converter Analog Comparators EEPROM
and Reference
EEADR
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
INT
Configuration
13 8
Data Bus PORTA
Program Counter
Flash RA0
4k x 14 RA1
Program RAM RA2
8-Level Stack (13-bit) RA3
Memory 256 bytes
File RA4
Registers RA5
Program 14
Bus RAM Addr
9 PORTB
Addr MUX
Instruction Reg
Direct Addr 7 Indirect RB4
8 Addr
RB5
FSR Reg RB6
RB7
STATUS Reg
8
PORTC
RC0
3 RC1
MUX
Power-up RC2
Timer RC3
Instruction
Decode and Oscillator RC4
Control Start-up Timer ALU RC5
RC6
OSC1/CLKI Power-on 8 RC7
Reset
Timing
OSC2/CLKO Generation Watchdog W Reg
Timer
Brown-out
Reset
Internal
Oscillator
Block
8 256 Bytes
2 Data
Analog-to-Digital Converter Analog Comparators EEPROM
and Reference
EEADR
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
Access 0-FFFh
Stack Level 1
Stack Level 2 1FFFh
Stack Level 8
FIGURE 2-3: PROGRAM MEMORY MAP
Reset Vector 0000h AND STACK FOR THE
PIC16F677/PIC16F687
Interrupt Vector 0004h
On-Chip 0005h
Page 0 PC<12:0>
Memory 03FFh
0400h CALL, RETURN 13
RETFIE, RETLW
Access 0-3FFh
Stack Level 1
1FFFh
Stack Level 2
Stack Level 8
Access 0-7FFh
1FFFh
3Fh
General 40h
Purpose
Registers
6Fh EFh 16Fh 1EFh
64 Bytes 70h accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
General General
General Purpose Purpose
Purpose Register Register
Register
80 Bytes 80 Bytes
96 Bytes EFh 16Fh
accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
General General
General Purpose Purpose
Purpose Register Register
Register
80 Bytes 80 Bytes
96 Bytes EFh 16Fh
accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 44,205
01h TMR0 Timer0 Module Register xxxx xxxx 81,205
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 44,205
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 36,205
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 44,205
05h PORTA(7) — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 59,205
06h PORTB(7) RB7 RB6 RB5 RB4 — — — — xxxx ---- 69,205
07h PORTC(7) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 76,205
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 44,205
0Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 38,205
0Ch PIR1 — ADIF(4) RCIF(2) TXIF(2) SSPIF(5) CCP1IF(3) TMR2IF(3) TMR1IF -000 0000 41,205
0Dh PIR2 OSFIF C2IF C1IF EEIF — — — — 0000 ---- 42,205
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 86,205
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 86,205
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 88,205
11h TMR2(3) Timer2 Module Register 0000 0000 91,205
12h T2CON(3) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 92,205
13h SSPBUF(5) Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 182,205
14h SSPCON(5, 6) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 181,205
15h CCPR1L(3) Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 128,205
(3)
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 128,205
17h CCP1CON(3) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 127,205
18h RCSTA(2) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 161,205
19h TXREG(2) EUSART Transmit Data Register 0000 0000 153
(2)
1Ah RCREG EUSART Receive Data Register 0000 0000 158
1Bh — Unimplemented — —
1Ch PWM1CON(3) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 145,205
1Dh ECCPAS(3) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 142,205
1Eh ADRESH(4) A/D Result Register High Byte xxxx xxxx 115,205
1Fh ADCON0(4) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 113,205
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F687/PIC16F689/PIC16F690 only.
3: PIC16F685/PIC16F690 only.
4: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
6: When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers 13-2 and 13-3 for more detail.
7: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 44,205
81h OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 37,205
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 44,205
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 36,205
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 44,205
85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 59,205
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 70,206
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 76,205
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 44,205
8Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 38,205
(4) (2) (2) (5) (3) (3)
8Ch PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 39,206
8Dh PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 40,206
8Eh PCON — — ULPWUE SBOREN — — POR BOR --01 --qq 43,206
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 48,206
90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 52,206
91h — Unimplemented — —
92h PR2(3) Timer2 Period Register 1111 1111 91,206
93h SSPADD(5, 7) Synchronous Serial Port (I2C mode) Address Register 0000 0000 188,206
93h SSPMSK(5, 7) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 191,206
(5)
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 180,206
95h WPUA(6) — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 62,206
96h IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 62,206
97h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 213,206
98h TXSTA(2) CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 160,206
99h SPBRG(2) BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 163,206
9Ah SPBRGH(2) BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 163,206
9Bh BAUDCTL(2) ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 162,206
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh ADRESL(4) A/D Result Register Low Byte xxxx xxxx 115,206
9Fh ADCON1(4) — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 114,206
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F687/PIC16F689/PIC16F690 only.
3: PIC16F685/PIC16F690 only.
4: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
6: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.
7: Accessible only when SSPCON register bits SSPM<3:0> = 1001.
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 44,205
101h TMR0 Timer0 Module Register xxxx xxxx 81,205
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 44,205
103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 36,205
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 44,205
105h PORTA(4) — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 59,205
106h PORTB(4) RB7 RB6 RB5 RB4 — — — — xxxx ---- 69,205
107h PORTC(4) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 76,205
108h — Unimplemented — —
109h — Unimplemented — —
10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 44,205
10Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 38,205
10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 120,206
10Dh EEADR EEADR7(3) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 120,206
10Eh EEDATH(2) — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 120,206
10Fh EEADRH(2) — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 120,206
110h — Unimplemented — —
111h — Unimplemented — —
112h — Unimplemented — —
113h — Unimplemented — —
114h — Unimplemented — —
115h WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 70,206
116h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 70,206
117h — Unimplemented — —
118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 105,206
119h CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 98,206
11Ah CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 99,206
11Bh CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 101,206
11Ch — Unimplemented — —
11Dh — Unimplemented — —
11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(3) ANS2(3) ANS1 ANS0 1111 1111 61,206
11Fh ANSELH(3) — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 115,206
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
4: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 44,205
181h OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 37,205
182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 44,205
183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 36,205
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 44,205
185h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 59,205
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 70,206
187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 76,206
188h — Unimplemented — —
189h — Unimplemented — —
18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 44,205
18Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 38,205
18Ch EECON1 EEPGD(2) — — — WRERR WREN WR RD x--- x000 121,206
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 119,206
18Eh — Unimplemented — —
18Fh — Unimplemented — —
190h — Unimplemented — —
191h — Unimplemented — —
192h — Unimplemented — —
193h — Unimplemented — —
194h — Unimplemented — —
195h — Unimplemented — —
196h — Unimplemented — —
197h — Unimplemented — —
198h — Unimplemented — —
199h — Unimplemented — —
19Ah — Unimplemented — —
19Bh — Unimplemented — —
19Ch — Unimplemented — —
19Dh PSTRCON(2) — — — STRSYNC STRD STRC STRB STRA ---0 0001 146,206
19Eh SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 103,206
19Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F685/PIC16F690 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
Data
Memory
7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
For memory map detail, see Figures 2-6, 2-7 and 2-8.
FOSC<2:0>
(Configuration Word Register)
External Oscillator SCS<0>
(OSCCON Register)
OSC2
Sleep
LP, XT, HS, RC, RCIO, EC
OSC1
MUX
IRCF<2:0>
(OSCCON Register) System Clock
(CPU and Peripherals)
8 MHz
111 INTOSC
Internal Oscillator 4 MHz
110
2 MHz
101
Postscaler
1 MHz
MUX
HFINTOSC 100
500 kHz
8 MHz 011
250 kHz
010
125 kHz
001
LFINTOSC 31 kHz
000
31 kHz
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
Figure 3-3 and Figure 3-4 show typical circuits for FIGURE 3-4: CERAMIC RESONATOR
quartz crystal and ceramic resonators, respectively.
OPERATION
(XT OR HS MODE)
FIGURE 3-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
PIC® MCU
HS MODE)
OSC1/CLKIN
PIC® MCU
C1 To Internal
OSC1/CLKIN Logic
C2 RS(1) OSC2/CLKOUT
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
Note 1: A series resistor (RS) may be required for 2: The value of RF varies with the Oscillator mode
quartz crystals with low drive level. selected (typically between 2 MΩ to 10 MΩ).
2: The value of RF varies with the Oscillator mode 3: An additional parallel feedback resistor (RP)
selected (typically between 2 MΩ to 10 MΩ). may be required for proper ceramic resonator
operation.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HFINTOSC
Start-up Time 2-cycle Sync Running
LFINTOSC
IRCF <2:0> ≠0 =0
System Clock
HFINTOSC
2-cycle Sync Running
LFINTOSC
IRCF <2:0> ≠0 =0
System Clock
LFINTOSC HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC
IRCF <2:0> =0 ¼0
System Clock
HFINTOSC
TOST
OSC2
Program Counter PC - N PC PC + 1
System Clock
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Global RABPU bit of the OPTION register must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Analog(1)
Input Mode
VDD
Data Bus
D Q Weak
WR CK Q
WPUA RABPU
RD
WPUA VDD
D Q
WR CK Q I/O Pin
PORTA
VSS
-
+ VT
D Q
WR CK Q
TRISA IULP
0 1
RD
TRISA Analog(1) VSS
Input Mode
ULPWUE
RD
PORTA
D Q
WR CK Q Q D
IOCA
EN Q3
RD
IOCA Q D
EN
Interrupt-on-Change
RD PORTA
To Comparator
To A/D Converter(2)
FIGURE 4-2: BLOCK DIAGRAM OF RA1 FIGURE 4-3: BLOCK DIAGRAM OF RA2
Analog(1) Analog(1)
Input Mode Data Bus Input Mode
Data Bus D Q
D Q VDD VDD
WR WR CK
CK Q Q Weak
WPUA Weak WPUA
RD RABPU RD RABPU
WPUA WPUA
C1OUT
Enable
VDD VDD
D Q D Q
WR CK Q WR CK
PORTA Q C1OUT
PORTA 1
0 I/O Pin
I/O Pin
D Q D Q
WR CK Q WR CK
TRISA VSS TRISA Q VSS
Analog(1) Analog(1)
RD Input Mode RD Input Mode
TRISA TRISA
RD RD
PORTA PORTA
D Q D Q
CK Q Q D Q D
WR WR CK
IOCA Q
IOCA
EN Q3 EN Q3
RD RD
IOCA Q D IOCA Q D
EN EN
Interrupt-on- Interrupt-on-
Change Change
RD PORTA RD PORTA
To Comparator
To A/D Converter(2) To Timer0
To INT
Note 1: ANSEL determines Analog Input mode. To A/D Converter(2)
2: Not implemented on PIC16F631.
WR CK Q D
Q
IOCA
EN Q3
RD
IOCA Q D
EN
Interrupt-on-
Change
RD PORTA
To T1G
To A/D Converter(4)
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3: ANSEL determines Analog Input mode.
4: Not implemented on PIC16F631.
INTOSC
Mode
TMR1LPEN(1)
Data Bus
D Q VDD
WR CK Weak
WPUA Q
RABPU
RD
WPUA
Oscillator
Circuit
OSC2 VDD
D Q
WR CK
PORTA Q
I/O Pin
D Q
WR CK
TRISA Q VSS
INTOSC
RD Mode
TRISA
(2)
RD
PORTA
D Q
CK Q D
WR Q
IOCA
EN Q3
RD
IOCA
Q D
EN
Interrupt-on-
Change
RD PORTA
To TMR1 or CLKGEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RD RABPU
WPUB
SSPEN VDD
D Q
SSPSR
WR CK Q 0
1
PORTB
1
0
I/O Pin
D Q From 1
0
WR SSP
CK
TRISB Q VSS
1
0
RD Analog(1)
TRISB Input Mode
RD
PORTB
D Q
CK Q Q D
WR
IOCB
EN Q3
RD
IOCB Q D
ST
EN
Interrupt-on-
Change
RD PORTB
To SSPSR
To A/D Converter(2)
Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690
only.
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
WR CK Q
TRISB 1
0 VSS
RD Analog(1)
TRISB Input Mode
RD
PORTB
D Q
CK Q Q D
WR
IOCB
EN Q3
RD
IOCB Q D
ST
EN
Interrupt-on-
Change
RD PORTB
To EUSART RX/DT
To A/D Converter(2)
RD
TRISB
RD
PORTB
D Q
WR CK Q Q D
IOCB
EN Q3
RD
IOCB Q D
ST
EN
Interrupt-on-
Change
RD PORTB
To SSP
Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690
only.
1
0
D Q I/O Pin
WR CK Q ‘1’ 0
1
TRISB
VSS
1
0
RD
TRISB
RD
PORTB
D Q
WR CK Q Q D
IOCB
EN Q3
RD
IOCB Q D
EN
Interrupt-on-
Change
RD PORTB
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
WR CK
RD Q CCP1OUT 0
1
PORTC
PORTC
To Comparators
1
0 I/O Pin
To A/D Converter(2) D Q
WR CK
TRISC Q VSS
Note 1: ANSEL determines Analog Input mode. Analog Input
2: Not implemented on PIC16F631. Mode(1)
RD
TRISC
RD
PORTC
To Comparators
To A/D Converter(2)
Note 1: Enabling both C2OUT and P1B will cause Note 1: CCP1 and P1A are available on
a conflict on RC4 and create unpredictable PIC16F685/PIC16F690 only.
results. Therefore, if C2OUT is enabled,
the ECCP+ can not be used in Half-Bridge FIGURE 4-14: BLOCK DIAGRAM OF RC5
or Full-Bridge mode and vise-versa.
Data bus
2: P1B is available on CCP1OUT
PIC16F685/PIC16F690 only. Enable
VDD
D Q
FIGURE 4-13: BLOCK DIAGRAM OF RC4 WR CK
PORTC Q CCP1OUT 0
1
C2OUT EN 1
0 I/O Pin
CCP1OUT EN
D Q
C2OUT EN WR
C2OUT VDD CK Q
TRISC VSS
CCP1OUT EN
CCP1OUT 0
1 RD
TRISC
1
0 I/O Pin
Data Bus
RD
D Q
PORTC
WR CK Q VSS To Enhanced CCP
PORTC
RD
TRISC
RD
PORTC
FIGURE 4-15: BLOCK DIAGRAM OF RC6 FIGURE 4-16: BLOCK DIAGRAM OF RC7
Data Bus
PORT/SDO
Select
VDD
D Q Data Bus
SDO 0
1
WR CK
PORTC Q VDD
D Q 1
0
I/O Pin WR CK
PORTC Q
D Q
WR CK I/O Pin
TRISC Q VSS
D Q
Analog Input
Mode(1) WR CK
RD TRISC Q VSS
TRISC
Analog Input
Mode(1)
RD RD
PORTC TRISC
To SS Input
RD
To A/D Converter(2) PORTC
To A/D Converter(2)
Available on PIC16F685/PIC16F690 only.
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631. Available on PIC16F685/PIC16F690 only.
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111
CCP1CON(2) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000
CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001
SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00--
(1)
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
2: PIC16F685/PIC16F690 only.
FOSC/4
Data Bus
0
8
1
Sync 2
1 cycles TMR0
T0CKI 0
pin 0
T0SE T0CS Set Flag bit T0IF
8-bit
on Overflow
Prescaler PSA
1
8
WDTE PSA
SWDTEN
PS<2:0> 1
WDT
16-bit Time-out
Prescaler 0
16
31 kHz Watchdog
INTOSC Timer PSA
WDTPS<3:0>
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 14.5 “Watchdog Timer (WDT)” for more
information.
TMR1GE
T1GINV
TMR1ON
Set flag bit
TMR1IF on To C2 Comparator Module
Overflow Timer1 Clock
TMR1(2)
Synchronized
EN 0 clock input
TMR1H TMR1L
1
Oscillator
(1) T1SYNC
OSC1/T1CKI 1
Prescaler Synchronize(3)
FOSC/4 1, 2, 4, 8 det
Internal 0
OSC2/T1G Clock 2
T1CKPS<1:0>
TMR1CS
1
INTOSC
Without CLKOUT
T1OSCEN SYNCC2OUT(4) 0
T1GSS
Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set.
6.4 Timer1 Oscillator For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
A low-power 32.768 kHz crystal oscillator is built-in contention may occur by writing to the timer registers,
between pins OSC1 (input) and OSC2 (amplifier while the register is incrementing. This may produce an
output). The oscillator is enabled by setting the unpredictable value in the TMR1H:TMR1L register pair.
T1OSCEN control bit of the T1CON register. The
oscillator will continue to run during Sleep. 6.6 Timer1 Gate
The Timer1 oscillator is shared with the system LP
The Timer1 gate (when enabled) allows Timer1 to count
oscillator. Thus, Timer1 can use this mode only when
when Timer1 gate is active. Timer1 gate source is
the primary system clock is derived from the internal
software configurable to be the T1G pin or the output of
oscillator or when the oscillator is in the LP mode. The
Comparator C2. This allows the device to directly time
user must provide a software time delay to ensure
external events using T1G or analog events using
proper oscillator start-up.
Comparator C2. See the CM2CON1 register
(Register 8-3) for selecting the Timer1 gate source. This
feature can simplify the software for a Delta-Sigma A/D
converter and many other applications.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1
register, as a Timer1 gate source.
Sets Flag
TMR2
bit TMR2IF
Output
Prescaler Reset
FOSC/4 TMR2
1:1, 1:4, 1:16
2 Postscaler
Comparator
EQ 1:1 to 1:16
T2CKPS<1:0>
PR2 4
TOUTPS<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
C1CH<1:0>
2 C1POL To
D Q Data Bus
Q1
C12IN0- 0 EN
RD_CM1CON0
C12IN1- 1
MUX Set C1IF
C12IN2- D Q
2
Q3*RD_CM1CON0
EN
C12IN3- 3 CL
NRESET
C1ON(1) To other peripherals
C1R
C1VIN- -
C1IN+ C1OUT (to SR latch)
C1VIN+ C1 C1OUT
0
MUX +
FixedRef 1
0
C1POL
MUX
CVREF 1
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
C1VREN 2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
C2POL To
D Q Data Bus
Q1
EN
RD_CM2CON0
C12IN3- 3 C2SYNC
C2POL
C2R 0
SYNCC2OUT
MUX
to Timer1 Gate, SR latch
D Q 1
and other peripherals
C2IN+ 0
MUX From TMR1
FixedRef 1 Clock
0
MUX
CVREF 1
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
C2VREN 2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding
PORT TRIS bit = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding
PORT TRIS bit = 0.
VT ≈ 0.6V RIC
Rs < 10K
To Comparator
AIN
CPIN ILEAKAGE(1)
VA VT ≈ 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
SR0
C1OE
PULSS Pulse
Gen(2)
0
C1OUT (from comparator) MUX
S Q 1
C1OUT pin(3)
C1SEN
SR
Latch(1) C2OE
SYNCC2OUT (from comparator)
C2REN R Q 1
MUX
0 C2OUT pin(3)
Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
2: To enable an SR latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured.
• Independent from Comparator operation This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
• Two 16-level voltage ranges
• Output clamped to VSS 8.10.4 OUTPUT RATIOMETRIC TO VDD
• Ratiometric with VDD
The comparator voltage reference is VDD derived and
• Fixed Reference (0.6) therefore, the CVREF output changes with fluctuations in
The VRCON register (Register 8-5) controls the VDD. The tested absolute accuracy of the Comparator
Voltage Reference module shown in Figure 8-8. Voltage Reference can be found in Section 17.0
“Electrical Specifications”.
8.10.1 INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
16 Stages
8R R R R R
VDD
8R VRR
Analog
MUX
15
CVREF(1)
To Comparators
and ADC Module 0
VR<3:0>(1)
C1VREN 4
C2VREN
VP6EN
Sleep
HFINTOSC enable
EN
Fixed Ref 0.6V Fixed Voltage
To Comparators Reference
and ADC Module
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE
REFERENCE MODULES
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 0000
CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000
CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ----
PIR2 OSFIF C2IF C1IF EEIF — — — — 0000---- 0000----
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00--
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
VDD
VCFG = 0
VREF VCFG = 1
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RA4/AN3/T1G/OSC2/CLKOUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-/P1D(1)
ADC
RC3/AN7/C12IN3-/P1C(1)
GO/DONE 10
RC6/AN8/SS(2)
RC7/AN9/SDO(2)
0 = Left Justify
RB4/AN10/SDI/SDA(2) ADFM
1 = Right Justify
RB5/AN11/RX/DT(2) ADON 10
CVREF
VSS ADRESH ADRESL
VP6 Reference
CHS
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is disconnected from analog input (typically 100 ns)
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2μs + T C + [ ( Temperature - 25°C ) ( 0.05μs/°C ) ]
1
V AP P LI ED ⎛ 1 – --------------------------⎞ = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
⎝ n+1 ⎠
(2 )–1
–TC
⎛ ----------⎞
RC
V AP P LI ED ⎜ 1 – e ⎟ = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
⎝ ⎠
– Tc
⎛ ---------⎞
1
V AP P LI ED ⎜ 1 – e ⎟ = V A PP LIE D ⎛ 1 – --------------------------⎞ ;combining [1] and [2]
RC
⎝ ⎠ ⎝ n+1 ⎠
(2 )–1
T C = – C HOLD ( R IC + R SS + R S ) ln(1/2047)
= – 10pF ( 1k Ω + 7k Ω + 10k Ω ) ln(0.0004885)
= 1.37 μs
Therefore:
T ACQ = 2μ S + 1.37μ S + [ ( 50°C- 25°C ) ( 0.05μ S /°C ) ]
= 4.67μ S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
VA CPIN I LEAKAGE(1)
VT = 0.6V CHOLD = 10 pF
5 pF
VSS/VREF-
6V
5V RSS
Legend: CPIN = Input Capacitance VDD 4V
VT = Threshold Voltage 3V
I LEAKAGE = Leakage current at the pin due to 2V
various junctions
RIC = Interconnect Resistance 5 6 7 8 9 10 11
SS = Sampling Switch Sampling Switch
CHOLD = Sample/Hold Capacitance (kΩ)
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
1 LSB ideal
3FBh
Full-Scale
004h Transition
003h
002h
001h
000h Analog Input Voltage
1 LSB ideal
ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEDAT<7:0>: 8 Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEADR<7:0>: 8 Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
S = Bit can only be set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable INTs.
;
NOP ;First instruction after BSF EECON1,RD executes normally
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDAT INSTR (PC + 3) INSTR (PC + 4)
RD bit
EEDATH
EEDAT
Register
EERHLT
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CCPR1L
CCPR1H(2) (Slave)
CCP1
Comparator R Q
(1) S
TMR2
TRIS
Comparator
Clear Timer2,
toggle CCP1 pin and
latch duty cycle
PR2
When TMR2 is equal to PR2, the following three events The CCPR1H register and a 2-bit internal latch are
occur on the next increment cycle: used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
• TMR2 is cleared
• The CCP1 pin is set. (Exception: If the PWM duty The 8-bit timer TMR2 register is concatenated with
cycle = 0%, the pin will not be set.) either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
• The PWM duty cycle is latched from CCPR1L into
clock is used if the Timer2 prescaler is set to 1:1.
CCPR1H.
When the 10-bit time base matches the CCPR1H and
Note: The Timer2 postscaler (see Section 7.1 2-bit latch, then the CCP1 pin is cleared (see
“Timer2 Operation”) is not used in the Figure 11-3).
determination of the PWM frequency.
11.3.3 PWM RESOLUTION
11.3.2 PWM DUTY CYCLE The resolution determines the number of available duty
The PWM duty cycle is specified by writing a 10-bit cycles for a given period. For example, a 10-bit resolution
value to multiple registers: CCPR1L register and will result in 1024 discrete duty cycles, whereas an 8-bit
DC1B<1:0> bits of the CCP1CON register. The resolution will result in 256 discrete duty cycles.
CCPR1L contains the eight MSbs and the DC1B<1:0> The maximum PWM resolution is 10 bits when PR2 is
bits of the CCP1CON register contain the two LSbs. 255. The resolution is a function of the PR2 register
CCPR1L and DC1B<1:0> bits of the CCP1CON value as shown by Equation 11-4.
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period EQUATION 11-4: PWM RESOLUTION
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
log [ 4 ( PR2 + 1 ) ]
register is read-only. Resolution = ------------------------------------------ bits
log ( 2 )
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cycle Note: If the pulse width value is greater than the
ratio. period the assigned PWM pin(s) will
remain unchanged.
CCPR1H (Slave)
P1B P1B
Output TRIS
Comparator R Q
Controller
P1C P1C
TMR2 (1)
S TRIS
P1D P1D
Comparator
Clear Timer2, TRIS
toggle PWM pin and
latch duty cycle
PR2 PWM1CON
Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions
TABLE 11-4: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D
Single 00 Yes(1) Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridge, Forward 01 Yes Yes Yes Yes
Full-Bridge, Reverse 11 Yes Yes Yes Yes
Note 1: Pulse Steering enables outputs in Single mode.
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
Pulse PR2+1
P1M<1:0> Signal 0
Width
Period
P1A Modulated
Delay(1) Delay(1)
10 (Half-Bridge) P1B Modulated
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
FET
Driver +
P1A
-
Load
FET
Driver
+
P1B
-
V+
FET FET
Driver Driver
P1A
Load
FET FET
Driver Driver
P1B
FET QA QC FET
Driver Driver
P1A
Load
P1B
FET FET
Driver Driver
P1C
QB QD
V-
P1D
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Reverse Mode
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as active-high.
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
(2)
P1D (Active-High)
Pulse Width
Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is (1/Fosc) • TMR2 prescale
value.
P1A
P1B
PW
P1C
P1D PW
TON
External Switch C
TOFF
External Switch D
ECCPAS<2:0>
PSSAC<0>
1
P1A_DRV
111 0
110
101 PSSAC<1>
P1A
100 TRISx
INT
011
From Comparator C2 010
PSSBD<0>
1
From Comparator C1 001 P1B_DRV
0
000 PRSEN
PSSBD<1>
R S P1B
TRISx
From Data Bus ECCPASE
D Q
Write to ECCPASE
PSSAC<0>
1
P1C_DRV
0
PSSAC<1>
P1C
TRISx
PSSBD<0>
1
P1D_DRV
0
PSSBD<1>
P1D
TRISx
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
ECCPASE
Cleared by
Start of Shutdown Shutdown Firmware PWM
PWM Period Event Occurs Event Clears Resumes
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
FET
Driver +
P1A V
-
Load
FET
Driver
+
P1B V
-
V-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
PORT Data
0
TRIS
STRB
PORT Data 0
TRIS
STRC
P1C pin
CCP1M1 1
PORT Data 0
TRIS
STRD
PORT Data 0
TRIS
PWM Period
PWM
STRn
P1n = PWM
PWM
STRn
P1n = PWM
TXEN
TRMT SPEN
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0
BRG16 X 1 0 1 0
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH FIFO
X 1 1 0 0 FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for asyn- condition is cleared. See Section 12.1.2.5
chronous operation. Setting the SPEN bit of the RCSTA “Receive Overrun Error” for more
register enables the EUSART and automatically config- information on overrun errors.
ures the RX/DT I/O pin as an input. If the RX/DT pin is
shared with an analog peripheral the analog I/O function 12.1.2.3 Receive Interrupts
must be disabled by clearing the corresponding ANSEL The RCIF interrupt flag bit of the PIR1 register is set
bit. whenever the EUSART receiver is enabled and there is
Note: When the SPEN bit is set the TX/CK I/O an unread character in the receive FIFO. The RCIF
pin is automatically configured as an interrupt flag bit is read-only, it cannot be set or cleared
output, regardless of the state of the by software.
corresponding TRIS bit and whether or not RCIF interrupts are enabled by setting all of the
the EUSART transmitter is enabled. The following bits:
PORT latch is disconnected from the
• RCIE interrupt enable bit of the PIE1 register
output driver so it is not possible to use the
TX/CK pin as a general purpose output. • PEIE peripheral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51
1200 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12
2400 2404 0.16 25 2400 0.00 23 2404 0.16 12 — — —
9600 — — — 9600 0.00 5 — — — — — —
10417 10417 0.00 5 — — — 10417 0.00 2 — — —
19.2k — — — 19.20k 0.00 2 — — — — — —
57.6k — — — 57.60k 0.00 0 — — — — — —
115.2k — — — — — — — — — — — —
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — 2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25
57.6k 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.2k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666
1200 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416
2400 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25
57.6k 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.20k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666
1200 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666
2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832
9600 9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207
10417 10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34
115.2k 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832
1200 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207
2400 2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103
9600 9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25
10417 10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23
19.2k 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12
57.6k 58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 — — —
115.2k 111.1k -3.55 8 115.2k 0.00 7 — — — — — —
BRG Clock
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
SDO
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 1)
SDI
(SMP = 0)
bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7 bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit 0
(SMP = 0)
bit 7 bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0)
bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0)
bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
The SSP module has six registers for the I2C operation, In this case, the SSPSR register value is not loaded
which are listed below. into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 13-3 shows the results of when a data
• SSP Control register (SSPCON) transfer byte is received, given the status of bits BF and
• SSP Status register (SSPSTAT) SSPOV. The shaded cells show the condition where
• Serial Receive/Transmit Buffer (SSPBUF) user software did not properly clear the overflow
• SSP Shift register (SSPSR) – Not directly condition. Flag bit BF is cleared by reading the
accessible SSPBUF register, while bit SSPOV is cleared through
software.
• SSP Address register (SSPADD)
• SSP Mask register (SSPMSK) The SCL clock input must have a minimum high and low
for proper operation. For high and low times of the I2C
specification, as well as the requirements of the SSP
module, see Section 17.0 “Electrical Specifications”.
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed
through the SSPMSK register. The SSPEN bit of the SSPCON register should be zero when accessing
the SSPMSK register.
2: In all other SSP modes, this bit has no effect.
DS41262E-page 192
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address
R/W = 0 Receive Second Byte of Address Receive Data Byte Receive Data Byte
ACK ACK ACK ACK
SDA 1 1 1 1 0 A9 A8 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF transfer
(PIR1<3>)
Cleared in software Cleared in software Cleared in software
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written Dummy read of SSPBUF
with contents of SSPSR to clear BF flag
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
that the SSPADD needs to when SSPADD is updated SSPADD is updated with high
be updated with low byte of address byte of address
UA is set indicating
that SSPADD needs to
be updated
I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>) Cleared in software
BF (SSPSTAT<0>)
From SSP Interrupt
SSPBUF is written in software Service Routine
CKP (SSPCON<4>)
DS41262E-page 194
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address R/W = 0 Receive Second Byte of Address Receive Data Byte Receive Data Byte ACK
ACK ACK ACK
SDA 1 1 1 1 0 A9 A8 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF transfer
(PIR1<3>)
Cleared in software Cleared in software Cleared in software
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written Dummy read of SSPBUF
with contents of SSPSR to clear BF flag
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
that the SSPADD needs to when SSPADD is updated SSPADD is updated with high
be updated with low byte of address byte of address
UA is set indicating
that SSPADD needs to
be updated
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX-1
SCL
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON
0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
10Bh/18Bh
0Ch PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
93h SSPMSK(2) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111
94h SSPSTAT SMP(3) CKE(3) D/A P S R/W UA BF 0000 0000 0000 0000
8Ch PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IF TMR1IF -000 0000 -000 0000
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the SSP module.
Note 1: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
2: SSPMSK register (Register 13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001.
See Registers 13-2 and 13-3 for more details.
3: Maintain these bits clear.
Legend:
R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented
bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
External
Reset
MCLR/VPP pin
Sleep
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
(1)
Brown-out
Reset BOREN
SBOREN S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter R Q
OSC1/
CLKI pin
PWRT
LFINTOSC 11-bit Ripple Counter
Enable PWRT
Enable OST
Internal
Reset 64 ms(1)
VDD
VBOR
Internal < 64 ms
Reset 64 ms(1)
VDD
VBOR
Internal
Reset 64 ms(1)
XT, HS, LP TPWRT + 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC
1024 • TOSC 1024 • TOSC
LP, T1OSCIN = 1 TPWRT — TPWRT — —
RC, EC, INTOSC TPWRT — TPWRT — —
VDD
MCLR
Internal POR
TPWRT
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
TPWRT
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
TPWRT
OST Time-out
Internal Reset
The PIC16F631/677/685/687/689/690 have multiple • The GIE is cleared to disable any further interrupt.
sources of interrupt: • The return address is pushed onto the stack.
• External Interrupt RA2/INT • The PC is loaded with 0004h.
• TMR0 Overflow Interrupt For external interrupt events, such as the INT pin,
• PORTA/PORTB Change Interrupts PORTA/PORTB change interrupts, the interrupt
• 2 Comparator Interrupts latency will be three or four instruction cycles. The
• A/D Interrupt (except PIC16F631) exact latency depends upon when the interrupt event
occurs (see Figure 14-8). The latency is the same for
• Timer1 Overflow Interrupt
one or two-cycle instructions. Once in the Interrupt
• Timer2 Match Interrupt (PIC16F685/PIC16F690
Service Routine, the source(s) of the interrupt can be
only)
determined by polling the interrupt flag bits. The
• EEPROM Data Write Interrupt interrupt flag bit(s) must be cleared in software before
• Fail-Safe Clock Monitor Interrupt re-enabling interrupts to avoid multiple interrupt
• Enhanced CCP Interrupt (PIC16F685/PIC16F690 requests.
only)
• EUSART Receive and Transmit interrupts Note 1: Individual interrupt flag bits are set,
(PIC16F687/PIC16F689/PIC16F690 only) regardless of the status of their
corresponding mask bit or the GIE bit.
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual 2: When an instruction that clears the GIE
interrupt requests in flag bits. The INTCON register bit is executed, any interrupts that were
also has individual and global interrupt enable bits. pending for execution in the next cycle
are ignored. The interrupts, which were
A Global Interrupt Enable bit, GIE (INTCON<7>), ignored, are still pending to be serviced
enables (if set) all unmasked interrupts, or disables (if when the GIE bit is set again.
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the For additional information on Timer1, Timer2,
INTCON, PIE1 and PIE2 registers, respectively. GIE is comparators, A/D, data EEPROM, EUSART, SSP or
cleared on Reset. Enhanced CCP modules, refer to the respective
peripheral section.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which 14.3.1 RA2/INT INTERRUPT
re-enables unmasked interrupts.
External interrupt on RA2/INT pin is edge-triggered;
The following interrupt flags are contained in the either rising if the INTEDG bit (OPTION_REG<6>) is
INTCON register: set, or falling, if the INTEDG bit is clear. When a valid
• INT Pin Interrupt edge appears on the RA2/INT pin, the INTF bit
• PORTA/PORTB Change Interrupts (INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
• TMR0 Overflow Interrupt
bit must be cleared in software in the Interrupt Service
The peripheral interrupt flags are contained in the PIR1 Routine before re-enabling this interrupt. The RA2/INT
and PIR2 registers. The corresponding interrupt enable interrupt can wake-up the processor from Sleep, if the
bits are contained in PIE1 and PIE2 registers. INTE bit was set prior to going into Sleep. The status of
The following interrupt flags are contained in the PIR1 the GIE bit decides whether or not the processor
register: branches to the interrupt vector following wake-up
(0004h). See Section 14.6 “Power-Down Mode
• A/D Interrupt
(Sleep)” for details on Sleep and Figure 14-10 for
• EUSART Receive and Transmit Interrupts timing of wake-up from Sleep through RA2/INT
• Timer1 Overflow Interrupt interrupt.
• Synchronous Serial Port (SSP) Interrupt
Note: The ANSEL and CM2CON0 registers
• Enhanced CCP1 Interrupt must be initialized to configure an analog
• Timer1 Overflow Interrupt channel as a digital input. Pins configured
• Timer2 Match Interrupt as analog inputs will read ‘0’.
The following interrupt flags are contained in the PIR2
register:
• Fail-Safe Clock Monitor Interrupt
• 2 Comparator Interrupts
• EEPROM Data Write Interrupt
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3 SSPIF
SSPIE
IOC-RA4
IOCA4 TXIF
TXIE
IOC-RA5
IOCA5
RCIF
RCIE Wake-up (If in Sleep mode)(1)
IOC-RB4 T0IF
IOCB4 TMR2IF T0IE
Interrupt to CPU
TMR2IE INTF
IOC-RB5
IOCB5 INTE
TMR1IF RABIF
TMR1IE
IOC-RB6 RABIE
IOCB6
C1IF
C1IE PEIE
IOC-RB7
IOCB7
C2IF GIE
C2IE
ADIF
ADIE
EEIF
EEIE
Note 1: Some peripherals depend upon the system
OSFIF clock for operation. Since the system clock is
OSFIE suspended during Sleep, these peripherals
will not wake the part from Sleep. See
CCP1IF Section 14.6.1 “Wake-up from Sleep”.
CCP1IE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag (5) Interrupt Latency (2)
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Prescaler(1)
1
16-bit WDT Prescaler
PSA
PS<2:0>
31 kHz
WDTPS<3:0> To TMR0
LFINTOSC Clock
0 1
PSA
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE
Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency (3)
GIE bit
(INTCON<7>) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle
Executed Inst(PC – 1) Inst(0004h)
To Normal
Connections
External
Connector * PIC16F631/677/
Signals 685/687/689/690
+5V VDD
0V VSS
VPP RA3/MCLR/VPP
CLK RA1
* * *
To Normal
Connections
Before Instruction
W = 0x07
After Instruction
W = value of k8
C=0 W>f
C=1 W≤f
DC = 0 W<3:0> > f<3:0>
DC = 1 W<3:0> ≤ f<3:0>
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOL x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
5.5
5.0
4.5
VDD (V)
4.0
3.5
3.0
2.5
2.0
0 8 10 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
± 5%
85
Temperature (°C)
± 2%
60
25 ± 1%
VDD (V)
Param Conditions
Device Characteristics Min. Typ† Max. Units
No. VDD Note
(1, 2)
D010 Supply Current (IDD) — 13 19 μA 2.0 FOSC = 32 kHz
— 22 30 μA 3.0 LP Oscillator mode
— 33 60 μA 5.0
D011* — 140 240 μA 2.0 FOSC = 1 MHz
— 220 380 μA 3.0 XT Oscillator mode
— 31 65 μA 5.0
D016* — 340 450 μA 2.0 FOSC = 4 MHz
— 500 700 μA 3.0 HFINTOSC mode
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in kΩ.
4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
Param Conditions
Device Characteristics Min. Typ† Max. Units
No. VDD Note
D020 Power-down Base — 0.05 1.2 μA 2.0 WDT, BOR, Comparators, VREF and
Current(IPD)(2) — 0.15 1.5 μA 3.0 T1OSC disabled
Param Conditions
Device Characteristics Min. Typ† Max. Units
No. VDD Note
D020E Power-down Base — 0.05 9 μA 2.0 WDT, BOR, Comparators, VREF and
Current(IPD)(2) — 0.15 11 μA 3.0 T1OSC disabled
— 0.35 15 μA 5.0
— 90 500 nA 3.0 -40°C ≤ TA ≤ +25°C
D021E — 1.0 17.5 μA 2.0 WDT Current(1)
— 2.0 19 μA 3.0
— 3.0 22 μA 5.0
D022E — 42 65 μA 3.0 BOR Current(1)
— 85 127 μA 5.0
D023E — 32 45 μA 2.0 Comparator Current(1), both
— 60 78 μA 3.0 comparators enabled
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O Port:
D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D030A Vss — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V
D031 with Schmitt Trigger buffer Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V
D032 MCLR, OSC1 (RC mode)(1) VSS — 0.2 VDD V
D033 OSC1 (XT and LP modes) VSS — 0.3 V
D033A OSC1 (HS mode) VSS — 0.3 VDD V
VIH Input High Voltage
I/O Ports: —
D040 with TTL buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V
D040A 0.25 VDD + 0.8 — VDD V 2.0V ≤ VDD ≤ 4.5V
D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V ≤ VDD ≤ 5.5V
D042 MCLR 0.8 VDD — VDD V
D043 OSC1 (XT and LP modes) 1.6 — VDD V
D043A OSC1 (HS mode) 0.7 VDD — VDD V
D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1)
IIL Input Leakage Current(2)
D060 I/O ports — ± 0.1 ±1 μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061 MCLR(3) — ± 0.1 ±5 μA VSS ≤ VPIN ≤ VDD
D063 OSC1 — ± 0.1 ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS and
LP oscillator configuration
D070* IPUR PORTA Weak Pull-up Current 50 250 400 μA VDD = 5.0V, VPIN = VSS
(5)
VOL Output Low Voltage
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)
VOH Output High Voltage(5)
D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 10.2.1 “Using the Data EEPROM” for additional information.
5: Including OSC2 in CLKOUT mode.
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
D100 IULP Ultra Low-Power Wake-up — 200 — nA See Application Note AN879,
Current “Using the Microchip Ultra
Low-Power Wake-up Module”
(DS00879)
Capacitive Loading Specs on
Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
Data EEPROM Memory
D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C
D120A ED Byte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time — 5 6 ms
D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C ≤ TA ≤ +85°C
Cycles before Refresh(4)
Program Flash Memory
D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C
D130A ED Cell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C
D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VPEW VDD for Erase/Write 4.5 — 5.5 V
D133 TPEW Erase/Write cycle time — 2 2.5 ms
D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 10.2.1 “Using the Data EEPROM” for additional information.
5: Including OSC2 in CLKOUT mode.
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O Port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Load Condition
Pin CL
VSS
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode
DC — 4 MHz XT Oscillator mode
DC — 20 MHz HS Oscillator mode
DC — 20 MHz EC Oscillator mode
(1)
Oscillator Frequency — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 20 MHz HS Oscillator mode
DC — 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 — ∞ μs LP Oscillator mode
250 — ∞ ns XT Oscillator mode
50 — ∞ ns HS Oscillator mode
50 — ∞ ns EC Oscillator mode
Oscillator Period(1) — 30.5 — μs LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TOSH, External CLKIN High, 2 — — μs LP oscillator
TOSL External CLKIN Low 100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TOSR, External CLKIN Rise, 0 — ∞ ns LP oscillator
TOSF External CLKIN Fall 0 — ∞ ns XT oscillator
0 — ∞ ns HS oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an
external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
VDD
VBOR + VHYST
VBOR
37
Reset
(due to BOR) 33*
* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
CCP1
(Capture mode)
CC01 CC02
CC03
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VOS Input Offset Voltage — ± 5.0 ± 10 mV
CM02 VCM Input Common Mode Voltage 0 — VDD - 1.5 V
CM03* CMRR Common Mode Rejection Ratio +55 — — db
CM04* TRT Response Time Falling — 150 600 ns (Note 1)
Rising — 200 1000 ns
CM05* TMC2COV Comparator Mode Change to Output — — 10 μs
Valid
* These parameters are characterized but not tested.
Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
Param
Symbol Characteristics Min. Typ. Max. Units Comments
No.
VR01 VROUT VR voltage output 0.5 0.6 0.7 V
VR02* TSTABLE Settling Time — 10 100* μs
* These parameters are characterized but not tested.
RB7/TX/CK
pin 121 121
RB5/AN11/RX/DT
pin
120
122
Note: Refer to Figure 17-3 for load conditions.
RB7/TX/CK
pin 125
RB5/AN11/RX/DT
pin
126
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
82
SS
70
SCK 83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb In bit 6 - - - -1 LSb In
74
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — Start condition
91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
SDA
Out
BSF ADCON0, GO
1 TCY
134 (TOSC/2)(1)
131
Q4
130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample 132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
130* TAD A/D Clock Period 1.5 — — μs TOSC-based, VREF ≥ 2.5V
3.0* — — μs TOSC-based, VREF full range
A/D Internal RC ADCS<1:0> = 11 (RC mode)
Oscillator Period 3.0* 6.0 9.0* μs At VDD = 2.5V
2.0* 4.0 6.0* μs At VDD = 5.0V
131 TCNV Conversion Time — 11 — TAD Set GO bit to new data in A/D Result
(not including register
Acquisition Time)(1)
132* TACQ Acquisition Time (2) 11.5 — μs
BSF ADCON0, GO
134 (TOSC/2 + TCY)(1) 1 TCY
131
Q4
130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample 132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.
FIGURE 18-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
3.5
2.0 4.0V
IDD (mA)
1.5
3.0V
1.0
2.0V
0.5
0.0
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC
4.0
Typical: Statistical Mean @25°C
5.5V
3.5 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.0V
3.0
2.5
4.0V
IDD (mA)
2.0
3.0V
1.5
2.0V
1.0
0.5
0.0
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC
FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
Typical IDD vs FOSC Over Vdd
HS Mode
4.0
Typical: Statistical Mean @25°C
3.5 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.5V
3.0
5.0V
2.5
4.5V
IDD (mA)
2.0
1.5
4.0V
1.0 3.5V
3.0V
0.5
0.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC
3.5 5.5V
5.0V
3.0
IDD (mA)
4.5V
2.5
2.0
1.5
4.0V
3.5V
1.0 3.0V
0.5
0.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC
FIGURE 18-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
XT Mode
900
Typical: Statistical Mean @25°C
800 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
700
600
500
IDD (μA)
4 MHz
400
300
1 MHz
200
100
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
1,400
1,000
800
IDD (μA)
4 MHz
600
400
1 MHz
200
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
80
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
70
(-40°C to 125°C)
60
50
IDD (uA)
32 kHz Maximum
40
30 32 kHz Typical
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
800
Typical: Statistical Mean @25°C
700 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
600
500
4 MHz
IDD (μA)
400
300
1 MHz
200
100
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-9: MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE)
EXTRC Mode
1,400
1,000
4 MHz
800
IDD (μA)
600
400 1 MHz
200
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
80
Typical: Statistical Mean @25°C
70 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
60
50
Maximum
IDD (μA)
40
30
Typical
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)
HFINTOSC
1,600
1,000 4.0V
IDD (μA)
800
3.0V
600
2.0V
400
200
0
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
FOSC
2,000
Typical: Statistical Mean @25°C
5.5V
1,800 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
1,600 5.0V
1,400
1,200 4.0V
IDD (μA)
1,000
3.0V
800
600
2.0V
400
200
0
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
FOSC
FIGURE 18-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical
(Sleep Mode all Peripherals Disabled)
0.45
0.30
0.25
IPD (μA)
0.20
0.15
0.10
0.05
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
10.0
IPD (μA)
8.0
6.0
4.0
Max. 85°C
2.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
180
120
Maximum
100
IPD (μA)
Typical
80
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
160
120
100
Maximum
IPD (μA)
80
Typical
60
40
20
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
3.0
Typical: Statistical
Typical: StatisticalMean
Mean @25°C
@25°C
2.5 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
2.0
IPD (μA)
1.5
1.0
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
25.0
20.0
Max. 125°C
Max. 85°C
5.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
30
Typical: Statistical Mean @25°C
28 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Max. (125°C)
26
Max. (85°C)
24
22
Time (ms)
20
Typical
18
16
14
Minimum
12
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
30
Typical: Statistical Mean @25°C
28 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
26
Maximum
24
22
Time (ms)
20
Typical
18
16
Minimum
14
12
10
-40°C 25°C 85°C 125°C
Temperature (°C)
FIGURE 18-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
High Range
140
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
120
(-40°C to 125°C)
100
Max. 125°C
80
IPD (μA)
Max. 85°C
60
Typical
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
180
Typical: Statistical Mean @25°C
160 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
140
120
Max. 125°C
100
IPD (μA)
Max. 85°C
80
Typical
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
160
140
120
100
Typical
IPD (uA)
80
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
180
160
140
Max 125°C
120
Max 85°C
IPD (uA)
100
80
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-25: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
30
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
25 (-40°C to 125°C)
Max. 125°C
20
IPD (uA)
15
Typ 25×C Max 85×C Max 125×C
2 2.022 4.98 17.54
2.5 2.247 5.23 19.02
10 3 2.472 5.49 20.29
3.5 2.453 5.79 21.50
Max. 85°C
4 2.433 6.08 22.45
4.5 2.711 6.54 23.30
5 5 2.989 7.00 24.00
5.5 3.112 7.34 Typ. 25°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
0.8
0.4
0.2
Min. -40°C
0.1
0.0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
0.45
0.25
VOL (V)
Typ. 25°C
0.20
0.10
0.05
0.00
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
3.5
3.0
Max. -40°C
Typ. 25°C
2.5
Min. 125°C
2.0
VOH (V)
1.5
0.5
0.0
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0
IOH (mA)
5.5
5.0
Max. -40°C
Typ. 25°C
4.5
VOH (V)
Min. 125°C
4.0
3.0
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0
IOH (mA)
1.7
Max. -40°C
1.3
Typ. 25°C
VIN (V)
1.1
Min. 125°C
0.9
0.7
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-31: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(ST Input, -40×C TO 125×C)
4.0
VIH Max. 125°C
Typical: Statistical Mean @25°C
3.5 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
VIH Min. -40°C
3.0
2.5
VIN (V)
2.0
VIL Max. -40°C
1.0
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
1000
900
700
Response Time (nS)
400
300
0
2.0 2.5 4.0 5.5
VDD (V)
1000
900
700
Response Time (nS)
400
300
0
2.0 2.5 4.0 5.5
VDD (V)
45,000
40,000
Max. -40°C
35,000
Typ. 25°C
30,000
Frequency (Hz)
25,000
Min. 125°C
15,000
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
6
85°C
Time (μs)
25°C
4
-40°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
16
12
25°C
10
-40°C
Time (μs)
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-37: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
25
15
Time (μs)
85°C
25°C
10
-40°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
10
9
Typical: Statistical Mean @25°C
8 Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
7
85°C
6
Time (μs)
25°C
5
-40°C
4
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
2
Change from Calibration (%)
-1
-2
-3
-4
-5
VDD (V)
3
Change from Calibration (%)
-1
-2
-3
-4
-5
VDD (V)
2
Change from Calibration (%)
-1
-2
-3
-4
-5
VDD (V)
3
Change from Calibration (%)
-1
-2
-3
-4
-5
VDD (V)
0.65
0.64
0.63
0.62
0.61
VP6 (V)
0.60
0.59
Typical
0.58
0.57
0.56
0.55
2 3 4 5 5.5
VDD (V)
0.66
0.64
Max.
0.62
0.6
VP6 (V)
Typical
0.58
0.56 Min.
0.54
0.52
-40°C 25°C 85°C 125°C
Temperature (°C)
0.66
0.64
0.62 Max.
0.6
VP6 (V)
0.58 Typical
0.56
Min.
0.54
0.52
-40 °C 25 °C 85 °C 125 °C
Temperature (°C)
35
30 Parts=118
25
Number of Parts
20
15
10
0
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
40
35
Parts=118
30
Number of Parts
25
20
15
10
0
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
40
35 Parts=118
30
Number of Parts
25
20
15
10
0
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
30
Parts=118
25
Number of Parts
20
15
10
0
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
30
25 Parts=118
Number of Parts
20
15
10
0
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
35
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25
Number of Parts
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15
10
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0.500
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Number of Parts
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Voltage (V)
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Revised Section 4.2.1, ANSEL and ANSELH Max Program 1024 4096
Registers; Register 4-3, ANSEL Analog Select; Added Memory (Words)
Register 4-4, ANSELH Analog Select High; Section SRAM (bytes) 64 128
11.3.2, Revised CCP1<1:0> to DC1B<1:0>; Section A/D Resolution 10-bit 10-bit
11.3.7, Number 4 - Revised CCP1 to DC1B; Figure 11-
Data EEPROM 128 256
5, Revised CCP1 to DC1B; Table 11-4, Revised P1M to
(Bytes)
P1M<1:0>; Section 12.3.1, Revised Paragraph 3;
Revised Note 2; Revised Figure 12-6 Title. Timers (8/16-bit) 1/1 2/1
Oscillator Modes 8 8
Revision D (February 2007) Brown-out Reset Y Y
Removed Preliminary status; Changed PICmicro to Internal Pull-ups RA0/1/2/4/5 RA0/1/2/4/5,
PIC; Replaced Dev. Tool Section; Replaced Package MCLR
Drawings. Interrupt-on-change RA0/1/2/3/4/5 RA0/1/2/3/4/5
Comparator 1 2
Revision E (March 2008) ECCP+ N Y
Add Char Data charts; Updated EUSART Golden Ultra Low-Power N Y
Chapter; Updated the Electrical Specification section; Wake-up
Updated Package Drawings as needed. Extended WDT N Y
Software Control N Y
Option of WDT/BOR
INTOSC 4 MHz 31 kHz-8 MHz
Frequencies
Clock Switching N Y
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01/02/08