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Asic Implementation of Digital Pulse Shaping Fir Filter
Asic Implementation of Digital Pulse Shaping Fir Filter
By,
C.Radhika (09VL03F)
N.M.Yeshoda (09VL28F)
Prajakta Panse (09VLF01)
1
Acknowledgment
We would like to take this opportunity to express our deep sense of gratitude
to Mr.Ramesh Kini M.(Associate Professor, E & C, N.I.T.K, Surathkal), our
guide for his help through provoking discussion, invigorating suggestions ex-
tended to us with immense care, zeal to our work.
We offer our sincere thanks to Dr. Sumam David S.(Head of the Depart-
ment, E & C, N.I.T.K, Surathkal) for providing necessary facilities, valuable
suggestions and support through our study.
2
Abstract
1 Introduction 3
2 ASIC Implementation 6
2.1 Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Back End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Results 13
1
List of Figures
3.1 Output of FIR filter for rectangular pulse of width= 2 clk cycle 13
3.2 Output of FIR in testing mode for boundary scanning . . . . . 14
3.3 Output of FIR in testing mode detecting B-S-A-0 . . . . . . . 14
3.4 Layout of Control Logic . . . . . . . . . . . . . . . . . . . . . 15
3.5 Layout of FIR logic . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Layout of Top module of FIR filter . . . . . . . . . . . . . . . 16
3.7 Comparison of ideal and practical FIR filter’s frequency do-
main behavioral . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
Chapter 1
Introduction
X
N −1
y[n] = h[k] ∗ x[n − k] (1.1)
k=0
3
y[n] : current output discrete sample
The impulse response of pulse shaping filters is short enough that very
little energy from one symbol smears into the next symbol.Thereby it does
not cause ISI. Figure 1.1 shows pulse shaping filter’s zero ISI property.
• Raised-cosine filter
• Gaussian filter
4
Where
α: roll-off factor
The roll off rate and chip duration decide the performance metric of
the FIR filter. With the typical α=0.22 and Tc=0.2674 microseconds filter
coefficients are even symmetric.
Pulse shaping filter is basically a FIR filter. Hardware realization of it can
be represented as basic Multiplier and Accumulator (MAC) unit as shown in
the Figure 1.2
.
As the order of the filter increases, the accuracy with which it smoothens
the wave contour becomes superior. But at the same time number of multi-
pliers and adders required increases linearly. Specially higher the number of
multipliers higher is the chip area and thus higher number of multipliers is a
threat to the popularity of pulse shaping filter.
In this project, implementation of the pulse shaping FIR filter is done
with an aim to reduce the chip area by limiting number of multipliers. In
order to make filter design fault tolerent BIST is incorporated in the chip.
BIST is a Design-for-Testability (DFT) technique, because it makes the elec-
trical testing of a chip easier, faster, more efficient,less costly and reduces
dependence on an external automated test equipment (ATE).In the project,
parallel testing of scan design and combinational design is done to reduce
number of clock cycles required for testing. The functionality of the system
is verified using XILINX and the backend design of the system is done using
CADENCE.
5
Chapter 2
ASIC Implementation
6
where floor planning, place and route were carried out. The system design
is done in two stages namely front end and back end.
7
• Fir Logic
• Boundary Scanner
The architecture is shown in the figure 2.2. Cont logic performs the func-
tion of routing appropriate data sequence to fir logic. In addition to that
it has all components of BIST like test vector gen, test mode gen, reset gen
etc. The fir logic block contains main 16-tap FIR filter, adder and latch to
get final convolution sum. Boundary scanner unit is included as an add-on,
to test input and output pins.
The figure 2.3 shows components of cont logic. In cont logic, system clock
is divided using T-Flip-flop. This signal is used to control the data given to 16
bit FIR filter. AND-OR combinational logic is used as multiplexer to route
appropriate (Xout /Data) signal to dout pin. Output of the T-Flip-flop is
also given to the pin n.
Built in self unit (BIST) is integrated within cont logic to endow with
testability measures. Design is optimized to trim down area and time over-
head. Testing of combinational and sequential design is done separately and
simultaneously. Test mode can be enabled by setting Test/normal pin of
the input to high. Fault collapsing and fault dominance has been exploited
to find out minimum number of test vectors for approximately 95% fault
coverage.
8
Figure 2.3: Block diagram of control logic
This necessitates the use of 6 clock cycles for testing entire circuit. In
the test mode, address generator unit is activated to generate address for
extracting test vectors. Test vectors along with expected output are saved in
ROM. In each clock cycle one vector is retrieved and applied to combinational
logic and second test vector is given out as dout signal for testing sequential
logic. Output is compared with expected result using XOR gate. Output of
XOR gate is used as feedback to address generator. Thus as soon as fault is
detected test enable signal goes low disabling address generator. This puts
into practice an idea of fault dropping and reduced power consumption. At
the end of the test mode, whatever data stored in sequential circuit need
to be flushed out. Thus reset gen unit is used to generate monoshot when
test mode pin makes high to low transition. This signal is inturn given out
9
Table 2.2: Fault equivalence and summery of test vectors
0101 a-sa1,c-sa1,e-sa1,fsa1,g-sa1 0 1
0011 c-sa0,d-sa0,f-sa0,g-sa0 1 0
1110 a-sa0,b-sa0,e-sa0 1 0
1010 b-sa1,d-sa1 0 1
10
data input pins and input pins are directly connected to output pins to
verify I/O functionality.
• Area
• Power
• Delay
***********************************************************
Report: area
Design: fir 32 ru
***********************************************************
Number of ports: 24
Number of nets: 189
Number of cells: 32
Number of references: 29
Combinational area: 509625.406250
Noncombinational area: 75118.203125
Total cell area: 584710.18750
This report gives the rough estimate of area (excluding routing area) re-
quired to do the back end design. Similarly the power analysis report gives
the amount of power dissipated, from which an estimate of driving current
can be obtained to decide the power ring metal width in the back end design.
11
*********************************************************
Report: power-analysis effort medium
Design: fir 32 ru
*********************************************************
Operating Conditions: nom pvt
Library: vtvt tsmc180
The post synthesized net list from Synopsys is used for back end layout
design. The tool used for placement and routing is SOC ENCOUNTER.
In layout design modular approach of coding is enforced to the fullest by
doing separate layout design for cont logic and fir logic. These designs have
been saved as .lefs and imported to top module. Table 2.3 gives summery of
backend performance metric got from SYNOPSYS AND CADENCE SOC.
12
Chapter 3
Results
The functionality of the 32 tap fir filter is verified using XILINX ISE Simu-
lator.The design is tested for different data vectors namely
• Delta input
• Step input
• Rectangular pulse
Figure 3.1: Output of FIR filter for rectangular pulse of width= 2 clk cycle
• Boundary Scan
13
• Single stuck at faults and Scan chain in shift registers mode
Figure 3.2 shows result for boundary scanning. In this mode of testing,
whatever data fed at the input reflects at the output. In second phase of
testing, design is tested for single stuck at fault. Figure 3.3 shows result of
B-S-A-0.
14
Figure 3.4: Layout of Control Logic
In the design of top module along with technology lef file, lef for these
two base modules are also imported.After importing lef files carefully place-
ment of the two blocks is done for optimum utilization of area. Layout top
module obtained is shown in the figure 3.6
15
Figure 3.6: Layout of Top module of FIR filter
Figure 3.7: Comparison of ideal and practical FIR filter’s frequency domain
behavioral
16
Conclusion
The concept of even symmetric pulse shaping FIR filter was substantiated
through the project. It is an attempt to optimize the design for area by
minimizing the number of multipliers. On-chip testability is adjoined for
good fault coverage while keeping area and delay overhead optimum. The
precision of the filter is retained to an acceptable level.
17
Appendix
The filter coefficients after truncating the decimal part of the coefficients
obtained from MATLAB are
The above 16 coefficients are symmetric w.r.t the zeroth sampling in-
stance.
18
Bibliography
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