Intel x86 Processors

Presented by
Kiyeon Lee
 Outline
• History
• Register Set
• Data Addressing Mode
• Real Mode & Protected Mode Memory Address
• Integer & Floating Point Operations
• Architecture (P5, P6, NetBurst)
 History
Intel 4004 (1971)
♠ 4 bit microprocessor, 4KB of memory
♠ 45 instructions, 50 KIPS(Kilo-instructions per second)
♠ Main problems: speed, word width, memory size

4040 (1974)
♠ Successor to the Intel 4004, higher speed

8008 (1972)
♠ Extended 8-bit version of the 4004 microprocessor
♠ 16KB of memory
 History
8080 (1974)
♠ The first of the modern 8-bit microprocessors

8008 8080
Not directly compatible Compatible with TTL
with TTL
16KB of memory 64KB of memory

8085 (1977)
♠ Update version of the 8080
♠ 246 instructions
♠ Internal clock generator, internal system controller, and higher clock frequency
 History
8086 (1978) / 8088 (1979)
♠ 16-bit microprocessor, 2.5 MIPS
♠ 1MB of memory
♠ A small 4- or 6-byte instruction cache or queue
♠ Over 20,000 variations of instructions
( 45 (4004) → 245 (8085) → +20,000 (8086) )
♠ The popularity of the Intel family ensured in 1981 by IBM

80286 (1982)
♠ 16-bit microprocessor
♠ 16MB memory system
♠ The first Intel processor that could run all the software written for its predecessor
 History
80386 (1985)
♠ 275,000 transistors
♠ Intel’s first practical 32-bit microprocessor
♠ 32-bit data bus and memory address
♠ 4GB of memory
♠ Memory management unit
♠ Multitasking

80486 (1989)
♠ 80386-like Microprocessor + 80387-like Numeric Coporcessor + 8KB Cache Memory
System
♠ Speed improved
 History
Pentium Processor (1993)
♠ P5 architecture / 80586
♠ Introductory version: 60MHz and 66MHz, 110MIPS / 100MHz, 150MIPS
♠ 16KB of cache size (8KB IC, 8KB DC)
♠ 4GB of memory system, 64-bit data bus
♠ Executes up to two instructions at a time (If they don’t conflict!)

Pentium Pro Processor (1995)

♠ P6 architecture
♠ 5.5M Transistors, 3 integer units, floating-point unit
♠ Basic clock frequency: 150 MHz and 166MHz
♠ 16K L1 Cache(8K for data and 8K for instructions) + 256K L2 Cache
♠ Execute up to three instructions at a time (It doesn’t matter even if the conflict!)
 History
Pentium II Processor (1997)
♠ P6 architecture
♠ 7.5M Transistors, Initially ran at 233MHz and 266MHz
♠ 32KB L1 Cache + 512KB L2 Cache (External → 50% of processor speed)
♠ Arranging the amount of L2 Cache → Celeron(1999) or Xeon(1998)

Pentium III Processor (1999)

♠ P6 architecture
♠ 9.5 Million transistors, 450 and 500 MHz
♠ SSE(Streaming SIMD Extensions) instructions, Improved L1 cache controller
♠ Low-end Celeron / High-end Xeon
 History
Pentium 4 Processor (2000)
♠ NetBurst architecture
♠ Deep instruction pipeline, SSE2, 64-Bit floating point computation
♠ 42 Million transistors, 1.4 GHz and 1.5 GHz
♠ Hyper Threading

Pentium M Processor, 2003

♠ M for Mobile: Laptop
♠ Execution core of the Pentium III + Pentium 4 compatible bus interface + improved
instruction decoding/issuing front end + improved branch prediction + SSE2 support
+ a much larger cache
♠ Low average power consumption, Lower heat output than desktop

Itanium Processor, 2001

♠ 64-bit microprocessor( by HP & Intel )
Register Set
 Data Addressing Modes
8086 through 80286
♠ Register addressing: MOV CX, DX
♠ Immediate addressing: MOV AL, 22H
♠ Direct addressing: MOV CX, LIST
♠ Register indirect addressing: MOV AX, [BX]
♠ Base-plus-index addressing: MOV [BX+DI],
CL
♠ Register relative addressing: MOV AX,
[BX+4]
♠ Base relative-plus-index addressing:
MOV AX, ARRAY[BX+DI]
80386 and above
♠ Register addressing: MOV ECX, EDX
♠ Immediate addressing: MOV EBX, 12345678H
♠ Direct addressing: MOV CX, LIST
♠ Register indirect addressing: MOV AL, [ECX]
♠ Base-plus-index addressing: MOV [EAX+EBX],
CL
♠ Register relative addressing: MOV AX, [ECX+4]
♠ Base relative-plus-index addressing:
MOV EAX, ARRAY[EBX+ECX]
♠ Scaled-index addressing: MOV EDX,
[EAX+4*EBX]
 Real Mode Memory Addressing
8086, 8088 can only operate in the real mode
Real mode operation
Allows the microprocessor to address only the first 1MB of memory

Real memory: The first 1MB of memory

Segment address + Offset address
Segmant address
The beginning address of any 64KB memory segment

Offset address
Selects any location within the 64KB memory segment
 Real Mode Memory Addressing

Ex) Segment register: 1000H, Offset address: 2000H, Physical address?

10000H(Appended with a 0H on its rightmost end) + 2000H = 12000H
 Protected Mode Addressing
80286 and above operate in either the real or protected mode

Allows the access to data and programs located above the first
1MB of memory

Selector → Descriptor

Descriptor decides the memory segment’s location, length, and

access rights.
Protected Mode Addressing
Integer & Floating Point Operations

Integer Operations
Data movement: Move, Push, and Pop
Arithmetic and logic: Logical Operations, Test, Shifts, and Integer & Decimal
Arithmetic Operations
Control flow: Conditional Branches & Unconditional Jump, Calls and Returns
String: String Move, String Compare

Floating Point Operations

Data movement: Load, Load Constant, and Store
Arithmetic: Add, Subtract, Multiply, Divide, Square Root, and Absolute Value
Comparison: Instructions to send the result to the integer CPU so that it can branch
Transcendental: Sine, Cosine, Log, and Exponentation
 Pipelining
The P5 microarchitecture
♠ ILP,5-Stage Pipeline
♠ Two General–Purpose Integer Pipelines & A Pipelined Floating-Point Unit
♠ Main Pipe(U): Pre-Fetch(PF), Decode Stage 1(D1), Decode Stage 2(D2), Execute(E),
Write Back(WB)
Secondary Pipe(V)
♠ Issued up to two instructions every cycle

The P6 microarchitecture(Pentium Pro ~ III)

♠ Out-of-order Execution, 10-stage pipeline
♠ Scheduler, Reorder Buffer
♠ Improved branch prediction algorithms

The NetBurst microarchitecture(Pentium 4, Xeon)

♠ Smaller, Faster, More Robust, 20-Stage Pipeline,
♠ Faster ALU, FPU, Improved Branch Prediction Algorithms
 P5 Architecture

• Superscalar Execution
• Pipeline Architecture
• Branch Target Buffer (BTB)
• Dual 8KB On-Chip Cache
• Write-Back Cache
• 64-Bit Bus
• Instruction Optimization
• Floating-Point Optimization
P6 Architecture (Pentium Pro)

Three-way Superscalar, pipelined architecture

P6 Architecture (Pentium Pro)
NetBurst Architecture
 Thanks!!
• Questions ???