CMOS process Integrat ion

!otroguct Ion to CMOS tethno!QCJY

The power dissipation crisis of VLSI and how CMOS came to the rlssue

tf'1)S (mid 1970's): fast, dense and cheap (S1masks) -> dc steady current -) power drssioanon t wah of packing density -) ceramtc (not plastic) packages

CMOS (1963) is a Da1INANT IC TECHNOLOGY: gives lower power consumption in chips and in systems (I-Mbit t-l1OS DRAMs ~ 120 mW (-) • 50 mW tn

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-De,vice Ichip performance

-Smatter gates ( 1/2 N'1OS 1nverter), in sene of 1s01at10n, due to Pt1)S:

2x wider ) ~S (E) but rf'1:)S (D) 4x larger) N'1OS (E)~ large packing density -) 'Ist,r systems (closer to bipolars)

-10 in 1dentical1y sized submicron devices PM:)S and N"K)S are the same dUt to velOCIty saturatIon

.Interconnection area -t -) transistor area is less important as is the input ceeacttance (Ct"K)S ) t-t1OS) -) N'1OS not faster anymore (power dissipation -) T t -) ~ degradation)

-0105 can operate over a wider range of VOO than tf10S

-Less bOdy-biasing senstttvtty (no bootstrapping for transferance of a

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b) Average POWI!: Dinipttion (mW)

Fla. 6·' (I) Ratio of p.channel saruration current to /I·chlNlel saturation current inc:re.ues IS !he effective channel ienath of !he devices shrinks. due to velocity Slturation effects. (b) Comparative speed I1Id power characteristics of various CMOS and bipolar Io,ic families.

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"'Low T (power dissipation) + reHabiHty

"LiSS hot-carrier degradat10n because of: the Pt1)S load, no stanc

current, no bootstrapping (t E -) hot-carrier degradation) ... Less electromigration (no static current)

-Sort error rates (SERs) of DRAMS and SRAMs .v I to 2 order of magnitude due to wells (reversed biased juncttons block carrIers generated in the substrate)

·Cost issues

-wafer fab: 20" higher than in t-I1OS due to more complex process

-25-75 ~ of the total cost Is due to packaging -) CMOS use cheaper

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-no grinding at the back (grounding at the front stde) and no gold coating

Dlsadyantages *Short-channel and hot carrier effects as 1n ~S *Somewhat lower packing density

*larger lnput capacitance in static logic gates (n- and p-channel MOSFETs in

parallel)

*PMJS with n+-poly gates scaling and connecting *We 11 contacts required

·Well process (11' T, t)

*latchup and prevent Ion

*Electrostatic discharge damage

The well controversy in CMOS

The need for wells in O1OS -) po (well/substrate) junctions at V<O: p-type biased wjth (-) voltage and n-type biased with (+) voltage

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AdVantages

*Better choice for pure-stat1c logic (. fJAl,AtvC4 eerase« p- ~ N-Hos)

*Used where p-type region Should be isolated (BJT as an on-chip driver) *EasJer fabricatfon as it is less susceptible tha.n-weIJ to field-Inversion *Easler for retrograde-well process (later)

"IIHlS ('p-well) better for SRAMs due to lower soft-error rate (SER) 'l!~1~ ':.~1~

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