MSP430

X5XX GENRATION
 INTRODUCTION

• The MSP430 family of ultra-low-power 16-bit RISC mixed-

signal processors from Texas Instruments (TI) provides the
ultimate solution for battery-powered measurement
applications. Using leadership in both mixed-signal and
digital technologies, TI has created the MSP430 which
enables system designers to simultaneously interface to
analog signals, sensors and digital components while
maintaining unmatched low power.
• Typical applications include utility metering, portable
instrumentation, intelligent sensing, and consumer
electronics.
 Anatomy of a Microcontroller
• Central processing unit:
• Memory for the program:
• Memory for data:
• Input and output ports:
• Address and data buses:
• Clock:
• Timers:
• Watchdogtimer:
• Communication interfaces
• Nonvolatile memory for data
• Analog-to-digital converter
• Digital-to-analogconverter
• Real-timeclock
• Monitor, backgrounddebugger, and embedded
emulator
 Memory
Volatile :
• RAM(random access memory)
Nonvolatile:
• MaskedROM:
• EPROM(electrically programmable ROM):
• OTP(one-time programmable memory):
• Flash memory:
Harvard and von-Neumann Architectures

MSP430 has a von-neuman architecture

Architecture
 Key Features
• Ultra-low-power architecture extends battery life:
• 0.1-µA RAM retention
• 0.8-µA real-time clock mode
• 250-µA/MIPS active
• Wide range of integrated intelligent peripherals offloads
the CPU
• Modern 16-bit RISC CPU enables new applications at a
fraction of the code size
• Complete development tools starting at only $20
• Devices starting at $0.49
CPU
SPECIAL FUNCTION REGISTERS
 Memory mapping
• PortP1 input,P1IN: Reading returns the logical
values on the inputs if they are configured for
digital input and output.
• Port P1 output, P1OUT: Writing sends the
value to be driven on to the pin if it is
configures as digital output
• Port P1 direction, P1DIR: A bit of 0 will
configure this as input.
 CLOCKS
• Crystal Oscillators, LFXT1 and XT2

• Master clock, MCLK is used by the CPU and a few peripherals.

• Sub system master clock (SMCLK ), is distributed to peripherals.

Both the mclk and smclk are derived from digitally controlled
oscillator

• Auxiliary clock (ACLK), is also distributed to peripherals. ACLK

comes from a low-frequency crystal oscillator, typically at 32KHz.
ACLK requires an external crystal
 OperatingModes

• Active mode(AM) All clock sare active

• Low-power mode 0 (LPM0) CPU is disabled, ACLK and SMCLK remain
active, MCLK is disabled, FLLloop control remains active
• Low-power mode 1 (LPM1) CPU is disabled–FLL loop control is disabled–
ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2(LPM2) CPU is disabled, MCLK and FLL loop control
and DCO CLK are disabled, ACLK remains active
• Low-power mode 3(LPM3) CPU is disabled, MCLK, FLL loop control, and
DCO CLK are disabled, DCO's dc generator is disabled–ACLK remains active
• Low-power mode 4(LPM4) CPU is disabled– ACLK is disabled–MCLK, FLL
loop control, and DCO CLK are disabled, Crystal oscillator is stopped
 C-PROGRAMMING
SOFTWARES
• IAR Embedded Workbench Kickstart:
• Code Composer Essentials Evaluation:

GUIDELINES FOR WRITING CODE

1. No line should exceed 80 characters.
2. Use macros provided in the MSP430 header
3. Comments start in column 45, first word is capitalized
4. For multiline comments, additional lines are NOT
capitalized.
 Resets
• Power-on Reset(POR): hardware related
• Power-up Clear(PUC): software related