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Intel x86 Processors: Presented by Kiyeon Lee
Intel x86 Processors: Presented by Kiyeon Lee
Intel x86 Processors: Presented by Kiyeon Lee
Presented by
Kiyeon Lee
Outline
• History
• Register Set
• Data Addressing Mode
• Real Mode & Protected Mode Memory Address
• Integer & Floating Point Operations
• Architecture (P5, P6, NetBurst)
History
Intel 4004 (1971)
♠ 4 bit microprocessor, 4KB of memory
♠ 45 instructions, 50 KIPS(Kilo-instructions per second)
♠ Main problems: speed, word width, memory size
4040 (1974)
♠ Successor to the Intel 4004, higher speed
8008 (1972)
♠ Extended 8-bit version of the 4004 microprocessor
♠ 16KB of memory
History
8080 (1974)
♠ The first of the modern 8-bit microprocessors
8008 8080
Not directly compatible Compatible with TTL
with TTL
16KB of memory 64KB of memory
8085 (1977)
♠ Update version of the 8080
♠ 246 instructions
♠ Internal clock generator, internal system controller, and higher clock frequency
History
8086 (1978) / 8088 (1979)
♠ 16-bit microprocessor, 2.5 MIPS
♠ 1MB of memory
♠ A small 4- or 6-byte instruction cache or queue
♠ Over 20,000 variations of instructions
( 45 (4004) → 245 (8085) → +20,000 (8086) )
♠ The popularity of the Intel family ensured in 1981 by IBM
80286 (1982)
♠ 16-bit microprocessor
♠ 16MB memory system
♠ The first Intel processor that could run all the software written for its predecessor
History
80386 (1985)
♠ 275,000 transistors
♠ Intel’s first practical 32-bit microprocessor
♠ 32-bit data bus and memory address
♠ 4GB of memory
♠ Memory management unit
♠ Multitasking
80486 (1989)
♠ 80386-like Microprocessor + 80387-like Numeric Coporcessor + 8KB Cache Memory
System
♠ Speed improved
History
Pentium Processor (1993)
♠ P5 architecture / 80586
♠ Introductory version: 60MHz and 66MHz, 110MIPS / 100MHz, 150MIPS
♠ 16KB of cache size (8KB IC, 8KB DC)
♠ 4GB of memory system, 64-bit data bus
♠ Executes up to two instructions at a time (If they don’t conflict!)
Offset address
Selects any location within the 64KB memory segment
Real Mode Memory Addressing
Allows the access to data and programs located above the first
1MB of memory
Selector → Descriptor
Integer Operations
Data movement: Move, Push, and Pop
Arithmetic and logic: Logical Operations, Test, Shifts, and Integer & Decimal
Arithmetic Operations
Control flow: Conditional Branches & Unconditional Jump, Calls and Returns
String: String Move, String Compare
• Superscalar Execution
• Pipeline Architecture
• Branch Target Buffer (BTB)
• Dual 8KB On-Chip Cache
• Write-Back Cache
• 64-Bit Bus
• Instruction Optimization
• Floating-Point Optimization
P6 Architecture (Pentium Pro)