Embedded Systems: Campus Training On

12/07/21 09:06 PM
Campus Training
on
EMBEDDED SYSTEMS
(08th June - 10th June 2009)
The 8051 Microcontroller Architecture & Interfacing
By
Siva Prasad M
Application Engineer, VLSI & Embedded group
Unistring Tech Solutions Pvt. Ltd, 5th Floor, Ureka

complex, Beside Image hospital, Ameerpet, Hyderabad
Campus training www.unistring.com

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Embedded Systems Overview

• Internal Architecture of 8051 Microcontroller
• ALP & Addressing Modes
• Instruction Set Architecture
• Study of various on chip peripherals
• Timers & Counters
• Serial Communication
• Interrupt Handling
• Embedded Communication Protocols
• External interfacing Techniques
String Technologies, Hyd

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Microcontroller
• Microcontroller is a device which integrates number of
components of a microprocessor system onto a single chip. It
typically includes:-
 CPU (Central Processing unit)
 RAM & ROM
 I/O inputs & outputs – Serial & Parallel
 Timers
 Interrupt Controller
By including the features that are specific to the task
(Control) , Cost is relatively low.Microcontroller are a “one chip
solutions” which drastically reduces parts count and design
costs.

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Microcontroller

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Microcontroller

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I/O Interfaces
• In an embedded system I/O interfaces are responsible for controlling or
monitoring the functionality. Following are the typical interfaces found in an
embedded system
• Digital Interface
– Digital input and output lines
• Analog interface
– Analog input and output channels
• Serial interface
– RS-232, RS-485, I2C,CAN,SPI
• LAN Interface
• Display Interface
– LCD,LED String Technologies, Hyd

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Microcontroller interfaces

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Microcontroller interfaces

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Major 8 bit Controller Family
• Motorola 6811
• Intel 8051
• Microchip 16Fxx
• Zilog Z80

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8051 Basic Component
• 4K bytes internal ROM
• 128 bytes internal RAM
• Four 8-bit I/O ports (P0 - P3).
• Two 16-bit timers/counters
• One serial interface
CPU RAM ROM

A single chip
I/O Serial
Port
Timer COM Microcontroller
Port

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Companies Producing 8051
• Intel
• Atmel
• Philips
• Siemens
• Dallas
• Maxim
• Sharp and many more…

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8051 Architecture

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A typical 8051 contains:
 CPU with Boolean processor;
 5 interrupts: 2 are external, 2 priority levels;
 2 16-bit timer/counters;
 programmable full-duplex serial port (baud rate
provided by one of the timers);

 32 I/O lines (four 8-bit ports);
 RAM and ROM/EPROM in some models.


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Block Diagram
External interrupts
4K ROM
Interrupt program 128 bytes Timer0 Counter
Control code
RAM Timer1 Inputs
CPU
Bus Serial
4 I/O Ports Port
OSC Control
String Technologies, Hyd TXD RXD

P0 P2 P1 P3
Address/Data

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Features
• It provides many functions (CPU, RAM, ROM, I/O, interrupt logic, timer,
etc.) in a single package
• 8-bit data bus - It can access 8 bits of data in one operation (hence it is an 8-
bit microprocessor)
• 16-bit address bus - It can access 216 memory locations - 64 kB each of
RAM and ROM
• On-chip RAM - 128 bytes ("Data Memory")
• On-chip ROM - 4 kB ("Program Memory")
• Four byte bi-directional input/output port
• UART (serial port)
• Two 16-bit timers
• Two-level interrupt priority
• Power saving mode

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8051 Architecture
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P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
8051 P1.2 3 38 ) 0.1(AD1)
P
Foot Print P1.3

P1.4
4
5
37
36
P0.2(AD2
) 0.3(AD3)
P
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 8051 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 (8031) 30 ALE/PROG
(INT0)P3.2 12 (8751) 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 (8951) 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 )P2.4(A12
(RD)P3.7 17 24 )P2.3(A11
XTAL2 18 23 )
P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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Important Pins (IO Ports)
• One of the most useful features = four I/O ports (P0 -

P3)
• Port 0 ： P0 （ P0.0 ～ P0.7 ）
– 8-bit R/W - General Purpose I/O
– low byte address and data bus for external memory
• Port 1 ： P1 （ P1.0 ～ P1.7 ）
– Only 8-bit R/W - General Purpose I/O
• Port 2 ： P2 （ P2.0 ～ P2.7 ）
– 8-bit R/W - General Purpose I/O
– high byte address for external memory
• Port 3 ： P3 （ P3.0 ～ P3.7 ）
– General Purpose I/O
– Timers(T0,T1) – ext. int (INT0, INT1) – Serial (TXD, RXD)- RD,WR
• Each port can be used
as input or output (bi-direction)

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Port 3 Alternate Functions

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Hardware Structure of I/O Pin
Read latch Vcc

B2
Internal
Pull-Up
Internal CPU D Q P1.X
bus P1.X pin
Write to latch Clk Q M1
B1
Read pin

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Pins of 8051
• Vcc （ pin 40) :

– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND （ pin 20 ） - ground
• XTAL1 and XTAL2 （ pins 19,18 ）

– These 2 pins provide external clock.
– Way 1 ： using a quartz crystal oscillator.
– Way 2 ： using a TTL oscillator.

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Pins of 8051
• RST （ pin 9 ）： reset

– It is an input pin and is active high (normally low).
• The high pulse must be high at least for 2 machine cycles.
– It is a power-on reset.
• High logical state on this input halts the MCU and
clears all the registers.
• Bringing this pin back to logical state zero starts the
program a new as if the power had just been turned on.
In another words, positive voltage impulse on this pin
resets the MCU.
– Way 1 ： Power-on reset circuit
– Way 2 ： Power-on reset with debounce


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XTAL Connection to 8051

Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin.
C2
XTAL2
30pF
C1
XTAL1
30pF
GND

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XTAL Connection to
External Clock Source
NC XTAL2
Using a TTL oscillator

EXTERNAL
XTAL2 is unconnected. OSCILLATOR
SIGNAL XTAL1
GND

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(Address - 0E0h)
• 8 - Bit Register
• Used for operations such as
• Addition
• Subtraction
• Multiplication
• Division &
• Bit Manipulations
• Used for Data Transfer Between 8051 & External memory.

• Used to store Results obtained from Arithmetic as well as logical Operations
and This is Bit Addressable Register

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(Address - 0F0h)
• Used for direct Multiplication & Division operations with Accumulator.

• Can be used as general purpose storage location with its direct address 0F0h.
• Bit Addressable Register.

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(Address - 0D0h)
• Consists of 5 FLAGS
• 4 MATH FLAGS
• Carry
•Auxiliary Carry
• Parity
• Overflow
• 1 USER DEFINED FLAG

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Bit Flag Description
7 CY Carry flag; used in arithmetic, jump,

rotate and Boolean instructions.
6 AC Auxiliary carry; used for BCD
arithmetic
5 F0 User defined flag 0
4 RS1 Register bank select bit-1
3 RS0 Register bank select bit-0

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RS1 RS0 Bank Select

0 0 Bank - 0
0 1 Bank - 1
1 0 Bank - 2
1 1 Bank - 3
Bit Flag Description
2 OV Overflow flag; used in arithmetic

instructions
1 - Reserved for future use
0 P Parity flag; shows parity of register A;

‘1’ => Odd parity; ‘0’ => Even Parity

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(Address - 81h)
• 8 - Bit Register.
• Stack Pointer is Initialized to 07h at RESET condition.
• Instructions such as PUSH and POP modify SP.
• UP - GROWING stack.
• Can be reinitialized to any desired location by the user.

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(Direct Address - NIL)
• Used to hold the Address of external Data Memory.
• Can be used as two individual 8 - bit registers such as
• Data Pointer High (DPL) - Address 82h
• Data Pointer Low (DPH) - Address 83h

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(Direct Address - NIL)
• Used to hold the Address of the next instruction to be executed
• Not directly accessible to the programmer.
• No internal address.

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• Group of registers used for specific purposes in 8051 microcontroller

mainly to
• Configure
• Control, &
• operate.
• Uses address locations from 80h to 0ffh.

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• Accumulator - A*
• Register B - B*
• Program Counter - PC
• Data Pointer - DPTR
• Stack Pointer - SP
• Program Status Word - PSW
• Ports - P0* , P1* , P2* , P3* .
• Timer Load Registers - TL0/1 & TH0/1
• Timer Config. & Ctrl Reg. - TCON*, TMOD

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• Serial Comm. Control Register - SCON*

• Serial Comm. Buffer Register - SBUF
• Program Control Register - PCON
• Interrupt Enable Register - IE*
• Interrupt Priority Register - IP*
NOTE:
Registers marked with * are both Bit as well as Byte Addressable

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• External bus of 8051 is grouped into 4 ports

namely:
• Port - 0
• Port - 1
• Port - 2
• Port - 3
• These ports supports all the three types of
buses namely:
• Address Bus,
• Data Bus, &
• Control Bus.

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• These ports supports all the three types of

buses namely:
• Address Bus,
• Data Bus, &
• Control Bus.

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• All the ports are Bi - directional.

• All the ports are Bit as well as Byte addressable.
• The addresses of the ports are as shown below:
PORTS ADDRESS
PORT 0 080h
PORT 1 090h
PORT 2 0A0h
PORT 3 0B0h

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8051 BLOCK DIAGRAM

I/O
Port 0
A0-A7
ALU PSW SFR
D0-D7
Port 1
I/O
A B
Port 2
I/O
A8-A15
DPTR
PC
DPH ROM
I/O
Port 3
DPL INT
CNTR
SERIAL
RD/WR
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~EA
ALE System Timing BYTE / BIT SFR
ADDRESSIBLE
PSEN IE
System Interrupt
XTAL1
Timers RB3 IP
XTAL2
PCON
RESET RB2
Data Buffers SBUF
VCC Memory Controls RB1
SCON
GND
RB0 TCON
TMOD
TL0
TH0
TL1
TH1
INTERNAL RAM STRUCTURE

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A* B* IP* IE* TMOD TCON*

E0 F0 B8 A8 89 88
MATH REGISTERS INTERRUPT REGISTERS TIMER CONTROL REG
THO TLO TH1 TL1

8C 8A 8D 8B
TIMER / COUNTER REGISTERS
SCON* SBUF PCON PSW*

98 99 87 D0
SERIAL DATA REGISTERS FLAGS
SP
81

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DPTR
DPH DPL PC
83 82
PORT 0* PORT 1* PORT 2* PORT 3*

LATCH LATCH LATCH LATCH
80 90 A0 B0

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TIMERS & COUNTERS

THE TIMER CONTROL (TCON)
7 6 5 4 3 2 1 0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
7 TF1 Timer 1 Overflow flag. Set when timer rolls from all 1s to 0. Cleared when processor
vectors to execute interrupt service routine located at program address 001Bh.
8 TR1 Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to
halt timer. Does not reset timer.
9 TF0 Timer 0 Over flow flag. Set when timer rolls from all 1s to 0. Cleared when processor
vectors to execute interrupt service routine located at program address 000Bh.
10 TR0 Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to
halt timer. Does not reset timer.
11 IE1 External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin
3.3 (INT 1). Cleared when processor vectors to interrupt service routine located at program
address 0013h. Not related to timer operations.
12 IT1 External interrupt 1 signal type control bit. Set to 1 by program to enable external interrupt 1 to
be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external
interrupt 1 to generate an interrupt.
13 IE0 External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin
3.2 (INT 0). Cleared when processor vectors to interrupt service routine located at program
address 0003h. Not related to timer operations.
0 IT0 External interrupt 0 signal type control bit. Set to 1 by program to enable external interrupt 0 to
be triggered by a falling edge Campus
signal. Set training
to 0 by program to enable a low-levelwww.unistring.com
signal or external
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PM 7,0 to generate an interrupt. on
interrupt 43
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THE TIMER MODE CONTROL (TMOD)

7 6 5 4 3 2 1 0
Gate C/T M1 M0 Gate C/T M1 M0

Timer 1 Timer 0
7/3 Gate OR gate enable bit which controls Run/ Stop of timer
6/2 C/T Set to 1 by program to make timer act as counter
5/1 M1 Mode select bit 1
4/0 M0 Mode select bit 0
M1 M0 Mode
0 0 0
0 1 1
1 0 2
1 1 3

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• 8051 supports two types of memories. They are:

• Internal Memory
• External Memory

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INTERNAL MEMORY ORGANIZATION

• On - Chip memory in built to the
Microcontroller.
• It has separate
• on - chip DATA Memory - 128 bytes RAM
• on - chip PROGRAM Memory - 4Kbytes of ROM

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INTERNAL RANDOM ACCESS MEMORY (RAM)
• 128 bytes of internal memory is grouped as:

• Register Bank
• Bit Addressable Area
• Scratch Pad Area

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Internal Data Memory
Accessible by Accessible by direct

indirect addressing Addressing(SFR Area)
(80-FF)=128 bytes (80-FF)=128 bytes
Accessible by direct
& indirect addressing
(00-7F)=128 bytes

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Lower 128 bytes of internal RAM
Scratch Pad Area

(30-7F)
SP=07
Bit & Byte Addressable RS1=0
Area (20-2F) RS0=0
Bank3(18-1F)
Bank2 (10-17)
Bank1(08-0F)
Bank0 (00-07)

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REGISTER BANK
REGISTER BANK 0 REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3

RB0 07h RB0 0Fh RB0 17h RB0 1Fh
RB0 00h RB0 08h RB0 10h RB0 18h

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• To select the register banks, there are 2 bits

present in PSW:
• RS0
• RS1

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BIT ADDRESSABLE AREA
• 16 eight bit locations, ranging from 20h to 2Fh

are bit addressable.
16 locations * 8 bits = 128 bits
i.e.., 128 bits can be individually addressed.

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• These bits can be addressed as

20.0h to 2F.7h
or
00h to 7Fh.

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SCRATCH PAD AREA
• Locations from 30h to 7Fh are available as

Scratch Pad area.
• Can store data such as partial results and such

variables.
i.e., as general purpose locations

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Thus,
4 - register banks => 32 bytes
1 bit addressable area => 16 bytes
1 scratch pad area => 80 bytes
128 bytes of
INTERNAL RAM

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INTERNAL READ ONLY MEMORY (ROM)
0FFFh
4 Kbytes of
Internal
ROM
0000h
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EXTERNAL MEMORY ORGANIZATION
• 8051 Microcontroller supports up-to

• 64 Kbytes of Data Memory
• 64 Kbytes of Program Memory

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• 8051 Microcontroller is interfaced and accessed to external memory using

16 address lines available on PORT0 and PORT 2.
• Address and Data lines are multiplexed using PORT0.
• De - multiplexing of the address and data lines are done by ALE signal

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DATA MEMORY ORGANIZATION
• 8051 Microcontroller supports

• 64 Kbytes of External Data Memory
• 128bytes of Internal Data Memory

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External Memory Interface
ADD-H
8051 Memory
Latch ADD-L

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• External Data Memory is accessed using

16 - bit address lines.
RD bar and WR bar are used as strobe signals
• Address range : 0000h to 0FFFFh
- External Memory
00h to 7Fh
- Internal Memory
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FFFFh
FFh
SFR’s
Direct
Addressing
64 Kbytes
only
80h of
External
7Fh Direct Memory
& In Direct
Addressing
only
00h
0000h

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Program Memory
64K FFFFH
4K External
0FFFH ROM
EA=0
Internal
ROM
EA=1
0000H 0000H
Campus training PSEN www.unistring.com

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Data Memory
64K FFFFH
128 bytes
External
7FH RAM
Internal
RAM
00H 0000H
Campus training WR RD www.unistring.com

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Internal RAM allocation

7FH
General RS1 RS0 Register Bank Address

purpose RAM 0 0 0 00H-07H
0 1 1 08H-0FH
30H 2FH 1 0 2 10H-17H
Mixed Bit/Byte 1 1 3 18H-1FH

Addressable
1FH 20H
Register Bank3
18H 17H
Register Bank2
0FH 10H
Register Bank1 String Technologies, Hyd

08H 07H Stack
Pointer
Register Bank0 Campus training www.unistring.com
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Internal RAM and SFR region
FFH FFH
Upper Accessible
Accessible SFR
128 by Indirect by Direct
addressing addressing
only Ports,
only
Timers,
Control
Registers,
80H 80H
Accumulator
7FH
,Stack
Pointer,
Accessible
Etc,.
by Direct &
Lower Indirect
128 addressing
00H
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SFR Memory map
FF
F8
F7
F0 B
EF
E8
E7
E0 ACC
DF
D8
D7
D0 PSW
CF
C8
C7
C0
IP BF
B8
P3 B7
B0
IE AF
A8
P2 A7
A0
SCON SBUF 9F
98
P1 97
90
TCON TMOD TL0 TL1 TH0 TH1 8F
88
P0 SP DPL DPH PCON 87
80
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8051 Memory Structure
External
External
(64Kb)
indirect direct
(128) (128)
EA bar=0 EA bar=1 direct

External Internal & indirect
(128)

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Embedded system design methodology

with Host and Target development setup

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Host – target approach

• A host target embedded
development setup will be
used

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Keil uVision IDE

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Write your feedback on your forms

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Embedded Systems: Campus Training On

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12/07/21 09:06 PM

The 8051 Microcontroller Architecture & Interfacing

Unistring Tech Solutions Pvt. Ltd, 5th Floor, Ureka

Campus training www.unistring.com

Embedded Systems Overview

String Technologies, Hyd

Campus training www.unistring.com

Campus training www.unistring.com

Campus training www.unistring.com

Campus training www.unistring.com

Campus training www.unistring.com

Campus training www.unistring.com

Campus training www.unistring.com

Major 8 bit Controller Family

String Technologies, Hyd

Campus training www.unistring.com

CPU RAM ROM

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Companies Producing 8051

Campus training www.unistring.com

Campus training www.unistring.com

A typical 8051 contains:

 CPU with Boolean processor;

 5 interrupts: 2 are external, 2 priority levels;

 programmable full-duplex serial port (baud rate

provided by one of the timers);

 RAM and ROM/EPROM in some models.

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String Technologies, Hyd TXD RXD

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String Technologies, Hyd

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String Technologies, Hyd

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Foot Print P1.3

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Important Pins (IO Ports)

• One of the most useful features = four I/O ports (P0 -

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Port 3 Alternate Functions

String Technologies, Hyd

Campus training www.unistring.com

Hardware Structure of I/O Pin

Read latch Vcc

Write to latch Clk Q M1

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• Vcc （ pin 40) :

• GND （ pin 20 ） - ground

• XTAL1 and XTAL2 （ pins 19,18 ）

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• RST （ pin 9 ）： reset

– Way 1 ： Power-on reset circuit

– Way 2 ： Power-on reset with debounce

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XTAL Connection to 8051

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Using a TTL oscillator

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• Used for Data Transfer Between 8051 & External memory.

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• Used for direct Multiplication & Division operations with Accumulator.

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