CDA 3101 Summer 2007

Introduction to Computer Organization

Processor Organization
Datapath Design

21 June 2007
 Review
• Construction of the ALU
– Building blocks (digital design gates)
– Modular design
• Multiplexor chooses operation
• All operations are performed in parallel
– Carry lookahead adder
• Computer arithmetic
– Finite precision
– Laws of algebra do not always hold
– Integers: two’s complement representation
– Floating point: IEEE 754 standard
 Overview
• Computer organization (microarchitecture)
• Processor organization
– Datapath
– Control
– Register file
• Processor implementation overview
• Clocking methodologies
• Sequential circuits
– Latches
– Registers
 Processor Performance
CPU time = IC * CPI * Cycle time
Program

Compiler

ISA

Microarchitecture

Hardware
 Computer Organization

Address Bus
Memory
Processor Data Bus
Control Bus Subsystem

I/O . . . I/O
device device
I/O Subsystem
 The Processor
• Processor (CPU)
– Active part of the computer
– Does all the work
• Data manipulation
• Decision-making
• Datapath
– Hardware that perform all required operations
– ALU + registers + internal buses
– The brawn
• Control
– Hardware which tells the datapath what needs to be done
– The brain
 Processor Organization
Address bus Data bus
Control bus signals

Control signals
Control
Unit Data values

Registers
Control signals

Data values (operands)

ALU
Data values (results)
 Implementation of MIPS
• ISA determines many aspects of implementation
• Implementation strategies affect clock rate and CPI
• MIPS subset to illustrate implementation
– Memory-reference instructions
• Load word (lw)
• Save word (sw)
– Integer arithmetic and logical instructions
• add, sub, and, or, and slt
– Branch instructions
• Branch if equal (beq)
• Jump (j)
 Implementation Overview

Instruction rd Data
memory
rs Address
PC

Address Registers ALU

rt Data
Instruction memory

+4 Data
imm

Opcode, funct

Controller

° Datapath is based on register transfers required to execute instructions

° Control causes the right transfers to happen
 Logic and Clocking
• Combinational elements
– Outputs depend only on current inputs
– Example: ALU (adders, multiplexers, shifters)
• Sequential elements
– Contain state
– Output depend on input and state
– Inputs: data values and clock
– Memory, registers
• Asserted signal: logically high
 Clocking Methodology
• Determines the order of (gate) events
– Defines when signals can be read/written
• Clock: circuit that emits a series of pulses
clock cycle
time

Timing diagrams

clock C Asymmetric clock

(C1 AND C2)

Rising edge Falling edge

 Edge-Triggered Clocking
• Either the rising edge or the falling edge is active
• State changes only on the active clock edge
State State
element Combinational element
logic
1 2

clock

State Combinational
element logic
 NOR SR Latch

State 0 State 1

S - set
Inputs Outputs: Q and Q
R - reset
Clocked SR Latch
 Clocked D Latch

D
C

Output is initially deasserted

 D flip-flop
D D Q D Q Q
D D
latch latch
C C Q Q

Setup time
D
hold time

Falling-edge trigger, output is initially deasserted

 Register File

Read ports

Write port
Register File Read Ports
Register File Write Ports
 Conclusions
• Datapath performs work of computation
• Building blocks for datapath
– ALU: Performs work of computation
– Register File: Data I/O from registers
• Register file implemented with D flipflops,
multiplexers, and decoder
– Clocked (synchronous) logic circuits
– Write-enabled data transfer into registers
– No need to protect data transfer from registers
Anticipate the Mid-Semester
Break!!
 New Topic –Datapath Design
• Datapath implements fetch-decode-execute
• Design Methodology
Determine instruction classes and formats
Build datapath sections for each instr.fmt.
Compose sections to yield MIPS datapath

• Challenge #1: What are instruction classes?

• Challenge #2: What components are useful?
 Simple Datapath Components
• Memory stores the instruction
• PC address of current instruction
• ALU executes current instruction

Increment program counter

+
4
PC Read Addr
Instruction
fetch
Instruction
Memory
 R-format Datapath
• Format: opcode r1, r2, r3
ALU op

Register 3
File
Read Reg 1 Read
Instruction
Data 1 Zero
Read Reg 2
Write ALU
Register Read
Write Data Data 2
Result
Register
Write
 Load/Store Datapath Issues
• lw $t1, offset($t2)
– Memory at base $t2 with offset
– lw: Read memory, write into register $t1
– sw: Read from register $t, write to memory
• Address computation – ISA says:
– Sign-extend 16-bit offset to 32-bit signed value

• Hardware: Data memory for read/write

Load/Store Datapath Components

MemWrite
16 32
Sign
Address Extend
Read data

Data
Write data Memor
y 1101 … 0011 
1111 1111 1111 1111
MemRead 1101 … 0011
 Load/Store Datapath Actions

1. Register Access Register File

-- Instruction/Data/Address Fetch
1. Memory Address Calculation ALU
-- Address Decode
1. Read/Write from Memory Data
Memory
2. Write into Register File Register File
-- Load/Store Instruction Execute
 Load/Store Datapath

Fetch Decode Execute

 Branch Datapath Issues
• beq $t1, $t2, offset
– Two registers ($t1, $t2) compared for equality
– 16-bit offset to compute branch target address
• Branch target address – ISA says:
– Add sign-extended offset to PC
– Base address is instruction after branch (PC+4)
– Shift offset left 2 bits => word offset
• Jump to target
– Replace lower 26 bits of PC with lower 26 bits
of instruction shifted left 2 bits
 Branch Datapath Actions

1. Register Access Register File

-- Instruction/Data Fetch
1. Evaluate Branch Condition ALU #1
2. Calculate Branch Target ALU #2
-- Branch Computation – similar to
Decode
1. Jump to Branch Target Control Logic
-- Branch Instruction Execute
Branch Datapath

Fetch Decode Execute

 Delayed Branch (MIPS)
• MIPS ISA: Branches always delayed
- Instr. Ib following branch is always executed
- condition = false => Normal branch
- condition = true => Ib executed
Why bother?
1. Improves efficiency of pipelining
2. Branch not taken (false condition) can be
common case
 Conclusions
• MIPS ISA: Three instruction formats (R,I,J)
• Datapath designed for each instruction format
• Datapath Components:
-- R-format: ALU, Register File
-- I-format: Sign Extender, Data Memory
-- J-format: ALU #2 for target address comp’n.
Trick: Delayed branch to make pipeline efficient
Have a safe Break Week! 