3Com

computer communication compatibility

3C400 Multibus

F,L~ernetController Reference Manual

J I

3Com Ca-rxx-ation

computer commUnicatIOn compabbll,ly .

Model 3C400

MULTIBUS Ethernet (ME) Controller

Reference Manual

May 18, 1982

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ABSTRACT

This document describes the 3Com 3C400 Multibus Ethernet Controller that

connects any Multibus compatible system processor to a DEC-Intel-Xerox

Ethernet Communication System.

300m Corporation 1390 Shorebird Way, Mountain View, california 94043 USA

(415) 961-9602 Telex: 345546

Tab!e of Contents

3eorn Ccrpaotial

~ompuler communlCa1l0n compatlblhty

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TABLE OF CONTENTS

CHAPTER 1 - 3COM ME CONTROLLER SPECIFICATiONS

1.1 DESCRIPTION 1.2 ME FEATURES

1.3 ME SPECIFICATIONS

CHAPTER 2 - BACKGROUND INFORMATION 2.1 BASIC ETHERNET SUBSYSTEMS

2.2 EXAMPLE FilE TRANSFER

2.3 HOW 3COM PRODUCTS IMPLEMENT ETHERNET

FOR MULTIBUS COMPATIBLE SYSTEMS

2.4 ETHERNET OPERATION •

2.5 TRANSMISSION SUBSYSTEM

2.6 ME CONTROLLER SUBSYSTEM

CHAPTER 3 - PHYSICAL DESCRIPTION

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3.1 ENVIRONMENT 3.2 PACKAG!NG

3.3 BLOCK DIAGRAM

CHAPTER 4 - 3COM ME PROGRAMMING 4.1 MEMORY ALLOCATION

4.2 TRANSMIT/RECEIVE

4 .3 PROG RAM~11 NG ANOMAL I E S 4.4 OPERATION

CHAPTER 5 ~ INSTALLATION AND CONFIGURATION CONSiDERATiONS

5.1 INSTALLATION CHECKLIST

5.2 ETHERNET ADDRESSING CONSIDERATIONS

CHAPTER 6 - FACTORY WARRANTY APPENDICES

A. ORDERING INFORMATION

B. B I BLI OGRAPHY

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SpecifIcatIons DescrIption

3Com Corporation

compute~ communoeatlOl1 compatlbthty

afAPTER 1

3COM ~ CONTROlLER SPECIFICATIONS

1.1 DESCRIPTION

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The 3C400 Multfbus Ethernet (ME) Controller provides the connection

to Ethernet for any Multibus compatible system processor. It consists of

..

one Multtbu5 (IEEE-796) board that plugs fnto the Multfbus. (See Figure

1-1 below).

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FIGlR 1-1. 3COM KJLTlBUS EllIERNET CONTROLLER BOARD SET

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1-1

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Specifications Description

3Com Corporation

computer communicatIOn compatibility

COnnection from the 3C400 ME Controller to Ethernet is made via the

3Com Ethernet TransceIver and Transceiver Cable, Oi any other Ethernet

compatible transceiver and cable.

The 3C400 Controller, 3C100 Ethernet Transceiver and the 3Cll0

Transceiver Cable conform to the Ethernet specifications, version 1.0,

publ ished by DEC, Intel, and Xerox on 30 September, 1980. When coupled with customer supplied driver sofTware, they implement layers one

(physical) and two (data I ink) of the International Standards

Organization Reference Model for Open Systems Interconnection. Any

Multibus compatible system processor so equipped will be compatible with i any other Ethernet-based system at the physical and data link levels.

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3eorn CorporatOO

computer commumcatlOn compatlbollty .

Spec If I cat I ons Features

1.2 ~ FEATlRES

e Compatible with

Intel.

Xerox Ethernet.

• Compatible with Multlbus (IEEE-796).

• Connects to Ethernet using 3C01 . ternet Transceiver and Transceiver Cable or any other transceiver and cable that conform to the Ethernet specification.

• Controller, transceiver, and cable together provide a complete hardware imp!ementatlon of the Ethernet specification except for multicast address comparison and random number generation for retransmIssion timing.

• Includes 8K byte dual-ported m~mory whIch appears In Multlbus memory space. Transmission between the dual-ported memory and Ethernet do not consume Multlbus cycles, allowing concurrent processing.

• Three 2K byte buffers can each handle maximum packet size allowed by Ethernet specification. One buffer Is dedicated to transmission, two to reception of Ethernet packets.

• Under software control, each packet buffer may be independently connected to either the Ethernet or the Multibus.

• Multlbus-addressed buffers allow In-place packet assembly, processIng and multiplexing.

• Can receive mInimally spaced packets.

• Controller can be selectively enabled to recognIze packets containing station address, broadcast packets; multicast packets or all packets.

• Ethernet address assIgned by 3Com is held In PROM on controller and can be referenced or replaced by software when loadIng address recognIzer.

• Manchester decodIng using phase-locked loop circuitry.

• 32-blt CRC generated on transmIssIon and verified on reception.

• Hardware generation and removal of preamble.

• Hardware retransmission timing with random number suppl ied by software.

• Hardware detection of oversized and undersized packets and alignment errors.

• Functions as 16-bit memory slave and is compatible with 8-blt and 16-blt masters.

• Contained on one Multlbus board.

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computer communlCatl()n compatlblhty

1.3 ~ SPECIFICATIONS

Compatlbt Iffy

Ethernet

Multibus

IEEE-796

FunctIons

Memory

Transmit

Receive

Control & Status

Byte Ordering

Address

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Specifications M:: Techn 1 ca I

Conforms fully to Ethernet specification, version 1.0, published 30 September, 1980, by DEC, Intel, and Xerox.

Conforms fully to Multibus specification.

J:'lIn r- +fl"lnc: .. c: 1fi._hr+ moml"lr-v c:1 .. "o r""'I"\",+t"'l~

. _ .. _ .. _ .. _ -... . _. _.. "'_'''_', -. - ... -. ,.,..., ... ..,.Q I ,.., I G

with 8-bit and 16-bit masters.

Compl iante is 016 M24 VO (16-bft transfers. 24-bit addressing, non-bus vectored interrupts).

Serial/parallel and parallel/serial conversions.

TransmIt and receive buffering. Framing of packets.

Manchester encoding and decoding. Address recognition

Coil islon and error detection. Preamble generation and removal. Carrier sense and deference. Backoff and retransmission timing. Coil islon fragment filtering.

Frame check generation and detectIon. Alignment error and overrun filtering.

One 2K byte dual-ported RAM memory.

Two 2K byte dual-ported RAM memories.

Registers which occupy 2K bytes~of Multlbus

address space. f

low order first or high order first, switch selectable.

Occupies 8K bytes of Multibus memory address space. Starting address set by switches at any 8K byte address boundary in range 0 to 1016K bytes.

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3Corn CorporatOO

computer communIcatIOn compalobollty

Timing

Bit Rate

Packet Spacing

Transmit Delay

Receive Delay

Jam Time

Ethernet Packet Format

length

Format

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Frame check sequence

Preamble

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SpecifIcations ~ Technical

10 mill ion bits per second

9.6 microseconds minimum

1 microsecond typical, without deference

3 microseconds typical

Transmits 32 bits of zeroes when collision is detected •

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512 bits minimum, 12,144 bits maximum, excluding 64-bit preamble.

Destination Address •••••• 48 bits

Source Address ••••••••••• 48 bits

Type ••••••••••••••••••••• 16 bits Data ••••••••••••••••••••• 8n bits

where n=46 minimum, 1500 maximum Frame Check Sequence ••••• 32 bits

32 bit CRG generated on transmit, verified on receipt.

Generated and removed by controiler.

1-5

3Com CcrpaatiJn

compuler communicatIOn compatibility

Address Recognltfon

Ethernet-Address

Address Recognizer

Error Handling

I t

Interrupts

Interrupt Conditions

Priority ievels

Software Functions

Installation

Size

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SpecificatIons ~ Technical

Unique 48-bft address assIgned by 3Com. Held I n socketed PRO~~ on contro II er, appear sIn Multlbus address space.

Station Ethernet address held In RAM memory, may be loaded from Ethernet address PROM or with an address supplied by software. Can be selectively enabled by software to recognize packets containing:

Station or broadcast address

Station, broadcast, or multicast address Any ~ddress

Controller can be selectIvely enabled by software to reject packets with FCS, alignment or range errors.

Selectively enabled by software:

Transmit done Recei\e buffer A full Receive buffer B full Collision (jam)

All Interrupts use a common priority level, jumper selectable from INTO to INT7.

The fol lowing functions must be performed by customer software:

Loading of Ethernet address Mu I t I cast address compar I son ,_

Random number gener~tlon for retransmission timing after collision.

One Multlbus-standard board

30.5cm X 17.1cm 121n X 6.751n

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Spec if icat ions ME Technical

3Com Caporaticn

commun.cahOn compa!lblhty computer

Slots

Requires one slot.

power

5A at +5V

O.5A at +12V for transceiver

Bus loading

One DC load

Transceiver cable connector Ethernet-standard fema Ie 15-p I n "0" subminiature connector attached to the controller via cable.

Transceiver cable

Uses Ethernet-standard transceiver cable which must be ordered separateiy.

Ethernet address

Unique a~dress suppl led by 3Com for each controller. contained in onboard PROM.

Operating Environment

Temperature

Humidity

10% to 90% without condensation

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1-7

Background Information Ethernet

3Com Corporation

- commUnication compatlblhty comPIJ,er

CHAPTER 2

BACKGROUtI) INFORMATION

This chapter covers some background Information about both the

Ethernet and the 3Com ME Controiier.

In the last decade, comput~rs have grown from a luxury to a

necessity in most businesses. Similarly, in the next decade,

Inter-computer communication will grow from a luxury to a necessity.

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The "Ethernet" network, developed for mechl ne-mechl ne ccemunl ce+ ton ,

was pioneered at Xerox Corporation as an appropriate implementation for

inter-computer communications. In use since 1974, the Ethernet has

evolved to an industry standard, documented in the Ethernet

Specification, published September 30, 1980 by DEC, Intel, and Xerox.

The benefits of modern computerized workstations are now magnified

as they communicate Information to other devices at 10 mi II ion

bits-per-second over the Ethernet. What's more the Ethernet network can

be tai lored to end user's needs and workstations once t~e Ethernet t

coaxial cable Is In place. This means multiple workstations can share

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Background Information Ethernet

3eom CaporatOn

:ompuIer communIcation compatlDllity

resources such as:

Word processors

Data bases

Printers

Process control stations

Electronic mail systems

Array processors

Gr~phics stations

Laser printers

Transaction workstations

Etc.

Individual workstations and shared resources are plugged into

Ethernet Information Outlets in the wal I the same way telephones are

plugged into telephone wal I-outlets. However, the Ethernet's 15-pin

connector is more complex than a telephone connector.

Each Ethernet device is assigned a unique address (I ike a unique

telephone number), therefore, it can be moved around and plugged into any

convenient Ethernet Information outlet. Further, al I devices plugged

Into the Ethernet can talk to each other, by mutual agreement, similar to

two people talking on the telephone.

Ethernet, due to Its standardized physical and logical protocol,

allows users to mix and match equipment from multiple vendor~.

In the future a voice capabf' fty will probably be Integrated Into

Ethernet for store-and-forward voice communications to complement

electron I c rna I I •

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3Com Capcration

~ef communoealo()l"l compatIbilIty

2. 1 BAS I C ETHERNET SLBSYSTEMS

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Background Information Ethernet Subsystems

The Ethernet is a bus-oriented communication system that supports up

to 100 stations using a 50 ohm coaxial cable as the bus.

fIgure 2-1 below shows the basic parts of a typical Ethernet system,

with ~orkstat!ons connected to the Ethernet coaxial cable.

The Transmission Subsystem is made up of 50 ohm coaxial cable,

terminators, transceivers, and transceiver cables.

The Controller Subsystem is the set of controller boards and the software

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MULTIBUS

F I GORE 2-1. BAS I C ETHERNET SLBSYSTEMS

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2-3

Background InformatIon Ethernet Subsystems

3Com Corporation

computer communICatIOn compatlblhty

supporting them.

The Station Subsystem Is everything else associated with the station,

such as, the terminal, processor, disk, and higher level protocol

software.

These three subsystems are discussed again later in this chapter, in

terms of 300m product implementation:

Meanwhile, the following example describes how a file of information

is transferred from one device to another using Ethernet.

2.2 EXAMPlE FilE TRANSFER

(This is an example text file transfer using a Fi Ie Transfer Program

running on the host processor.)

1. The terminal user runs the FI Ie Transfer Program, connects to the

receiver, and specifies the file to be transferred.

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2. The file's characters are mapped Into device-Independent virtual

characters (by software) to meet protocol specifications.

3. The mapped character stream Is then routed to a virtual circuit set up

between the two devices.

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Background Information Example File Transfer

3eorn Corporation

computer communIcatIon compatlbollty

4. The vIrtual circuit protocol software breaks the character stream Into

packets for transmission. (It also retransmits corrupted packets, and

limits data rate to avoid overruns.)

5. The packets are then passed to the Ethernet driver software.

6. The Ethernet driver then copieo the packet into a packet buffer and

tells the controller to transmit It.

7. The controller walts until the coaxial cable Is not in use, then

transmits the packet.

8. The Ethernet transceiver receives the packet's bit stream and injects

it onto the coaxial cable. (If the transceiver detects a col I ision, it

signals the controller to retransmit.)

9. The receiving station recognizes its address and reverses the above

procedure: bits are received by the transceiver, fed to the controller,

passed to software that reassembles the packets, maps the characters, and

stores the data.

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3eom Corporatro

Background Information 300m Implememtation

'" f computer communicatIOn compatlblhty

2.3 HOW 3COM PRODUCTS IJoPlEMENT ETHERNET FOR t«JlTIBUS CC»PATIBlE DEVICES

For a complete local computer network, there are only three

additional components needed by Multlbus compatible systems:

1. 3Com Ethernet Transceiver - fully conforms to published Ethernet specifications and connects directly to the Ethernet coaxial cable.

2. 300m Ethernet Controller - plugs directly into the Multibus

3. Higher-level Protocol Software - providing high-level network protocol

1 services - Including data I ink drivers. 3Com's UNET Software Is UNIX

~ compatible and provides the Internet Protocol (IP), Transmission Control Protocol (TCP), file transfer protocol (UFTP), electronic mai I protocol

(UMTP), virtual terminal protocol (UVTP), etc.

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3Com Ccrpcration

Background Information Ethernet Operation

computer comrnuncanon compa11blilty

2.4 ETHERNET OPERATION

The Ethernet is a carrier sense, multiple access transmission system

with collision detection (CSMA/CO). To transmit a packet, a station

waits for quiet on the network (defers). When the network Is quiet. it

During packet transmission, the station also watches for collisions

with other transmitters; these may occur within one round-trip time

through the network. The station Is said to have "acquired the network"

If no collision occurs In that time interval. It a collision does occur,

the station transmits 4 to 6 additional bytes of data (jam) and the

aborts the packet. The extra bytes Insure that any other participant In

the col I Is Ion Is sure to see It. The station then walts a random amount

of time (backoff) before retransmitting (after deferring to packets In

progress on the network).

2.5 TRANSMISSION SUBSYSTEM

The transmission subsystem, In the form of a 3Com "sta~er package",

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3Com Copoatcn

Background Information Transmlsston Subsystem

computer .;ornmun.catlOn compatibility

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(Model 3C440) is shown In FIgure 2-2 below.

It consists of four types

of components: transceIver cables. transceIvers. coaxial cable. and

tenlll nators.

These are described below.

Transceiver Cable - The transceiver cable is a 15 meter shielded twisted

pair cable that connects the controller to the transceiver. It has 4

pairs, one each for transmit, receive, col I Ision detect, and power. It

has a male 15 pin connector with lock posts on the controller end and a

femaie i5 pin 0 connector with sl ide lock assembly on the transceiver

end. Thus the cables can be concatenated to make a longer cable, up to

the maximum length of 50 meters.

Station No.1 Station No.2 Station No.3

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Transceiver ~ Transceiver! Transceiver!

Cable Cable Cable

15 meter ~ 15 meter 15 meter

Tran~;ver, NoJ Tran,,!,ehler NoJ TranscehlerNoJ

o 0 c:=tF===::l 0 c:=tF===::l 0 0 , .

Terminator Coaxial Cable Coaxial Cable Termi~ator

15 meter 15 meter

----------30meter----------+ Ethernet Transmission System

FIGURE 2-2. 3COM ETHERNET TRANSCEIVER STARTER PACKAGE

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Background Infon.atlon Transmission Subsystem

3Com Corpcratial

computer eommorucaton compatibility

To minimize EMI (electro magnetic Inteference), the connectors have

!ntern~! shields connecting the cable shield to the shell of the

connector.

The male cable connector can either be brought out of the wall to the

station or mounted on a cover plate providing a bulkhead disconnect at

the wal I. When mounted on the cover plate, it has been referred to as

the "Information Outlet." (see Figure 2-3 below)

Transceiver - The 3Com transceiver Is compatible with the DEC, Intel and

Xerox Ethernet specification. It makes a high impedance connection to

the common coaxial cable and provides electrical isolation between the

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~ Ethernet Information Outlet

FIGmE 2 - 3. INFORMATION OUTlET

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Background Information Transmission Subsysta.

computer communocatlOt1 compatibility

coaxial cable and the twisted pair cable.

The transceiver injects transmit signals from the controller into the

coaxial cable. The transceiver also receives signals from the coaxial

cable which appear on the receive lead of the transceiver cable with

balanced signalling.

The receiver also provides correction for signal distortions caused by

traveling through long lengths of coaxial cable.

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The col I ision signal appears if there is a signal present from any other

station on the network. When transmitting, this Indicates a col I ision.

When not transmitting, it Indicates the presence of other signals on the

network.

Coax I a I Cab I e - The co a x I a I cab I e I s a 50 0 h m cab lew i t h m u I tIp I e

shields to minimize susceptability to strong RF fields.

Cable Connectors - Cable sections are terminated with standard N-series

connectors. Rubber boots cover the connectors to prevent multiple

connections of the coaxial shield to building grounds i a potential source of ground induced noise into the coaxial shield. Coaxial cable

.

sections are joined by insulated barrel connectors (N-Serles

female-female adapters).

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Terminators - The ends of a coaxial cable segment are terminated with 50

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Background Informa~lon Transmission Subsys~em

lCorn Corporation

computer commun,catoQl"l compatibility

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ohm terminators wIth insulated outsIde covers.

2 • 6 JE CONTROLLER SlI3SYSTEM

The ME Ethernet Controller Interfaces the transceiver to the

Internal bus of the Multibus system to which it Is connected. It

performs serial-paral lei and parallel-serial conversIon. buffering. CRC

generation and checking. address recbgnitlon. phase encoding and decoding

- discussed below. The I/O structure and speed of the processor

determine how these functions are partItIoned between hardware and

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software (or microcode) in the Ethernet station.

Buffering:

Most processors have bus transfer rates that are unduly

stressed by the 10Mbps Ethernet bandwidth, therefore, ful I packet buffers

are provided to keep pace with the bit rate of network traffic.

CRC Generation And Checking:

The cyclic redundancy code (CRC) uses the

32 bit polynomial from the U.S. Department of Defense Autodln I I system.

The CRC function Is implemented in hardware on the ME.

Address Recognition:

The controller watches every packet that passes to l

detemi

Jhether to accept the packet, based on Its destination address.

The ME Control!er !mp!ements address recognition fn hardware to minimize

CPU overload.

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Phase Encoding, Decoding. and Transceiver Interface:

Man c h est e r

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3Corn Corpcratioo

Background Information 3Com Controller Subsystem

computer communlCill1()f1 compatlbtlity

encod 1 ng I s used for data transm i ssl on on the Ethernet. I t has a 50%

duty cycle. The fIrst half of a brt cel I contaIns the complement of the

bit and the second half of the bit cell contains the bit.

Phase Encoding Is done In the controller by excluslve-ORlng the clock with the data. (Decoding is also performed in the controller. Partitioning of encode-decode functions into the controller rather than

the transceiver minimizes wires to· the transceiver whl Ie minimizing

transceiver size and power dissipation.)

Phase Decoding In the ME Controller is done by an analog phase-locked

loop technique. This technique has the advantage of tolerating more phase jitter than alternative techniques In use. twice the tolerance of a

typical one-shot decoder and four times the tolerance of a typical

digital state-machine decoder.

The Transceiver Interface contains I ine drivers and receivers.

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PhysIcal Description Environment

QlAPTER 3

PHIS i CAL OESCR I PT: ON

3. 1 ENY IRONMENT

The ME Controller Interfaces a Multlbus compatible processor to an

Ethernet transceiver.

The ME Controller plugs Into the same Multlbus backplane as the

processor and resides in the same enclosure with l r , An Ethernet

transceiver cable (approximately 50 feet long) connects the ME Controller

to the Ethernet transceiver. The Ethernet transceiver in turn taps

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directly into the Ethernet coaxial cable.

According to the International Standards Organization Open Systems

Interconnection Reference Model, the ME Controller performs part of both

the physical and link layer services, the first and second of seven

3/ E,/TCm·'ME3!

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3Com Corporation

computer communICatIOn compat!blhty

layers of service (see FIgure 3-1 below).

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Physical Description EnvlroMlent

The two main functIons of the ME In the link layer of the ISO Model are:

1. Oata Encapsulation

o framing (frame boundary dellmltatton)

o addressing (handling of source and destination addresses)

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o error detection (detection of physical channel transmission errors)

-----TR,A.NSCE I VER

--_ .... _--.-COAXIAL CABLE

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APPLI CATION

PRESENTATION

-~--111!11111!1!!!!!!!!!!!!!!!!!!!!!!!!!!

HIGHER LEVEL PROTOCOLS

SESSION

TRANSPORT

-------.

NETWORK

------- ---------

LINK

NET

PHYSICAL

- HOST CO~fPUTER

- CONTROLLER BOARD

FIGURE 3-1. I SO PROTOCOl HIERARCHY

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Physlcel Description Environment

3Com ea-poration

computer communlcahon compatibility

2. L I ok Management

o channef ai iocatlon (collision avoidance)

o contention resolution (collision handling)

In the physical layer of the ISO model~ the controller performs preamble generation/removal and bit encoding/decoding (between binary and

phase-encoded form).

3.2 PACKAGING

The ME Controller is a single multibus compatible PC board whose

overall dimensions are 12 inches x 6.75 inches. It uses one Multibus

5/1 ~

3-3

PhysIcal Description Packaging

3Com Corpa-atim

computer communlcatl()n compatlbtlity

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backplane slot as shown in Figure 3-2 below.

On the edge opposite the gold fingers is a 14 pin male header. A

shielded cable, with four twisted pairs terminated to a female socket at

one end, mates the ME Controller to the Ethernet Transceiver Cable. At

this end of the shielded cable !s a tin plated sub-miniature 0 connector.

controller end. This shield drain Is to be connected to the chassIs

...

ground of the Multfbus cardcage.

The ME Controller Is a high density four layer PC board with two

circuit trace layers plus continuous ground and power planes.

F IGlRE 3-2. rE PACKAG IN; ENY IROmENT

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3-4

Physical Description Packaging

computer communoeatlOn compatibility

f

The-PC iayout design rules foiiowed are:

0 Ten mi I traces
0 Ten mi I air gaps
0 At most two traces between IC leads
0 Four layer pcb
0 Intact internal voltage and ground planes The ME Control!er can be used with any transceiver that conforms to

the DEC-Intel-Xerox Ethernet specifications.

5/18/82/TCOMME3/

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Physical Description Block Diagram

3Com CorpaotOO

":Omputer communoeatlOn compabblhty

3.3 BLOCK DIAGP~

The major ME Controller components are shown In Figure 3-3 below.

The ME Controller presents to the Multtbus a fuji 16 bit interface.

All bus transfer instructions to a 16 bit slave device are impiemented on

this controller.

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The 3Com t.'u I t i bus Ethernet Contro II er I s memory-mapped and therefore

appears as 8K bytes of memory on the Multlbus; 4K is used for two receive

buffers and 2K is used fer one transmit buffer. There are four bytes of

ETHER.
r- ADDRESS I
MEMORY RECEIVE
SYNCH
ADDRESS
I COMPARE
STATUS r- RECEIVE t . PARAllEL
& CONTROL MEMORY i1 CONVERS
I t i I
RECEiVE
~ ADDRESS SEQUENCE
M I MULTIPLEX I-
t
U N t I
L T -GJ
T 16 BIT E BYTE CRC f- ECl
I R COUNTER SECTION SECTION
B F , l
U A
S C
E r- ADDRESS
MULTIPLEX TRANSMIT
1 l
, CLOCK


~y TRANSMIT . SERIAL
IEMORY I COUNTERS.
I
S TRANSMIT
" SEQUENCE. FIGURE 3-3. tE CONTROlLER FUNCTIONAl BLOCK DIAGRAM

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Physical Description Block Diagram

computer communICatIOn compatibility

control and two words of status In the lowest 2K of memory. The actual

device address Is switch selectable on any 8K boundary.

On transmit, the processor loads the packet to be sent Into the

TRANSMIT MEMORY (see Figure 3-3 above). Once the transmit bit is set In

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the control byte no further processor intervention is required.

Successive bytes are taken from the TRANSMIT MEMORY and placed Into the SERIAllZER where they are converted to a serial bit stream. The

serla! lzed data Is fed to both the CRC (Cyclic Redundancy Check) and to

the ECl SECTION which does a level conversion to be compatible with the

Ethernet Transceiver. The CRC Is automatically appended to the end of

the transmit data packet.

On receive, the processor must first make available to the ME one or

both of the RECEIVE MEMORIES available (see Figure 3-3 above) by setting

the proper control bits. Since hardware address recognition is

incorporated Into this design, the receive packet Is further qual ified.

The ME can be hardware configured to receive only packets with correct

physical, multicast, and/or broadcast addresses. After address

recognition, the Ethernet data enters the ECl SECTION where a phase lock loop generates a proper synchronizing clock from the incomin9 date. Also

the ECl SECTION does a level cpnversion to TTL signals. The serial data

is sent to the PARAllEL CONVERSION logic (and converted to a byte format) and to the CRC SECT i ON. The CRC Is ca I cu I atedand compared to the eRe

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code appended to the end of the packet by the transmitting station. If a

CRC error occurs, (Frame Check error) a flag is set in the first byte of the RECE I VE f·1EMORY.

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3Com Ccrporation

computer communlcatoon compatibIlity

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DlAPTER 4

foE PROOfW0t4 J NG

Progrannlng Memory A II ocat (on

The fol lowing chapter Is Important for development of software

drivers.

4.1 MEMlRY ALLOCATION

The ME occupies 8K bytes of the Multlbus 24 bit address space. See

Figure 4-1 below. Switches on the controller select the base address of

I (

MECSR Control and Status Register
MEBACK Retransmission Backoft Counter
Station Address ROM
Stat I on Address RA~'
Transmi t Buffer
Receive Buffer A
Receive Buffer B MEBASE

MEBASE + 2H

MEBASE + 400H

~'EBASE + 600H

MEBASE + BOOH

MEBASE + lOOOH

MEBASE + n~OOH l

FIGURE 4-1. ME BUFFER ORGANIZATION 8K BYTES.

ADDRESSES IN HEX

4-1

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Progranwn I ng Memory Allocation

3Com Copoatco

compuler communtcallOn compal,bthly

the ME memory called MEBASE. MEBASE must be aligned on an 8K byte

boundary. The controller partlons fts memory into six regions as

fo II ows: (AI so see FI gure 4-1 ebove .}

1 • Control region (MEBASE)
2. Station address ROM (MEBASE + 400H)
3. Station address RAM (MEBASE + 500H)
4. One 2K byte transmit buffer tMEBASE + 800H)
5. First 2k byte receive buffer (MEBASE + 1000H)
5. Second 2k byte receive buffer (MEBASE + 1800H) Software uses the registers In the control region to manipulate the

controller and read its status. There are two registers In the control

region:

1. MECSR, the control and status register, at MEBASE

2. MEBACK, the retransmission backoff counter, at MEBASE+2.

NOTE: The byte-ordering switch, TRB (See section 5.1) will affect the

ordering of the bytes in both MECSR and MEBACK. If the TRB switch Is OFF, MECSR and MEBACK are as shown In in Figure 4-2. If the TRB switch

51 18/82/TCO~1~·lE4!

4-2

Prograa.ing Memory Allocation

3Com Caporation

'COmputer commumcahon compatlblilty

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Is ON the bytes of MECSR and MEBACK are reversed. See Figure 4-2 below.

The statIon address ROM, at MEBASE+400H, hOlds the sIx byte statIon

address of the controller. The address recognItion cIrcuitry uses the

station address RAM, at MEBASE+600H, to compare the destInation address

of packets from the ether when decidIng whether to accept a packet.

Software myst write the statton address Into the RAM and ·g!~eW the

address to the controller by writing one into AMSW. Any further

~

references to the address memory are Ignored until reset.

'------- TINTEN

~ AINTEN

I I

II

1...-------- BINTEN

L..- reset (reads as zero)

..._---------, not used

'------------, RBBA state of A when B arrives

L..- AMSW 1 => belongs to

Ether '------::----------- ·JAf.1, wrltln!; 1 clears jam '---------------- TBSW 1 => belongs Ito Ether

'-- ABS~I 1 => belongs to

Ether

L..- BBSW 1 => belongs to

Ether

FIGURE 4-2. MECSR=MEBASE. THE MUlTIBUS ETHERNET CONTROl AND STATUS REG I STER

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Programml n9 Memory Allocation

3Com Oxpcratm

computer communICatIOn compatibility

4.2 TRANSMIT/RECEIVE

The transmJt buffer starts at MEBASE+8-00H (see Figure 4-0. The first word of the buffer Js MEXHDR, the transmit buffer header, as shown

In in Figure 4-3 below •• To transmit. align the packet In the buffer so

the last byte of the packet coincides with the iast byte of the transmit

buffer. Set up MEXHOR to contain the offset of the first byte of the

packet. Finally. set TBSW to one .... As long as TBSW remains one, the

transmIt buffer is busy and belongs to the controller; (any reference to it is ignored). When TBSW becomes zero, transmission is complete and the

transmit buffer is available to software once again. In the event of a

co!! isfon, the controller sets JAM to one. To retransmIt the packet,

MEXHDR=ME8ASE+800, THE TRANSMIT BUFFER HEADER

offset of fIrst byte

unused

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FIGURE 4-3. MEXHlR=t£BASE+800. llIE TRANSMIT BUFFER

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Progranm I ng TransmIt/ReceIve

t!~~~

f"" software must write the two's complement of the number of slot times to

delay into MEBACK; then write a one back Into JAM. Writing Into MEBACK

when JAM Is not set produces unpredictable results.

The ME provides two buffers to receive packets from the ether.

Software controls these buffers with two bits in MECSR; one for each

buffer. ABSW controls receive buffer A which starts at MEBASE+l000H.

BBS~I controls receive buffer B which.. starts at MEBASE+1800H. (See Figure

4-1 on Page 4-1) To receive a packet In A. set ABSW to one. While ABSW

remains a one, any reference to A will be Ignored. ABSW wll I remain one

as long as the buffer belongs to the control Jer; when ABSW becomes zero

the buffer contains a packet and beiongs to the software. To receive a

packet tn B. the software manipulates BBSW similarly. If both ABSW and BBSW are zero after gIving both receive buffers to the controller. RBBA helps the software decide which buffer has the oldest packet: If RBBA Is

zero. then the packet In A Is older than the packet tn B. If RBBA is one

the packet in B is oider than the packet In A.

The header (first) word of both receive buffers are cal led, MEAHDR

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Progr CiffII1 l fig Transmit/Receive

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computer commurucauon compatIbility

and MEBHDR. see Figure 4-4 below. The received packet minus the preample

starts lmmedlately after the buffer header.

After a packet arrives, the

controller writes a status word In the buffer header. The low order

eleven bits specify the offset of the first free byte after the packet. The high order bits contain various status flags, starting with the sign

bit:

fcs error,

h~~a~-a~+ ~a~~- e~~~~ s+a+l~n 2dn~oss m2+ch 2~~

..... \"I u ...... ::. I, I lI!::fC" I I VI, ., ,,,. ... "'....... "'W' II, Wit'"

PA al lows the software to select which packets the controller will

accept on receive. The controller classifies all packets on the ether,

as follows:

I I I I I I

I i., first free byte

l.__--- fram I ng error

r.1EAHDR=r.1EBASE+l 000, MEBHDR=r.1EBASE+1800 THE A AND BE RECEIVE BUFFER HEADERS

101

'------------------- address match

~---------------------range error

~-------------------------broadcest

~----------------r_----------------fcs error

c

FIGURE 4-4. A AND B RECEIVE BUFFER HEADERS

5/18/82/TCOMME4/

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Progranrnlng TransmIt/ReceIve

3Com Corporatiexl

computer communICatIOn compahbllrty

Ai I

the universe of packets on the ether

Range

runts and oversized packets

FCS

packets with frame check sequence errors

Frame

packets with al ignment errors

Mine packets with destination address = station address

Multi

multicast packets

Broad

broadcast packet

Errors

range+fcs+frame

The software sets PA to receive only selected classes of packets.

" ai i
v
all - errors
2 all - fcs - frame
3 mine + multi
4 mine + multi - errors
5 mine + muiti - fcs - frame
6 mine + broad
7 mine + broad - errors
8 mine + broad - fcs - frame I

Jumpers on the board select a single Interrupt level for the ME

controller. Setting JINTEN enables Interrupts when JAM Is set. Setting

TINTEN enables Interrupts when TBSW Is zero. Setting AINTEN and BINTEN

enables Interrupts when ABSW and BBSW are zero respectively. The ME

interrupts whenever any of the masked bits meet the conditions stated

5/18/82/TCOMtw1E4/

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Programm f ng TransmIt/Receive

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computer communICatIon compatibIlity

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above; in particular, Interrupts are not edge triggered, but level

triggered. An Interrupt routine should not leave an Interrupt enabled

unless it turns around the buffer that caused the interrupt. If the

interrupt routine does not turn around the associated buffer and leaves

the interrupt enabled, the controller wi I I immediately retnterrupt as

soon interrupt routine completes.

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ProgrammIng AnomalIes

3Com Corpoatco

computer communocatlOn compatibility

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4.3 PROORNt4IN3 ANOMALIES

MECSR and MEBACK are replicated al I through the control region.

There Is no method to read the value of MEBACK. If the software attempts

to read ME8AC~, it wli i read MECSR Instead.

The station address RO~ is the first six bytes of an eight byte

block; this eight byte block is replicated throughout the region.

The station address RAM is the first sIx bytes of an eight byte

block; this eight byte biock is repi icated throughout the region.

The Interrupt enables for the transmit or receive buffers must NOT

be set until that buffer has been assigned to the Ether. Enabling the

interrupts before that time will result In an immediate interrupt going

to the processor. Part of the Interrupt service routine must Include

disabling the Interrupt enables; otherwise, the processor will stay

Interrupted. The JAM interrupt can be left in the enabled state as long

as desired.

I NOTE:The packet stored into the packet buffer by the

.

processor does not Include the preamble or FCS, but does

include the Ethernet data I Ink layer header fields

(destination address, source address, and type field) along

with the data. Since the maximum legal packet sIze on the

~i 18/C2/TCOMME4! 4-9

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Progranm i ng Anomalies

3eam CcrporatOO

computer .:.ommunocahon compallbtllty

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Ethernet is 1514 (excluding the frame check sequence (FCS)

field), at least 532 bytes of each transmit packet buffer

will always be unused. Conversely, since the minimum legal

packet size is 60 bytes (again excluding the FCS field), at

most 1986 bytes of each transmit packet will be left unused.

It 15 the responsibl I lty of the driver software to insure

tnat minimum and maximum packet size requirements ere

observed.

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4-10

Programm I ng Operation

3Com Corporation

computer communICatIOn compabbthty

4.4 OPEP.A T! ON

The transmitter and receiver operate Independently, giving the

programmer the illusion that the Ethernet Is a full-duplex device. In

fact, only one packet may exist on the coaxial cable at a time.

Whenever the Ethernet channei is nOT in use, the packet suppi jed to

the transmitter Is transmitted a~ quickly as possible. The ME hardware

separates packets by the minimum packet spacing (9.6 - 10.2

microseconds).

Whenever a packet appears on the Ethernet, (except while

transmitting) It is read into a buffer previously supplied to the

receiver.

One aspect of the transmit process, the binary exponential backoff

algorithm, is implemented by the ME hardware and requires software

support only for random number generation. When the controller detects a

collision it sets the JAM bit in the transmit control register which

causes a 32-bit jam signal to be transmitted and, If the JINTEN bit Is

set, an Interrupt occurs. The software must store a random number into I

theMEBACK register to cause a delay (back off) of the J ropriate time

after a collision. After the delay, the same packet Is retransmitted.

If a collision happens again, the cycle repeats.

The delay time is an Integral multiple of a slot time (512 bit-times

4-11

Programm I n9 Operation

3Com Corpa-ation

computer communIcatIon compatibtllty

or 51.2 microseconds). The Integral multiple is chosen as a uniformly

distributed random Integer greater than or equal to zero and less than 2k

(2 to the k1h power), where k is either the number of retransmission

attempts for the packet being transmitted or 10, whichever Is less. This

algorithm doubles the mean of the delay time each time a col I Ision

occurs, ensuring the stability of the Ethernet even under extreme

loading.

If the number of retransmission attempts exceeds 15 (probably a

I l

transmission subsystem malfunction), an error should be reported.

The processor overhead to support backoff in software is minimal.

Studies show that Ethernet packets typically experience col I isions less

than 0.03% of the time.

5/18/82/TCOMr.1E.1/

4-12

3Corn Corporatial

~Ier communiCation cornpal,bllily

Installation Checklist

CHAPTER 5

INSTALLATION AND CONFIGURATION CONSIDERATIONS

5.1 INSTALLATION CHECKLIST

BEFORE OPENING THE SHIPPING GARTON. Inspect it for damage or water

s+atns, if so.

Write a brief description of the damage on the bill of

lading, and

Request that the carrier's agent be present when the carton

Is opened.

Save the carton and packing materials to show the carrier in

case the controller was damaged. The carrier is I iable for

sh i pp i ng damage.

Unpack the ME Controller module gently by removing the foam packing

material.

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aCom Corporatial I nsta II atl on

computer communlcaloon compatIbIlity Check list

Ver.lfy that all components are present. (See Figure 5-1 below.)

One PC Board

One Cable

FIGURE 5-1. M: CONTROlLER PARTS

~:/: b/::-:C/TCO~1ME5/

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computer commun,ca!Ion compatIbIlity.

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Installation Check I 1st

t.oce+e the byte ordering switch labeled TRB. see legend in FIgure

5-2 below.

The byte ordering switch is configured at the factory to address

high-order bytes first, like the Motorola 68000 microprocessor. If

the ME Controller is going to be operated by a processor that

addresses bytes In the reverse order (low-order first I ike the

Intel 8086 microprocessor) turn the switch to the ON position.

locate I/O-Memory jumpers (labeled MRDC,MWTC,IORC,IOWC). (See

Legend in Figure 5-2)~ To configure the ME Controller on the

memory side, connect the memory jumpers I abe I ed ~1RDC and MWTC. To

Jumpers

FIGURE 5-2. tE CONTROLLER BOARD LEGEND

5/18/82/TCOf,:''<::S/

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3eom Corporatim

Installation Check I 1st

COmpuler commun,cahon compallb,hty

configure the ME COntroller on the I/O stde~ connect the I/O

jumpers, 10RC and 10~/C.

Locate the address switches labeled ADR13/ and ADR17/. (See

Figures 5-2, 5-3, 5-4). The switches iabeied ADRi3/ specify the

most significant bit for 20-bit addressing. Switch ADR17;

specifIes the most significant bit for 24-bit addressing. If the factory default settings (80000H) are satisfactory, go the next

step, otherwise change the switch settings to meet your specific

needs.

Locate the interrupt jumpers labeled INTERRUPTS. (See Figures 5-2,

5-3). Set the interrupt switches to the interrupt level desired:

From O=highe5t, to 7=lo.e5t.

(Installation procedures continued after figures and tables on fol lowing

pages. )

5/18/82/TCOMt-.1E'!

5-4

.~,- -------

Installation Oleckllst

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FIGURE 5-3. AOORESS SWITCHES ADR13/ TO ADROD/ AND TRB SWITCH

(Also see Ffgure 5-4.)

--~-~--. -- .- ..... __ .-

5/1S/82/TCOMME5/

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~: communocatlon compiltlbility

Installation Checklist

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FIGURE 5-4. ADDRESS SWITCHES ADR17/ TO ADR14/

(Also see Figure 5-3.)

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Description. Switches

Buffer Memory Base Address

Byte ordering

Description. Jumpers

24-bit Addressing

20-bit Addressing

Memory Configuration

24-blt Addressing

20-blt Addressing

16-bit Addressing

5/18/82!TCOMME5/

Installation Check I 1st

TABLE OF SWITCH AM) JUMPER SETIIOOS

r" __ .a.. __ ..... n_~'"!:!l.1 I + ..-CR.IVI J .., .... u ....

c:: .. t+,.h t.J2mb

.... ••• 'W ..... _ ......

80000 H

..

~'emory ADR17/ -ADROD/ TRB

OFF

(Most significant byte at EVEN address)

e.g. UNLIKE the 8086!

Factory Default

Jumper Name

Inserted

JPl

Inserted

JP2

JPl

JP2

Inserted

Inserted

Out

. Inserted

Out

Out

5-7

3Com Ccrporaticn

InstallatIon Checklist

computer communication compatlbtllty

Turn the DC power to the backplane OFF.

Plug the serial cable suppl led Into the 14-pin connector on the

back edge of the ME. The Notched Position of the Seriai Cabie

14-pin leader has "component-side" orientation.

Plug the Multibus board into the Multibus backplane.

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Plug the Ethernet transceiver cable (not supplied) Into the

subminiature - 0 end of the serlai cable.

Attach the lug at the end of the pigtail on the serial cable (near

the board) to any convenient ~g~~ ground. PROPER GROUNDING !S

CRITICAL TO THE PROPER OPERATION OF THE ETHERNET.

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5.2 ETHERNET ADDRESS CONSIDERATIONS

Each station on an Ethernet has a 48-blt Ethernet address associated

with It that is unique across all Ethernets In the universe. The station

address is assigned by the manufacturer of the station. For stations

assembied from components from muitipie manufacturers, the assignment of

Ethernet addresses is ambiguous. T~is section describes the conventions

to be fol lowed to maintain unique Ethernet addresses under various

configurations of components.

Each ME Controller manufactured by 3Com is shipped with a unique

Ethernet address. The address Is contained In a special address

recognition PROM, and Is also printed on the PC board in Indel ible Ink.

For stations that contain only a single ME Controller, the station

address is the one suppl led with the ME Controller. For stations that

contain multiple ME Controllers, such as gateways, one of the controllers

should be arbitrarily selected to contribute its Ethernet address as the

station address. The hardware address recognition in the station must be

programmed to respond to the chosen Ethernet address in al I the ME

Controllers attached.

It may become necessary 'In order to analyze a hardware problem to

swap boards between stat ions at a user site. I n that case It is the

user's option either to have the Ethernet address to follow the board, or

to disassociate the board from the address in software. The advantage of the former Is that the address recognized always matches the address

5/18/82/TCO~lME5/

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~ter communoeatlOn compatibility

Installation Ethernet Address COnsiderations

printed on at least one of the controllers in the station. The advantage of the latter Is the abll ity to swap hardware around without changing any

station name/station address directory entries for the network.

If a board is sent back to the factory for repair, the board that

comes back may not have the same Ethernet address printed on ft. The

customer has the option of using either the new Ethernet address or the

old. 80th addresses are al located to the customer and are under the

customer's control.

I It Is the cus+omer ' S raspons i b 1 i Ity TO manage the e l located Ethernet
addresses. Addresses be assigned in long
( can any manner as as none are
dup I i cated on more than one station. The recommended practice is to add each t~ Controller Ethernet address to a site-wide pool of addresses

maintained independently of the hardware. That way, ME hardware can be

moved around among stations or sent back to 3Com for repair without

affecting any software.

5/18/B2/TCO~1ME51

5-10

7/21/82

This is an addendum to the

Model 3C400

MULTIBUS Ethernet (ME) Controller

Reference Manual

of

May 18, 1982

CORRECTIONS:

Page 4-6: The "address match" sta..tus bit is inverted. In other words, the bit is 0 if the destination address of the received packet is equal to the station address, and 1 if it is not.

Page 4-6: The "broadcast" status bit is also inverted. In other words, the bit is 0 if the the destination address is the broadcast address (all ones), and 1 if it is not.

CLARIFICATIOr~S ;

Page 4-5: The JAM bit is cleared by setting it (writing a one into the JAM bit).

Page 4-5: The TBSW bit remains 1 during all JAM processing. It does not become 0 again until the packet has been successfully transmitted.

Page 4-6: There is no status bit indicating a multicast packet which is not a broadcast packet. Such a packet is identified by a broadcast status bit equal to 1 (false) and the multicast bit in the destination address being 1 (true). Multicast packets will only appear in receive buffers if the receiver is enabled to accept them.

Page 4-7: Broadcast is a special case of multicast. Enabling the receiver for multicast (modes 3,4,5) includes the .broadcast address.

Page 4-7: The multicast bit of the destination least significant (low ord~r) bit of the packet. In a receive buffer, this is the following the buffer header word.

f

address is the

first byte of the byte immediately

Page 4-12: The number of retransmissions normally exceeds 15 only when the Ethernet is broken. When this occurs the only way to get the ME to return the transmit buffer to the processor is to reset the controller by setting bit 8 of MECSR.