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Assignment New
Assignment New
By
Devanshu Kaushik (2008A8PS236G)
22 October 2010
Cadence Tool Simulation
Shown below is the schematic I used for the Large Signal Analysis of a
common source amplifier with source degeneration:-
After the circuit is established and drawn as a schematic, I then
proceeded to the Analog Design Environment (ADE) to plot the
various graphs (using DC analysis) shown below:-
1. Id v/s Vin:-