Problem Solutions to Problems Marked With a * in

Logic Computer Design Fundamentals, Ed. 2

CHAPTER 4
© 2000 by Prentice-Hall, Inc.

4-3. (All simulations performed using Xilinx Foundation Series software.)

4-4.
D
R Q

C
S Q

4-5.
S
C Q

Q
R

4-6.

Q
Reset Complement Set No Change
J=0 , K=1 J=1 , K=1 J=1 , K=0 J=0 , K=0

1
 Problem Solutions – Chapter 4

4-10.
J K Q(t) Q(t+1) S R Q(t) Q(t+1) D Q(t) Q(t+1) T Q(t) Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 1 1 0 1 0 0 1 1
0 1 0 0 0 1 0 0 1 0 1 1 0 1
0 1 1 0 0 1 1 0 1 1 1 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 X Q (t + 1 ) = D Q(t + 1) = T ⊕ Q
1 1 1 0 1 1 1 X
JA = B KA = BX
JB = X KB = AX + AX
Q ( t + 1 ) = JQ + KQ Q ( t + 1 ) = S + RQ

A(t+1) = JAA + KAA = BA+ BA +XA

B(t+1) = JBB + KBB = X B + ABX + ABX

4-12.
Present state Input Next state X=0

000 100 110 011

A B C X A B B
0 0 0 0 1 0 0
0 0 0 1 0 0 0 111
001 010 101
0 0 1 0 0 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 1 0 1 X=1
0 1 1 0 1 0 1
0 1 1 1 0 0 1 001 100 010 101
1 0 0 0 1 1 0
1 0 0 1 0 1 0
000
1 0 1 0 0 1 0 011 111 110
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 0 1 1 1 1 State diagram is the combination of the above two diagrams.
1 1 1 0 1 1 1
1 1 1 1 0 1 1

4-17.
1/1
Present state Input Next state Output 0/0
0 1
A B X A B Y
0 0 0 0 1 0 0/1
0/1 1/0
0 0 1 0 0 1
1/0
0 1 0 1 0 1
0 1 1 1 1 0 2 3
1 0 0 0 0 1 1/1
0/0
1 0 1 0 1 0
1 1 0 1 1 0
Format: X/Y
1 1 1 1 0 1

2
 Problem Solutions – Chapter 4

4-19.
DA B DB B
Present state Input Next state
1 1
A B X A B
A 1 1 1 A 1 1 1
0 0 0 0 0
0 0 1 1 0 X X
0 1 0 0 1
DA = AB + AX + BX D B = AX + BX
0 1 1 0 0
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 0 1

4-20.
Format: XY/Z (x = unspecified)

Present state Inputs Next state Output x1/x

00/0 00/1
x1/x 10/0
Q(t) X Y Q(t+1) Z 0 1
0 0 0 0 0
0 0 1 0 X 10/1
0 1 0 1 1
0 1 1 0 X
1 0 0 1 1
1 0 1 0 X
1 1 0 1 0
1 1 1 0 X

4-24.
DA B DB B Y B
Present state Input Next state Output
1 1 1 1 1 1
A B X A B Y
A 1 1 1 A 1 A
0 0 0 0 1 1
0 0 1 0 0 1 X X X
0 1 0 0 1 0
DA = AX + BX DB = BX + A X Y=AB
0 1 1 1 1 0
1 0 0 1 0 0
1 0 1 0 0 0
1 1 0 1 0 0
1 1 1 1 1 0

4-25.
DA J
Present state Input Next state
1 1
A J K A
A 1 1
0 0 0 0
0 0 1 0 K
0 1 0 1
DA = AJ+ AK
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

3
 Problem Solutions – Chapter 4

4-30.

Present state Input Next state FF Inputs JA = BX

A B X A B JA KA JB KB KA = B X + B X
0 0 0 0 1 0 X 1 X JB = A X
0 0 1 0 0 0 X 0 X KB = A X
0 1 0 0 1 0 X X 0
0 1 1 1 1 1 X X 0
1 0 0 1 0 X 1 0 X
1 0 1 0 0 X 1 0 X
1 1 0 1 0 X 0 X 1
1 1 1 1 1 X 0 X 0

4-33.

Present state Inputs Next state FF Inputs

JA = E(BX + B X)
A B E X A B JA KA JB KB
0 0 0 0 0 0 0 X 0 X K A = E(BX + B X)
0 0 0 1 0 0 0 X 0 X
0 0 1 0 1 1 1 X 1 X JB = E
0 0 1 1 0 1 0 X 1 X
0 1 0 0 0 1 0 X X 0 KB = E
0 1 0 1 0 1 0 X X 0
0 1 1 0 0 0 0 X X 1
0 1 1 1 1 0 1 X X 1
1 0 0 0 1 0 X 0 0 X
1 0 0 1 1 0 X 0 0 X
1 0 1 0 0 1 X 1 1 X
1 0 1 1 1 1 X 0 1 X
1 1 0 0 1 1 X 0 X 0
1 1 0 1 1 1 X 0 X 0
1 1 1 0 1 0 X 0 X 1
1 1 1 1 0 0 X 1 X 1

4-36.
TA = ABX + ABX
Present state Input Next state FF Inputs TB = ABX + ABX + BX
A B X A B TA TB
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 1 0 1 1 T A

0 1 1 0 1 0 0 C A
1 0 0 1 0 0 0 X
1 0 1 1 1 0 1
1 1 0 1 1 0 0
1 1 1 0 0 1 1
T B

C B

Clock

4
 Problem Solutions – Chapter 4

4-37
library IEEE; architecture mux_4to1_arch of mux_4to1 is
use IEEE.std_logic_1164.all; begin

entity mux_4to1 is process (S, D)

port ( begin
S: in STD_LOGIC_VECTOR (1 downto 0); case S is
D: in STD_LOGIC_VECTOR (3 downto when "00" => Y <= D(0);
0); when "01" => Y <= D(1);
Y: out STD_LOGIC when "10" => Y <= D(2);
); when "11" => Y <= D(3);
end mux_4to1; when others => null;
end case;
-- (continued in the next column)
end process;
end mux_4to1_arch;

4-40.
library IEEE; case J is
use IEEE.std_logic_1164.all; when '0' =>
entity jkff is if K = '1' then
port ( q_out <= '0';
J,K,CLK: in STD_LOGIC; end if;
Q: out STD_LOGIC when '1' =>
); if K = '0' then
end jkff; q_out <= '1';
else
architecture jkff_arch of jkff is q_out <= not q_out;
signal q_out: std_logic; end if;
begin when others => null;
end case;
state_register: process (CLK) end if;
begin end process;
if CLK'event and CLK='0' then --CLK falling edge
Q <= q_out;
-- (continued in the next column) end jkff_arch;

4-45.
module problem_4_45 (S, D, Y) ; always @(S or D)
begin
input [1:0] S ;
input [3:0] D ; if (S == 2'b00) Y <= D[0];
output Y; else if (S == 2'b01) Y <= D[1];
reg Y ; else if (S == 2'b10) Y <= D[2];
else Y <= D[3];
// (continued in the next column)
end
endmodule

5
 Problem Solutions – Chapter 4

4-47.
module JK_FF (J, K, CLK, Q) ; always @(negedge CLK)
case (J)
input J, K, CLK ; 0'b0: Q <= K ? 0: Q;
output Q; 1'b1: Q <= K ? ~Q: 1;
reg Q; endcase
endmodule
// (continued in the next column)