1 2 3 4 5 6 7 8

VCC5V

VCC33
C12 C13
100n 10u/16V

C3 C4 C5 C6 C19 VCC33 VCC5V

U2 100n 100n 100n 100n 10u/16V
VCC5V J4
6 28
PB3/MISO SO Vdd
7 25 1
PB2/MOSI SI Vddosc L1
8 20 2
PB1/SCK SCK Vddpll Ferrite Bead P1
19 3
Vddrx R4 270R 10k
A 4 15 4 A
PD0/INT0 #INT Vddtx PB7
5
CN1 PB6
5 27 1 6
PD1/INT1 #WOL LEDA R5 270R P1 PB5
26 7
LEDB AD0
9 7 8
PB4 #CS P7 AD1
10 9
#Reset AD2
17 2 10
R2 TPOUT+ P2 AD3
16 C10 TX (1:1) 11
VCC33 TPOUT- R6 50R AD4
12
10k AD5
13 3 RX (1:1) 13
PD2 TPIN+ R7 50R P3 AD6
12 100n VCC5V 14
R3 TPIN- AD7
8
VCC33 TP1 P8
LCD
10k R14 10R J1
1 6
Vcap P6
C7 C9 LED Backlight
10u/16V C11
R8 50R
3 22 4 VCC33
CLKout Vssosc P4
18p 23 21
OSC1 Vsspll R9 50R J2
X1 24 18 100n
OSC2 Vsstx
25MHz 11 L1 C20 1
Vssrx L1 PB7
C8 14 2 L2 Green 100n 2
Rbias Vss L2
U8 3
PB6
ENC28J60 L3 1 14 4
L3 PB4 OE1 VCC
18p L4 Yellow 4 5
R1 L4 OE2 PB5
10 6
2k3 OE3
J5 G1 13 7
G1 Frame OE4 PB4
1 G2 VCC5V 8
PB1/SCK G2 R11 180R
2 RJ45 MM-Jack 2 3 9
B PB2/MOSI PB3/MISO A1 Y1 B
3 5 6 10
PB3/MISO PD1/INT1 A2 Y2 R12 180R
4 9 8 11
PB4 PD0/INT0 A3 Y3 PB2/MOSI
5 C14 12 11 12
PD0/INT0 A4 Y4 R13 180R
6 VCC5V VCC33 100n 13
Port Usage: PD1/INT1 PB1/SCK
7 7 14
PD2 External Power GND
8 U3 15
PB0 -> Memory bank selection (128k mode)VCC33 JP2 PB0
9 20 28 74LVT125 16
PB1/SCK -> ENC28J60, pin 8 (SCK) #CS0 CE VCC
10 22 17
PB2/MOSI -> ENC28J60, pin 7 (SI) #RD OE PD3
U1 LM1117-3.3 27 18
PB3/MISO -> ENC28J60, pin 6 (SO) #WR WE
IDC 10-PIN 3 2,4 19
PB4 -> ENC28J60, pin 9 (/CS) IN OUT PD2
10 11 20
PB5 -> LCD (E) ADJ A0 A0 DQ0 AD0
9 12 21
PB6 -> LCD (R/W) A1 A1 DQ1 AD1
C1 C2 8 13 22
PB7 -> LCD (RS) 1 A2 A2 DQ2 AD2
100n 100n 7 15 23
A3 A3 DQ3 AD3
6 16 24
PD0/INT0 -> ENC28J60, pin 4 (/INT) A4 A4 DQ4 AD4
5 17 25
PD1/INT1 -> ENC28J60, pin 5 (/WOL) A5 A5 DQ5 AD5 PD5
4 18 26
PD2 -> ENC28J60, pin 10 (/RESET) A6 A6 DQ6 AD6 PD4
3 19
PD3 A7 A7 DQ7 AD7
25 VCC5V To VFD connector
PD4 A8 A8
24
PD5 #RESET A9 A9
21
A10 A10
23
A11 A11
B1 2 C15
External Power (JP2): A12 A12
Reset 26 100n
A13 A13
1 U5
This one is used when the ethernet-part of the A14 A14
1 20
board is connected via header J5 and the host OE VCC
14 11
system uses 3.3V. The regulator should not be GND ALE LE J3
C used in this case. C
Bank 0 (32k x 8) 2 19 1
AD0 D1 Q1 A0 AD0
3 18 2
AD1 D2 Q2 A1 A8
VCC5V VCC5V VCC5V 4 17 3
AD2 D3 Q3 A2 AD1
5 16 4
AD3 D4 Q4 A3 A9
6 15 5
AD4 D5 Q5 A4 AD2
C18 7 14 6
AD5 D6 Q6 A5 A10
U7 100n C16 8 13 7
AD6 D7 Q7 A6 AD3
VCC5V 22 32 100n 9 12 8
#E1 Vcc AD7 D8 Q8 A7 A11
14 30 9
VCC E2 AD4
29 U4 10 10
U6C #WR #W GND A12
24 20 28 11
#RD #G #CS1 CE VCC AD5
22 74HC573 12
5 6 #RD OE A13
AY 12 13 27 13
A0 A0 DQ0 AD0 #WR WE AD6
11 14 14
A1 A1 DQ1 AD1 A14
74HC04 10 15 10 11 15
7 A2 A2 DQ2 AD2 A0 A0 DQ0 AD0 AD7
GND 9 17 9 12 #CS1 16
U6D A3 A3 DQ3 AD3 A1 A1 DQ1 AD1 A15
8 18 8 13 17
A4 A4 DQ4 AD4 A2 A2 DQ2 AD2 U6B U6A #WR
7 19 7 15 18
9 8 A5 A5 DQ5 AD5 A3 A3 DQ3 AD3 #RESET
6 20 6 16 19
A6 A6 DQ6 AD6 A4 A4 DQ4 AD4 4 3 2 1 #RD
5 21 5 17 #CS0 A15 20
A7 A7 DQ7 AD7 A5 A5 DQ5 AD5
74HC04 27 4 18 21
A8 A8 A6 A6 DQ6 AD6 ALE
26 3 19 74HC04 74HC04 22
U6E A9 A9 A7 A7 DQ7 AD7
23 25 23
A10 A10 A8 A8 VCC5V PG5
25 24 24
11 10 A11 A11 A9 A9
4 21 VCC5V 25
A12 A12 A10 A10 C17
28 23 26
A13 A13 A11 A11 100n
74HC04 3 2
A14 A14 A12 A12
D U6F 31 26 To Expansion connector D
A15 A15 A13 A13
2 16 1
A16 GND A14 A14 Memory options:
13 12
M68AF127B 14
GND 32k: Use U3 only
Title
74HC04 Bank 1 (32k x 8)
64k: Use U3 and U4 OR U7 (only lower half will be used, ATmega128 board expansion
R10 JP1 don't short JP1)
Size Number Revision
PB0
10k Enable 128k BS 2 x 64k: Use U7 only, short JP1 A3 R1A
Short to use PG5 as bank selector (Use PB0 to select memory page)
Date: 2/5/2008 Sheet of
File: F:\Work\..\AddOn.SchDoc Drawn By:
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