32 bit Lossless Data Compression

BY

SAIKUMAR REDDY (07261A0466)

SWAROOP KUMAR(07261A0470)
VISHNU PRASAD(07261A0480)

GUIDED BY

Mrs.Subhashini
Objective:

 To design a lossless parallel data

compression system which operates in high-
speed to achieve high compression rate.

 By using parallel architecture of

compressors, the data compression rates
are significantly improved. Also inherent
scalability of parallel architecture is possible.
ABSTRACT:

 A 32-BIT system with distributed memory architecture is

based on having multiple data compression and
decompression engines working independently on
different data at the same time. This data is stored in
memory distributed to each processor.

 The main parts of the system are the two Xmatchpro

based data compressors in parallel and control blocks
providing control signals for the data compressors,
allowing appropriate control of the routing of data into and
from the system.
 Each Data compressor can process four bytes of data
into and from a block of data every clock cycle.

 The data entering the system needs to be clocked

in at a rate of 4n bytes every clock cycle, where n is
the number of compressors in the system. This is to
ensure that adequate data is present for all compressors
to process rather than being in an idle state.
BLOCK DIAGRAM:
FEASIBILITY:
SOFTWARE USED:

The project is to be implemented using

VHDL language and to be simulated and
synthesized using xilinx9.2I.
APPLICATIONS:

 Computer systems. 
 Networking products. 
 High performance storage devices. 
 Data logging equipment. 
 Remote sensing applications. 
ORGANIZATION:

CHINMAYA MICRO SYSTEMS (P)LTD

Innovation starts here….
THANK YOU