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    This document provides an overview of CISC and RISC architectures. CISC uses complex instructions that perform multiple operations and take multiple clock cycles to execute, while RISC uses a reduced instruction set with simpler instructions that execute in one clock cycle. RISC incorporates pipelining to process multiple instructions simultaneously and improve performance. Key differences are that CISC instructions can directly reference memory while RISC only allows load and store, and RISC uses more general purpose registers than CISC.

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    RISC - Derek Ng

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    This document provides an overview of CISC and RISC architectures. CISC uses complex instructions that perform multiple operations and take multiple clock cycles to execute, while RISC uses a reduced instruction set with simpler instructions that execute in one clock cycle. RISC incorporates pipelining to process multiple instructions simultaneously and improve performance. Key differences are that CISC instructions can directly reference memory while RISC only allows load and store, and RISC uses more general purpose registers than CISC.

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    21 views12 pages

    RISC - Derek NG

    Uploaded by

    sharzeenpatel
    This document provides an overview of CISC and RISC architectures. CISC uses complex instructions that perform multiple operations and take multiple clock cycles to execute, while RISC uses a reduced instruction set with simpler instructions that execute in one clock cycle. RISC incorporates pipelining to process multiple instructions simultaneously and improve performance. Key differences are that CISC instructions can directly reference memory while RISC only allows load and store, and RISC uses more general purpose registers than CISC.

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    of 12

    RISC / CISC

    Architecture

    by Derek Ng
    Overview
     CISC Architecture
     RISC Architecture
     Pipelining
     RISC vs CISC
    What is CISC
     Complex Instruction Set Computer
     “High level” Instruction Set
    Executes several “low level operations”
    Ex: load, arithmetic operation, memory
    store
    Features of CISC
     Instructions can operate directly on
    memory
     Small number of general purpose registers
     Instructions take multiple clocks to execute
     Few lines of code per operation
    What is RISC?
     Reduced Instruction Set Computer
     RISC is a CPU design that recognizes
    only a limited number of instructions
    Simple instructions
    Instructions are executed quickly
    Features of RISC
     “Reduced” instruction set
     Executes a series of simple instruction instead of a
    complex instruction
     Instructions are executed within one clock cycle
     Incorporates a large number of general registers for
    arithmetic operations to avoid storing variables on a
    stack in memory
     Only the load and store instructions operate directly
    onto memory
     Pipelining = speed
    Quick Performance
    Pipelining
     “Assembly Line”
     Technique to process multiple instructions
    at the same time
     Allows instructions to be executed
    efficiently
    Stages of Pipelining
     Fetch instructions from memory
     Decode the instruction
     Execute the instruction or calculate an
    address
     Access an operand in data memory
     Write the result into a register
    Pipelining Example
    CISC vs RISC
    CISC RISC

    Complex instructions require Reduced instructions take 1


    multiple cycles cycle

    Many instructions can reference Only Load and Store instructions


    memory can reference memory

    Instructions are executed one at Uses pipelining to execute


    a time instructions

    Few general registers Many general registers


    References
     http://cse.stanford.edu/class/sophomore-
    college/projects-00/risc/
     http://en.wikipedia.org/wiki/Complex_instruction_set_co
    mputer
     http://en.wikipedia.org/wiki/RISC
     http://arstechnica.com/articles/paedia/cpu/pipelining-
    1.ars/4

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