Behavioral

Loops
(Algorithmic)
Processes

RTL
Functional
Boolean

Gate
Structural
Switch

Figure 9-01
 Register Gate-level
transfer level netlist

Logic Place-and-
RTL Synthesis Route

Logic Logic
Simulator Simulator

RTL functional Gate-level functional

verification verification

Figure 9-02
 Register Gate-level
transfer level netlist
Mapping
Logic Packing
RTL Synthesis Place-and-
Route

Logic Logic
Simulator Simulator

RTL functional Gate-level functional

verification verification

Figure 9-03
 Graphical State Diagram Textual HDL

When clock rises

If (s == 0)
then y = (a & b) | c;
else y = c & !(d ^ e);

Top-level
block-level
schematic

Graphical Flowchart Block-level schematic

Figure 9-04
 System

Behavioral
(Algorithmic)

Functional

Verilog
(RTL,
Boolean)

Structural
(Gate, Switch)

Figure 9-05
 System

Behavioral
(Algorithmic)

VHDL
Functional

Verilog
(RTL,
Boolean)

Structural VITAL
(Gate, Switch)

- Relatively easy to learn - Relatively difficult to learn

- Fixed data types
- Interpreted constructs
- Good gate-level timing
- Limited design reusability
- Limited design management
- No structure replication
- Abstract data types
- Compiled constructs
- Less good gate-level timing
- Good design reusability
- Good design management
- Supports structure replication

Figure 9-06
 if SEL == “00“ then Y = A;
elseif SEL == “01“ then Y = B;
elseif SEL == “10“ then Y = C;
else Y = D;
end if;

2:1 MUX
D 2:1 MUX
2:1 MUX
C
B Y
A
SEL == 10
SEL == 01
SEL == 00

Figure 9-07
 4:1 MUX
case SEL of;
A 00
“00“: Y = A;
“01“: Y = B; B 01
Y
“10“: Y = C; C 10
otherwise: Y = D; D 11
end case;

SEL

Figure 9-08
 if (B > C)
then Y = A + B;
else Y = A + C;
end if;
Resource Resource
Sharing = ON Sharing = OFF

A +
B
B + Y

C
+
Y
C

> >
Total LUTs = 32 Total LUTs = 64
Clock frequency = 87.7 MHz Clock frequency = 133.3 MHz (+52% !)

Figure 9-09