Al-Quds University

Faculty of Engineering
Digital Logic Systems I (0701341)
January 24, 2002 Second Exam Time : One Hour

Q1) A majority gate is a digital circuit whose output is logic 1 if the

majority of the inputs are logic 1, otherwise the output is logic 0.
Design the logic circuit for a 3-input majority gate.
[25%]

Q2) Design a combinational logic circuit with four input lines that
represent a decimal digit in BCD and four output lines that generate
the 9 's complement of the input digit. Provide a fifth output that
detects an error in the input BCD number. This output should equal
to logic 1 when the four inputs have one of the unused combinations
of the BCD code. Use minimum number of logic gates in your
design.
[25%]

Q3) Design a logic circuit that multiples two 3-bit binary numbers,
a2a1a0 and b2b1b0 to produce 6-bit product, c5c4c3c2c1c0 . Use AND
gates and Full-adders.
[25%]

Q4) Consider the following block diagram of a 2-to-4-line decoder with

active low enable input and active low outputs.

DO
x D1
2-to-4
y D2
Decoder
D3

Enable

a) Construct the truth table of this decoder

b) Draw the logic diagram of this decoder
c) Show how you can use this decoder in addition to external logic
gate(s) to implement the half adder circuit.
[25%]

Good Luck