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MCP41XXX/42XXX: Single/Dual Digital Potentiometer With SPI Interface
MCP41XXX/42XXX: Single/Dual Digital Potentiometer With SPI Interface
SI 3 12 SHDN
VSS 4 11 RS
PB1 5 10 PB0
PW1 6 9 PW0
PA1 7 8 PA0
AC TIMING CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C.
tCSH
CS
tCSSR 1/FCLK tCHS
tCSO tHI tLO tCS1
SCK
tSU
tHD
SI msb in
tDO
CS
tRSCS
tRS
RS
tS
±1%
±1% Error Band
VOUT
tCSL
CS
tSE
tRS
RS
tSE
tSH
SHDN
1 14
VDD = +3V to +5V
Normalized Resistance (Ω)
12 RAB
0.5 70
Potentiometer INL Error (LSB)
TA = -40°C to +85°C
0.4
Nominal Resistance (kΩ)
FIGURE 2-2: Potentiometer INL Error vs. FIGURE 2-5: Nominal Resistance 50 kΩ
Code. vs. Temperature.
70 140
Potentiometer Mode TempCo
TA = -40°C to +85°C
Nominal Resistance (kΩ)
60 VA = 3V 120
50 RAB
100
(ppm / °C)
40
80 RWB
30 Code = 80h
60
20
40
10
0 20
MCP41100, MCP42100 (100 kΩ potentiometers)
-10 0
0 32 64 96 128 160 192 224 256 -40 -25 -10 5 20 35 50 65 80 95 110 125
Code (Decimal) Temperature (°C)
0.5 280
Refer to Figure 2-27
FIGURE 2-7: Rheostat INL Error vs. FIGURE 2-10: Active Supply Current vs.
Code. Temperature.
3000 1000
TA = -40°C to +85°C, A - VDD = 5.5V, Code = AAh
900
2500
RWB measured 800 C - VDD = 5.5V, Code = FFh
D - VDD = 3.3V, Code = FFh B
2000 700
(ppm / °C)
600
1500
500
1000 400 A
C
300
500 200
0 100
D
0 32 64 96 128 160 192 224 256 0
1k 10k 100k 1M 10M
Code (Decimal) Clock Frequency (Hz)
FIGURE 2-8: Rheostat Mode Tempco vs. FIGURE 2-11: Active Supply Current vs.
Code. Clock Frequency.
1000 1
VDD = 5.5V
RS & SHDN Sink Current (mA)
0
Static Current (nA)
-1
100
-2
-3
10 -4
-5
-6
1
-40 -25 -10 5 20 35 50 65 80 95 11 12 -7
0 5 0 2 4 6
Temperature (°C) RS & SHDN Pin Voltage (V)
FIGURE 2-9: Static Current vs. FIGURE 2-12: Reset & Shutdown Pins
Temperature. Current vs. Voltage.
180
160
MCP41010,MCP42010 CL = 27 pF
Code = 00h,
Number of Occurrences
140
MCP41050, MCP41100, CL = 27 pF
MCP42050, MCP42100
Number of Occurrences
120
Code = 00h, Code = 80h
100 Sample Size = 796
80 VOUT
60
40
20
CS
0
115 117 119 121 123 125 127 129 131 133
Wiper Resistance (Ω)
FIGURE 2-14: 50 kΩ, 100 kΩ Device Wiper FIGURE 2-17: Digital Feed through vs.
Resistance Histogram. Time.
6
Code = FFh
CL = 17 pF 0
Code = 80h
-6
Code = 40h
-12
Code = 20h
-18
VOUT Code = 7Fh Code = 80h
Gain (dB)
Code = 10h
-24
Code = 08h
-30 Code = 04h
-36 Code = 02h
-42
Code = 01h
CS -48
CL = 30pF, Refer to Figure 2-29
-54 MCP41010, MCP42010 (10kΩ potentiometers)
-60
100 1k 10k 100k 1M 10M
Frequency (Hz)
FIGURE 2-15: One Position Settling Time. FIGURE 2-18: Gain vs. Frequency for
10 kΩ Potentiometer.
6 40
Code = FFh VDD = 4.5V to 5.5V,
0 Code = 80h,
Code = 80h 35 10 kΩ Potentiometer
CL = 27 pF,
-6
Code = 40h VA = 4V
-12 30
Code = 20h
Refer to Figure 2-28
-18
PSRR (dB)
25
Gain (dB)
Code = 10h
-24
Code = 08h 20 50 kΩ Potentiometer
-30
Code = 04h
-36 15
Code = 02h
-42 10 100 kΩ Potentiometer
-48 Code = 01h
FIGURE 2-19: Gain vs. Frequency for FIGURE 2-22: Power Supply Rejection
50kΩ Potentiometer. Ratio vs. Frequency.
6 700
Code = FFh MCP41010, MCP42010
0 Iw = 1 mA, Code = 00h,
Code = 80h 600
Code = 10h
-24
-30
Code = 08h
300
Code = 04h
-36 200
Code = 02h
VDD = 5V
-42
Code = 01h 100
-48
CL = 30pF, Refer to Figure 2-29 0
-54
MCP41100, MCP42100 (100kΩ potentiometers)
-60 0 1 2 3 4 5
100 1k 10k 100k 1M
Frequency (Hz) Terminal B Voltage (V)
FIGURE 2-20: Gain vs. Frequency for FIGURE 2-23: 10 kΩ Wiper Resistance vs.
100kΩ Potentiometer. Voltage.
0 450
Code = 00h
400 Refer to Figure 2-27
-6
Wiper Resistance (Ω)
1.06 MHz
350
145 kHz
-12 300 VDD = 2.7V
Gain (dB)
V+ = VDD
1LSB = V+/256
A VDD A
V+ V+
W W
B B
DUT + + V
VMEAS* DUT
- - MEAS*
VIN ~ +
MCP601
2.5V DC
FIGURE 2-27: Wiper Resistance Test Offset
Circuit.
The Reset pin will set all potentiometers to mid-scale 13 SO Data Out for Daisy-Chaining
(Code 80h) if this pin is brought low for at least 150 ns. 14 VDD Power
This pin should not be toggled low when the CS pin is
low. It is possible to toggle this pin when the SHDN pin
is low. In order to minimize power consumption, this pin
has an active pull-up circuit. The performance of this
circuit is shown in Figure 2-12. This pin will draw negli-
gible current at logic level ‘0’ and logic level ‘1’. Do not
leave this pin floating.
RDAC1 RDAC2
D7 D0 D7 D0
RS
Decode
Logic D7 D0
CS
16-bit Shift Register
SCK
SI SO SHDN
FIGURE 4-1: Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and
data register 1 are 8-bit registers allowing 256 positions for each wiper. Standard SPI pins are used with
the addition of the Shutdown (SHDN) and Reset (RS) pins. As shown, reset affects the data register and
wipers, bringing them to mid-scale. Shutdown disconnects the A terminal and connects the wiper to B,
without changing the state of the data registers.
When laying out the circuit for your digital potentiome-
VDD
VDD ter, bypass capacitors should be used. These capaci-
tors should be placed as close as possible to the device
0.1 uF pin. A bypass capacitor value of 0.1 µF is recom-
0.1 uF mended. Digital and analog traces should be separated
MCP4XXXX
A
A
V2
W
W B
B MCP4XXXX
MCP4XXXX Resistor
FIGURE 4-3: Three terminal or voltage
divider mode.
FIGURE 4-2: Two-terminal or rheostat
configuration for the digital potentiometer. Acting In this configuration, the ratio of the internal resistance
as a resistive element in the circuit, resistance is defines the temperature coefficient of the device. The
resistor matching of the RWB resistor to the RAB resistor
controlled by changing the wiper setting.
performs with a typical temperature coefficient of
Using the device in this mode allows control of the total 1 ppm/°C (measured at code 80h). At lower codes, the
resistance between the two nodes. The total measured wiper resistance temperature coefficient will dominate.
resistance would be the least at code 00h, where the Figure 2-3 shows the effect of the wiper. Above the
wiper is tied to the B terminal. The resistance at this lower codes, this figure shows that 70% of the states
code is equal to the wiper resistance, typically 52Ω for will typically have a temperature coefficient of less than
the 10 kΩ MCP4X010 devices, 125Ω for the 50 kΩ 5 ppm/°C. 30% of the states will typically have a
(MCP4X050), and 100 kΩ (MCP4X100) devices. For ppm/°C of less than 1.
the 10 kΩ device, the LSB size would be 39.0625Ω
(assuming 10 kΩ total resistance). The resistance
would then increase with this LSB size until the total
measured resistance at code FFh would be 9985.94Ω.
The wiper will never directly connect to the A terminal
of the resistor stack.
In the 00h state, the total resistance is the wiper resis-
tance. To avoid damage to the internal wiper circuitry in
this configuration, care should be taken to ensure the
current flow never exceeds 1 mA.
For dual devices, the variation of channel-to-channel
matching of the total resistance from A to B is less than
1%. The device-to-device matching, however, can vary
up to 30%. In the rheostat mode, the resistance has a
positive temperature coefficient. The change in wiper-
to-end terminal resistance over temperature is shown
in Figure 2-8. The most variation over temperature will
occur in the first 6% of codes (code 00h to 0Fh) due to
the wiper resistance coefficient affecting the total resis-
tance. The remaining codes are dominated by the total
resistance tempco RAB, typically 800 ppm/°C.
10
R R
V OUT = – V IN ------B- + V REF 1 + ------B-
R R
Absolute Gain (V/V)
A A
Where:
R AB ( 256 – D n ) R AB D n 1
R A = --------------------------------------
- R B = -----------------
-
256 256
R AB = Total Resistance of pot
D n = Wiper setting forD n = 0 to 255 0.1
0 64 128 192 256
FIGURE 4-4: Single-supply, Decimal code (0-255)
-
resistances. Figure 4-10 shows an example calculation
1/2
VSS
B using a 10 kΩ potentiometer.
R PA
V OUT = ( V A – V B ) ------B-
RA
VREF PW
Where:
PB
R AB ( 256 – D n ) R AB D n
RA = --------------------------------------
- RB = -----------------
-
256 256 ( R AB ) ( 256 – D n )
R WA ( D n ) = -------------------------------------------
- + RW
R AB = Total Resistance of pot 256
D n = Wiper setting forDn = 0 to 255
( R AB ) ( D n )
R WB ( D n ) = ---------------------------
- + RW
NOTE: Potentiometer values must be equal 256
Where:
FIGURE 4-7: Single Supply PA is the A terminal
programmable differential amplifier using digital PB is the B terminal
PW is the wiper terminal
potentiometers. RWA is resistance between Terminal A and wiper
RWB is resistance between Terminal B and Wiper
RAB is overall resistance for pot (10 kΩ, 50 kΩ or 100 kΩ)
4.2.3 PROGRAMMABLE OFFSET TRIM RW is wiper resistance
Dn is 8-bit value in data register for pot number n
For applications requiring only a programmable voltage
reference, the circuit in Figure 4-8 can be used. This
circuit shows the device used in the potentiometer FIGURE 4-9: Potentiometer resistances
mode along with two resistors and a buffered output. are a function of code. It should be noted that,
This creates a circuit with a linear relationship between when using these equations for most feedback
voltage-out and programmed code. Resistors R1 and amplifier circuits (see Figure 4-4 and Figure 4-5),
R2 can be used to increase or decrease the output volt- the wiper resistance can be omitted due to the
age step size. The potentiometer in this mode is stable high impedance input of the amplifier.
over temperature. The operation of this circuit over
temperature is shown in Figure 2-3. The worst perfor-
PA Example:
mance over temperature will occur at the lower codes
due to the dominating wiper resistance. R1 and R2 can R = 10 kΩ
10 kΩ PW
also be used to affect the boundary voltages, thereby Code = C0h = 192d
eliminating the use of these lower codes. PB
( R AB ) ( 256 – D n )
VDD R WA ( D n ) = -------------------------------------------
- + RW
256
VDD ( 10k Ω ) ( 256 – 192 )
R1 R WA ( C0h ) = --------------------------------------------------- + 52 Ω
- 256
-IN
MCP41010
R WA ( C0h ) = 2552 Ω
A MCP606
+IN + OUT
( R AB ) ( D n )
B VSS R WB ( D n ) = ---------------------------
- + RW
0.1 uF 256
( 10k Ω ) ( 192 )
R WB ( C0h ) = ----------------------------------- + 52 Ω
R2 256
VSS R WB ( C0h ) = 7552 Ω
FIGURE 4-8: By changing the values of Note: All values shown are typical and
R1 and R2, the voltage output resolution of this actual results will vary.
programmable voltage reference circuit is FIGURE 4-10: Example Resistance
affected. calculations.
† There must always be multiples of 16 clocks while CS is low or commands will abort.
‡ The serial data out pin (SO) is only available on the MCP42XXX device.
* P1 is a ‘don’t care’ bit for the MCP41XXX.
FIGURE 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer.
COMMAND BYTE
X X C1 C0 X X P1* P0
Command Potentiometer
Selection Selection
Bits Bits
SCK
Command Byte Data Byte Command Byte Data Byte Command Byte Data Byte
for Device 3 for Device 3 for Device 2 for Device 2 for Device 1 for Device 1
Command and Data for Device 3 Command and Data for Device 2
First 16 bits shifted out start shifting out after the first 16 clocks start shifting out after the first 32 clocks
will always be zeros
SO X XC C X X P P D DD DD DD D X XC C X X P P D DD DDDD D
† There must always be multiples of 16 clocks while CS is low or commands will abort.
‡ The serial data out pin (SO) is only available on the MCP42XXX device.
CS
SCK
SO
Microcontroller
CS
SCK
CS
SI SO
SCK
Device 1 CS
SI SO
SCK
EXAMPLE: Device 2 SI
Device 1
XX10XX11 11001100 Device 2
XX01XX10 11110000 Device 3
XX10XX00 10101010
e
After 48 clocks, all 3 devices
Clock-In the data for Device 1 have the proper command/
(16 more clocks). The data that data loaded into their shift
was previously loaded into registers.
Device 1 gets shifted into Device 1
Device 2 and Device 3 contains XX10XX11 11001100 Device 2
the first byte loaded. Raise the XX01XX10 11110000 Device 3
XX10XX00 10101010
CS line to execute the com-
mands for all 3 devices at the
same time. * Last device on a daisy-chain may be a single channel MCP41XXX device.
Data is always latched in Data is always clocked out the SO Data Registers are
on the rising edge of SCK. pin after the falling edge of SCK.
loaded on rising
CS† edge of CS. Shift
register is loaded
with zeros at this time.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCK
† There must always be multiples of 16 clocks while CS is low or commands will abort.
‡
The serial data out pin (SO) is only available on the MCP42XXX device.
XXXXXXXX MCP41010
XXXXXNNN I/P256
YYWW 0313
XXXXXXXX MCP41050
XXXXYYWW I/SN0313
NNN 256
XXXXXXXXXXXXXX MCP42010
XXXXXXXXXXXXXX I/P
YYWWNNN 0313256
XXXXXXXXXXX 42050ISL
XXXXXXXXXXX XXXXXXXXXXX
YYWWNNN 0313256
XXXXXXXX 42100I
YYWW 0313
NNN 256
* Standard marking consists of Microchip part number, year code, week code, facility code, mask rev#,
and assembly code.
E1
n 1
A A2
L
c
A1
β B1
p
eB B
E1
D
2
B n 1
h α
45°
c
A A2
φ
β L A1
E1
n 1
α
A A2
c L
A1
β B1
eB
B p
E1
B n 1
α
h
45°
c
A A2
φ
A1
L
β
E1
2
n 1
B
α
A
β A1 A2
L
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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intended manner and under normal conditions.
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