Abdu Rahiman V

Lecturer in ECE
Govt. College of Engineering,
Kannur, Kerala, India

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
Arithmetic Operations
 Addition, Subtraction, Multiplication and Division
 Adder Implementation for unsigned integer
 Half adders and Full adders

Xi Yi Xi Yi Ci

Full adder

Si Ci+1
Half adder Si Ci+1
Abdu Rahiman V, Govt. College of Engineering,
Kannur, Kerala
Full Adder
 Addition of two four bit numbers X and Y
X = [X3 X2 X1 X0] and Y = [Y3 Y2 Y1 Y0]

Si  X i Y i Ci  X iYi Ci  X i Yi Ci 3 gate delays

Ci 1  X iYi  X i Ci  CiYi  X iYi  Ci ( X i  Yi )

Two gate delays to compute Ci 1 after obtaining Ci

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
4 bit ripple carry adder

X3 Y3 X2 Y2 X1 Y1 X0 Y0 C0

Full adder Full adder Full adder Full adder

C3 C2 C1

C4 S3 S2 S1 S0

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
Carry Look Ahead (CLA) Adder
 If carry of each stage is pre-computed with less delay,
it will speed up adder.
 How to pre compute carry

Ci 1  X iYi  X i Ci  CiYi
 X iYi  Ci ( X i  Yi )
 Gi  Ci Pi
Gi  X iYi Carry generation term - One delay
Pi  X i  Yi Carry propagation term - One delay

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
Pre-computation of carry
C1  X 0Y0  C0 ( X 0  Y0 )
 G0  C0 P0 3 delays
C2  G1  C1 P1  G1  (G0  C0 P0 ) P1
 G1  P1G0  P1 P0C0 3 delays
C3  G2  C2 P2  G2  (G1  P1G0  P1 P0C0 ) P2
 G2  P2G1  P2 P1G0  P2 P1 P0C0 3 delays
C4  G3  P3G2  P3 P2G1  P3 P2 P1G0  P3 P2 P1 P0C0 3 delays

Calculation of any carry requires only

3 gate delays
Abdu Rahiman V, Govt. College of Engineering,
Kannur, Kerala
Hardware requirements
 For 4 bit adder
 5 input AND gates, 5 input OR gates
 For 16 bit adder
 17 input AND gates, 17 input OR gates
 Complex and difficult to realize
 Costly but very fast

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
Block CLA adder
 Use blocks of four 4 bit CLA adder
 Pre-compute the carry to next stages using CLA
method

C4  G3  P3G2  P3 P2G1  P3 P2 P1G0  P3 P2 P1 P0C0 3 delays

 G1  P1C0
G1  G3  P3G2  P3 P2G1  P3 P2 P1G0
P1  P3 P2 P1 P0

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
C8  G7  P7G6  P7 P6G5  P7 P6 P5G4  P7 P6 P5 P4C4 3 delays
 G2  P2C 4  G2  P2 (G1  P1C0 )
 G2  P2G1  P2P1C0
C12  G3  P3G2  P3P2G1  P3P2P1C0
C16  G4  P4G3  P4P3G2  P4P3P2G1  P4P3P2P1C0

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
 Use blocks of four 4 bit CLA adder in ripple carry
configuration
 Slower but faster than 16 bit ripple carry adder
 Relatively low cost
a= 0:3, b=4:7, c=8:11, d=12:15

Xd Yd Xc Yc Xb Yb Xa Ya C0

4bit CLA 4bit CLA 4bit CLA 4bit CLA

adder adder adder adder

C12 C8 C4

C16 Sd Sc Sb Sa

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
Xd Yd Xc Yc Xb Yb Xa Ya C0

4bit CLA 4bit CLA 4bit CLA 4bit CLA

adder adder adder adder

C12 C8 C4

C16 Sd Sc Sb Sa

Carry Look ahead for each blocks

a= 0:3, b=4:7, c=8:11, d=12:15

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala
 Thank You

Abdu Rahiman V, Govt. College of Engineering,

Kannur, Kerala