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AN ABSTRACT ON

FUTURE MICROPROCESSOR AND THEIR POWER


GENERATION

BY: MOHAMMEED VASIM

It is often asked to paint a picture of microprocessor of future. Even if


newest processor just hits streets and has not even come close to full use,
people naturally crave where they are going rather than where they have
been. Over the last 10 years evolving microprocessor performance increased
at a higher than envisioned rate, unfortunately, so did manufacturing capital
costs. This paper lists predictions for today’s microprocessor performance at
speed at speeds of hundred MIPS which is equivalent to an rating of 2.5 and
clock rates of 150MHz. surprisingly, today’s performance dramatically
exceeds this. The Intel Pentium Pro processor with rating of 10 and 200MHz
clock rate. This great performance boost has stimulated a huge range of
applications for business, home and entertainment, from mobile computers
to servers. As a result, the PC market segment isa lot larger today than we
anticipated years ago.
The bad news is producing advanced microprocessors involves much higher
capital cost than anyone ever expected. At Intel, we’ve augmented Moore’s
law(the number of transistors on a processor doubles approximately every
18 months) with Moore’s law 2. Law 2 says that as the sophistication of chips
increases, the cost of fabrication rises exponentially.

By reducing the power supply voltage, faster, lower power consumption, and
high integration density data processing systems can be achieved. The
current generation high-speed CMOS processors are operating at above
300MHz with 2.5 to 3.3V output range. Future processors will be designed in
the 1.1-1.8V range, in further enhance their speed-power performance.
These new generations microprocessors will present very dynamic loads with
high current slew rates during transient. As a result, they will require a
special power supply, Voltage Regulator Module (VRM), to provide well-
regulated voltage. The VRMs should have high power densities, high
efficiencies, and good transient performance. This paper addresses the
critical technical issues to achieve this target for future generation
microprocessors.

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