SEL 4743 Basic Digital VLSI: Project: IC Number Generator (Complete Report)

SEL 4743
Basic Digital VLSI

Project : IC number Generator (Complete Report)
Name : Lee Yee Hui

IC Number : 880417-35-5172
Matric Number : AE070120
Course : SEC (Computer Engineering)
Section : 01
Supervisor : En. Zulkifli Bin Md Yusof
Date : 28 November 2010
Truth Table:
PS NS Output, O
PS3 PS2 PS1 PS0 NS3 NS2 NS1 NS0 O3 O2 O1 O0
0 0 0 0 0 0 0 1 1 0 0 0 =8
0 0 0 1 0 0 1 0 1 0 0 0 =8
0 0 1 0 0 0 1 1 0 0 0 0 =0
0 0 1 1 0 1 0 0 0 1 0 0 =4
0 1 0 0 0 1 0 1 0 0 0 1 =1
0 1 0 1 0 1 1 0 0 1 1 1 =7
0 1 1 0 0 1 1 1 0 0 1 1 =3
0 1 1 1 1 0 0 0 0 1 0 1 =5
1 0 0 0 1 0 0 1 0 1 0 1 =5
1 0 0 1 1 0 1 0 0 0 0 1 =1
1 0 1 0 1 0 1 1 0 1 1 1 =7
1 0 1 1 0 0 0 0 0 0 1 0 =2
1 1 0 0 X X X X X X X X
1 1 0 1 X X X X X X X X
1 1 1 0 X X X X X X X X
1 1 1 1 X X X X X X X X
0 4
8 1
8 7
2 3
7 5
1 5
QUARTUS II Simulation
Next state logic:
PS3 PS2 PS3 PS2

PS1 PS0 00 01 11 10 PS1 PS0 00 01 11 10
00 0 0 X 1 00 0 1 X 0
01 0 0 X 1 01 0 1 X 0
11 0 1 X 0 11 1 0 X 0
10 0 0 X 1 10 0 1 X 0
NS3 = PS1PS3+PS0PS3+PS0PS1PS2 NS2 = PS1PS2+PS0PS2 + PS0PS1PS2PS3
= (PS0+PS1)PS3+PS0PS1PS2 = (PS0+PS1)PS2+PS0PS1PS2PS3
PS3 PS2 PS3 PS2

PS1 PS0 00 01 11 10 PS1 PS0 00 01 1
0 0 X 0 00 1 1 X 1 00
1 1 X 1 01 0 0 X 0 01
0 0 X 0 11 0 0 X 0 11
1 1 X 1 10 1 1 X 1 10
NS1 = PS0PS1+PS0PS1 NS0 = PS0
= PS0 + PS1
Output Logic:
PS3 PS2 PS3 PS2

PS1 PS0 00 01 11 10 PS1 PS0 00 01 11 10
1 000 X 0 00 0 0 X 1
1 010 X 0 01 0 1 X 0
0 110 X 0 11 1 1 X 0
0 100 X 0 10 0 0 X 1
O3 = PS1PS2PS3 O2 = PS0PS1PS3+PS0PS3+PS0PS2
= PS0(PS1PS3+PS2)+PS0PS3
PS3 PS2 PS3 PS2

PS1 PS0 00 01 11 10 PS1 PS0 00 01 11 10
00 0 0 X 0 00 0 1 X 1
01 0 1 X 0 01 0 1 X 1
11 0 0 X 1 11 0 1 X 0
10 0 1 X 1 10 0 1 X 1
O1= PS0PS1PS2+ PS0PS1PS2+PS1PS3 O0 = PS2+PS1PS3+PS0PS3
= PS0PS1PS2+PS1(PS0PS2+PS3) = PS2+(PS0+PS1)PS3
Schematic Diagram For Top Level:

Timing Simulation Result for the design:
S-edit Simulation
NS3 = (PS0+PS1)PS3+PS0PS1PS2
NS2 = (PS0+PS1)PS2+PS0PS1PS2PS3
NS1 = PS0PS1+PS0PS1 NS0 = PS0
NS_logic
********* Simulation Settings - General section *********
.include "C:\Users\YeeHui\Documents\micron_25.txt"
*************** Subcircuits *****************
.subckt NS0 NS0 PS0 Gnd Vdd
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 NS0 PS0 Gnd 0 NMOS W=375n L=250n AS=337.5f PS=2.55u AD=337.5f PD=2.55u
MPMOS_1 NS0 PS0 Vdd Vdd PMOS W=1.125u L=250n AS=1.0125p PS=4.05u AD=1.0125p PD=4.05u
.ends
.subckt NS1 NS1 PS0 PS1 PS0bar PS1bar Gnd Vdd
MNMOS_1 N_1 PS0bar Gnd 0 NMOS W=750n L=250n AS=675f PS=3.3u AD=675f PD=3.3u
MNMOS_2 N_1 PS1 Gnd 0 NMOS W=750n L=250n AS=675f PS=3.3u AD=675f PD=3.3u
MNMOS_3 NS1 PS1bar N_1 0 NMOS W=750n L=250n AS=675f PS=3.3u AD=675f PD=3.3u
MNMOS_4 NS1 PS0 N_1 0 NMOS W=750n L=250n AS=675f PS=3.3u AD=675f PD=3.3u
MPMOS_1 N_3 PS0 Vdd Vdd PMOS W=2.25u L=250n AS=2.025p PS=6.3u AD=2.025p PD=6.3u
MPMOS_2 N_2 PS0bar Vdd Vdd PMOS W=2.25u L=250n AS=2.025p PS=6.3u AD=2.025p PD=6.3u
MPMOS_3 NS1 PS1 N_2 Vdd PMOS W=2.25u L=250n AS=2.025p PS=6.3u AD=2.025p PD=6.3u
MPMOS_4 NS1 PS1bar N_3 Vdd PMOS W=2.25u L=250n AS=2.025p PS=6.3u AD=2.025p PD=6.3u
.ends
.subckt NS2 NS2 PS0 PS1 PS2 PS3 PS0bar PS1bar PS2bar Gnd Vdd
Simulation
MNMOS_6 N_1 waveform(Next StateL=250n
PS1 N_2 0 NMOS W=1.5u Logic):
AS=1.35p PS=4.8u AD=1.35p PD=4.8u
MNMOS_7 N_2 PS0 Gnd 0 NMOS W=1.5u L=250n AS=1.35p PS=4.8u AD=1.35p PD=4.8u
MPMOS_5 N_4 PS2 N_5 Vdd PMOS W=4.5u L=250n AS=4.05p PS=10.8u AD=4.05p PD=10.8u
MPMOS_6 N_5 PS1bar N_6 Vdd PMOS W=4.5u L=250n AS=4.05p PS=10.8u AD=4.05p PD=10.8u
.ends
.subckt NS3 NS3 PS0 PS1 PS0bar PS1bar PS2bar PS3bar Gnd Vdd
MNMOS_4 N_1 PS1 N_2 0 NMOS W=1.5u L=250n AS=1.35p PS=4.8u AD=1.35p PD=4.8u
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XNS3_1 NS3 PS0 PS1 PS0bar PS1bar PS2bar PS3bar Gnd Vdd NS3
XNS0_1 NS0 PS0 Gnd Vdd NS0
XNS1_1 NS1 PS0 PS1 PS0bar PS1bar Gnd Vdd NS1
XNS2_1 NS2 PS0 PS1 PS2 PS3 PS0bar PS1bar PS2bar Gnd Vdd NS2
VVdd Vdd0001Gnd 0010

DC 2.50011 0100 0101 0110 0111 1000 1001 1010 1011 0000
VPS0 PS0 GND pulse (0 2.5 23n 2n 2n 23n 50n)
VPS0bar PS0bar GND pulse (2.5 0 23n 2n 2n 23n 50n)
.tran 1n 400n
.probe
.print tran v(NS0) v(NS1) v(NS2) v(NS3) v(PS0) v(PS1) v(PS2) v(PS3)
.end
O3 = PS1PS2PS3 O2 = PS0(PS1PS3+PS2)+PS0PS3
O1= PS0PS1PS2+PS1(PS0PS2+PS3) O0= PS2+(PS0+PS1)PS3
Output Logic
Simulation waveform (Output Logic):
*************** Subcircuits *****************
.subckt O0 O0 PS0 PS1 PS2bar PS3bar Gnd Vdd
MNMOS_1 O0 PS2bar N_1 0 NMOS W=750n L=250n AS=675f PS=3.3u AD=675f PD=3.3u
MPMOS_1 O0 PS2bar Vdd Vdd PMOS W=1.125u L=250n AS=1.0125p PS=4.05u AD=1.0125p PD=4.05u
MPMOS_4 O0 PS3bar N_3 Vdd PMOS W=2.25u L=250n AS=2.025p PS=6.3u AD=2.025p PD=6.3u
.ends
.subckt O1 O1 PS0 PS1 PS0bar PS1bar PS2bar PS3bar Gnd Vdd
MNMOS_2 O1 PS1 N_3 0 NMOS W=750n L=250n AS=675f PS=3.3u AD=675f PD=3.3u
MNMOS_5 N_1 PS3bar Gnd 0 NMOS W=1.5u L=250n AS=1.35p PS=4.8u AD=1.35p PD=4.8u
MNMOS_7 N_3 PS2bar N_1 0 NMOS W=1.5u L=250n AS=1.35p PS=4.8u AD=1.35p PD=4.8u
.ends
.subckt O2 O2 PS0 PS3 PS0bar PS1bar PS2bar PS3bar Gnd Vdd
1000 1000 0000 0100 0001 0111 0011 0101 0101 0001 0111 0010
MNMOS_1 O2 PS0 N_2 0 NMOS W=750n L=250n AS=675f PS=3.3u AD=675f PD=3.3u
8
MNMOS_2 0 N_240 NMOS
8O2 PS3bar 1 W=750n 7 L=250n
3 AS=675f
5 PS=3.3u
5 AD=675f
1 7
PD=3.3u2
MNMOS_4 N_2 PS2bar N_6 0 NMOS W=1.5u L=250n AS=1.35p PS=4.8u AD=1.35p PD=4.8u
MNMOS_5 N_6 PS1bar Gnd 0 NMOS W=1.5u L=250n AS=1.35p PS=4.8u AD=1.35p PD=4.8u
.ends
.subckt O3 O3 PS1 PS2 PS3 Gnd Vdd
MNMOS_1 O3 PS3 Gnd 0 NMOS W=375n L=250n AS=337.5f PS=2.55u AD=337.5f PD=2.55u
MPMOS_3 O3 PS3 N_2 Vdd PMOS W=3.375u L=250n AS=3.0375p PS=8.55u AD=3.0375p PD=8.55u
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XO0_1 O0 PS0 PS1 PS2bar PS3bar Gnd Vdd O0
XO1_1 O1 PS0 PS1 PS0bar PS1bar PS2bar PS3bar Gnd Vdd O1
XO2_1 O2 PS0 PS3 PS0bar PS1bar PS2bar PS3bar Gnd Vdd O2
XO3_1 O3 PS1 PS2 PS3 Gnd Vdd O3
VVdd Vdd Gnd DC 2.5
.tran 1n 400n
.probe
.print tran v(O0) v(O1) v(O2) v(O3) v(PS0) v(PS1) v(PS2) v(PS3)
.end
Calculation and Simulation Result (O3)
Let’s take O3 of the output logic for the comparison,
O3 = PS1PS2PS3
VDD
R1
PS1
R2 C1
PS2
R3
C2
PS3
CL
R4 R5 R6
PS1 PS2 PS3
Manual Calculation:
PMOS NMOS
Cox 6.14 x 10-3 6.14 x 10-3
Co 0.27 0.31
Cjo 1.9 2
Cjswo 0.22 0.28
Keq (H→L) 0.79 ; (L→H) 0.59 (H→L) 0.57 ; (L→H) 0.79
Keqsw (H→L) 0.86 ; (L→H) 0.7 (H→L) 0.61 ; (L→H) 0.81
From netlist for O3:
MPMOS_3 O3 PS3 N_2 Vdd PMOS W=3.375u L=250n AS=3.0375p PS=8.55u AD=3.0375p PD=8.55u
C term Expression Value (fF) Value (fF)

(H→L) (L→H)
Cd1 = Cd2 = Cd3 Keqp x ADp x Cjop + 0.79*3.0375x10-6*1.9 + 0.59*3.0375x10-6*1.9 +
= Cs1 = Cs2 = Cs3 Keqswp x PDp x Cjswop 0.86*8.55*0.22 0.7*8.55*0.22
= 1.62fF =1.32fF
Cd4 = Cd5 = Cd6 Keqn x ADn x Cjon + 0.57*3.375x10-7*2 + 0.79*3.375x10-7*2 +
0.61*2.55*0.28 0.81*2.55*0.28
Keqswn x PDn x Cjswon =0.44fF =0.58fF
Cgd1 = Cgd2 = Cgd3 2CopWp 2*0.27*3.375 2*0.27*3.375
=1.82fF =1.82fF
Cgd4 = Cgd5 = Cgd6 2ConWn 2*0.31*0.375 2*0.31*0.375
=0.23fF =0.23fF
Cgs2 = Cgs3 2CopWp 2*0.27*3.375 2*0.27*3.375
=1.82fF =1.82fF
Capacitor Contribution Value(fF)

C1 Cd1 + Cs2 + Cgd1 + Cgs2 (L→H):
1.32 + 1.32 + 1.82 + 1.82 = 6.28fF
(H→L):
1.62 + 1.62 + 1.82 + 1.82 = 6.88fF
C2 Cd2 + Cs3 + Cgd2 + Cgs3 (L→H):
1.32 + 1.32 + 1.82 + 1.82 = 6.28fF
(H→L):
1.62 + 1.62 + 1.82 + 1.82 = 6.88fF
CL Cd3 + 2*Cgd3 + Cd4 + Cd5 + Cd6 + Cgd4 + (L→H):
Cgd5 + Cgd6 1.32 + 1.82 + 3*0.58 + 3*0.23 = 5.57fF
= Cd3 + Cgd3 + 3*Cd4 + 3*Cgd5
(H→L):
1.62 + 1.82 + 3*0.44 + 3*0.23 = 5.45fF
For worse case (input {PS1 PS2 PS3} transition from 111 → 000),
tpLH = 0.69(R1.C1 + (R1+R2).C2 + (R1+R2+R3).CL)
= 0.69Rp (C1+2.C2 + 3.CL)
= 0.69* (31kΩ/13.5)(6.28fF+2*6.28fF + 3*5.57fF)
= 56.327ps
For worse case (input {PS1 PS2 PS3} transition from 000 → 001),
tpHL = 0.69(Rn.CL) +0.69[(Rp + Rn)C2 + (2Rp + Rn)C1]
= 0.69*(13kΩ/1.5)(5.45fF)+0.69[(10.96kΩ)*6.88fF + (13.26kΩ)*6.88fF]
= 147.568ps
tp = (tpHL + tpLH) / 2
= (56.327 + 147.568) / 2
= 101.948ps
Simulation:
From the simulation result (input transition from 000 → 001) :
tpHL = 436.859ps
From the simulation result, fall time, tf = 873.718ps

From the simulation result (input transition from 111 → 000) :
tpLH = 291.238ps
From the simulation result, rise time, tr = 789.028ps
tp = (tpHL + tpLH) / 2
= (436.859 + 291.238) / 2
= 364.049ps
Comparison between simulation result and calculation result:
Simulation : tp = 364.049ps
Calculation : tp = 101.948ps
It can be observed that the propagation delay obtain from simulation result and
calculation are slightly different. This may due to the sensitivity of the W-edit where we
are not able to set the cursors of the graph to the exact point we want. Other than that, the
calculation method is using the formula to approximate the propagation delay which will
cause inaccuracy of the result obtained.
Minimum pulse period that produce correct result:
Following shows the minimum pulse change period can be used to for simulation that
could produce the correct output waveforms.
VVdd Vdd Gnd DC 2.5
VPS0 PS0 GND pulse (0 2.5 0.9n 0.1n 0.1n 0.9n 2n)
VPS0bar PS0bar GND pulse (2.5 0 0.9n 0.1n 0.1n 0.9n 2n)
.tran 0.1n 16n
.probe
.print tran v(O0) v(O1) v(O2) v(O3) v(PS0) v(PS1) v(PS2) v(PS3)
L-edit & LVS Simulation
O3:
O3
PS3 PS2 PS1

O3 VDD
GND
VDD
O3
PS1 PS2 PS3

GND
O2:
O2
PS3bar PS0
PS2bar
O2 VDD
PS0bar
PS3
PS1bar
GND
VDD
O2
PS1 PS3 PS0 PS3 PS0 PS2

GND
O1:
O1
PS2bar PS1 PS0bar
O1 VDD
PS0
PS1bar PS2bar
PS3bar
GND
VDD
O1
PS0 PS1 PS2 PS1 PS3 PS0 PS2

GND
O0:
O0
PS2bar
O0 VDD
PS0
PS3bar
PS1
GND
VDD
PS0 PS1
GND
NS3:
NS3
PS1bar
PS2bar PS0bar
NS3 VDD
PS1
PS3bar
PS0
GND VDD
NS3
PS1 PS0 PS3 PS2 PS1 PS0

GND
Netlists and Waveform Simulations for Output Logic (L-edit):
O3:
* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* TDB File: C:\Users\YeeHui\Documents\4th year\VLSI\l-edit\output.tdb
* Cell: O3 Version 1.03
* Extract Definition File: mamin08.ext
* Extract Date and Time: 11/24/2010 - 18:22
* Warning: Layers with Unassigned AREA Capacitance.
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* Warning: Layers with Unassigned FRINGE Capacitance.
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <Pad Comment>
M1 O3 PS3 8 Vdd PMOS L=250n W=3.375u AD=3.375p PD=8.75u AS=1.6875p PS=4.375u $ (-12 233 -10 260)
M2 8 PS2 6 Vdd PMOS L=250n W=3.375u AD=1.6875p PD=4.375u AS=1.6875p PS=4.375u $ (-22 233 -20 260)
M3 6 PS1 Vdd Vdd PMOS L=250n W=3.375u AD=1.6875p PD=4.375u AS=4.640625p PS=9.5u $ (-32 233 -30 260)
M4 O3 PS3 GND GND NMOS L=250n W=375n AD=796.875f PD=3.75u AS=421.875f PS=2u $ (-12 215 -10 218)
M5 GND PS2 O3 GND NMOS L=250n W=375n AD=421.875f PD=2u AS=421.875f PS=2u $ (-22 215 -20 218)
M6 O3 PS1 GND GND NMOS L=250n W=375n AD=421.875f PD=2u AS=1.296875p PS=4.75u $ (-32 215 -30 218)
* Pins of element D1 are shorted:
* D1 GND GND D_lateral AREA=1.25E-016 $ (-43 210 -42.999 218)
* D2 Vdd Vdd D_lateral AREA=4.21875E-016 $ (-43.001 233 -43 260)
VVdd Vdd Gnd DC 2.5
.tran 1n 400n
.probe
.print tran v(O3) v(PS0) v(PS1) v(PS2) v(PS3)
* Total Nodes: 8
* Total Elements: 8
* Total Number of Shorted Elements not written to the SPICE file: 0
* Output Generation Elapsed Time: 0.001 sec
* Total Extract Elapsed Time: 3.964 sec
.END
O2: * TDB File: C:\Users\YeeHui\Documents\4th year\VLSI\l-edit\output.tdb
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <Pad Comment>
M1 13 PS1bar Vdd Vdd PMOS L=250n W=4.5u AD=2.25p PD=5.5u AS=5.0625p PS=11.25u $ (20 4 22 40)
M2 2 PS2bar Vdd Vdd PMOS L=250n W=2.25u AD=4.21875p PD=11u AS=1.96875p PS=5.5u $ (70 22 72 40)
M3 Vdd PS0 11 Vdd PMOS L=250n W=2.25u AD=1.96875p PD=5.5u AS=1.96875p PS=5.5u $ (60 22 62 40)
M4 11 PS3bar O2 Vdd PMOS L=250n W=2.25u AD=1.96875p PD=5.5u AS=1.96875p PS=5.5u $ (50 22 52 40)
M5 O2 PS0bar 2 Vdd PMOS L=250n W=2.25u AD=1.96875p PD=5.5u AS=2.109375p PS=5.5u $ (40 22 42 40)
M6 2 PS3 13 Vdd PMOS L=250n W=4.5u AD=2.109375p PD=5.5u AS=2.25p PS=5.5u $ (30 4 32 40)
M7 1 PS1bar GND GND NMOS L=250n W=1.5u AD=750f PD=2.5u AS=1.6875p PS=5.25u $ (20 -30 22 -18)
M8 1 PS2bar 3 GND NMOS L=250n W=1.5u AD=1.5p PD=5u AS=703.125f PS=2.5u $ (70 -30 72 -18)
M9 3 PS0 O2 GND NMOS L=250n W=750n AD=703.125f PD=2.5u AS=656.25f PS=2.5u $ (60 -30 62 -24)
M10 O2 PS3bar 3 GND NMOS L=250n W=750n AD=656.25f PD=2.5u AS=656.25f PS=2.5u $ (50 -30 52 -24)
M11 3 PS0bar GND GND NMOS L=250n W=750n AD=656.25f PD=2.5u AS=703.125f PS=2.5u $ (40 -30 42 -24)
M12 GND PS3 1 GND NMOS L=250n W=1.5u AD=703.125f PD=2.5u AS=750f PS=2.5u $ (30 -30 32 -18)
* D1 GND GND D_lateral AREA=1.875E-016 $ (11 -30 11.001 -18)
* D2 Vdd Vdd D_lateral AREA=5.625E-016 $ (10.999 4 11 40)
VVdd Vdd Gnd DC 2.5
.tran 1n 400n
.probe
* Total Nodes: 14
* Total Elements: 14
.END
O1: * Extract Definition File: mamin08.ext
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <Pad Comment>
M1 4 PS2bar 15 Vdd PMOS L=250n W=4.5u AD=5.625p PD=11.5u AS=2.25p PS=5.5u $ (71 -9 73 27)
M3 15 PS0 Vdd Vdd PMOS L=250n W=4.5u AD=2.25p PD=5.5u AS=2.109375p PS=5.5u $ (61 -9 63 27)
M4 Vdd PS3bar 4 Vdd PMOS L=250n W=2.25u AD=2.109375p PD=5.5u AS=1.96875p PS=5.5u $ (51 9 53 27)
M5 4 PS1bar O1 Vdd PMOS L=250n W=2.25u AD=1.96875p PD=5.5u AS=2.0390625p PS=5.5u $ (41 9 43 27)
M6 13 PS1 9 Vdd PMOS L=250n W=3.375u AD=2.109375p PD=5.5u AS=2.109375p PS=5.5u $ (21 0 23 27)
M7 9 PS0bar Vdd Vdd PMOS L=250n W=3.375u AD=2.109375p PD=5.5u AS=4.359375p PS=11u $ (11 0 13 27)
M8 2 PS2bar 1 GND NMOS L=250n W=1.5u AD=1.6875p PD=5.25u AS=750f PS=2.5u $ (71 -43 73 -31)
M9 1 PS2bar O1 GND NMOS L=250n W=1u AD=687.5f PD=2.5u AS=687.5f PS=2.5u $ (31 -39 33 -31)
M10 1 PS0 2 GND NMOS L=250n W=1.5u AD=750f PD=2.5u AS=750f PS=2.5u $ (61 -43 63 -31)
M11 2 PS3bar GND GND NMOS L=250n W=1.5u AD=750f PD=2.5u AS=953.125f PS=3.125u $ (51 -43 53 -31)
M12 GND PS1bar 1 GND NMOS L=250n W=1u AD=953.125f PD=3.125u AS=687.5f PS=2.5u $ (41 -39 43 -31)
M13 O1 PS1 1 GND NMOS L=250n W=1u AD=687.5f PD=2.5u AS=687.5f PS=2.5u $ (21 -39 23 -31)
M14 1 PS0bar O1 GND NMOS L=250n W=1u AD=687.5f PD=2.5u AS=1.25p PS=4.75u $ (11 -39 13 -31)
* D1 GND GND D_lateral AREA=9.375E-017 $ (44 -48 50 -47.999)
* D2 Vdd Vdd D_lateral AREA=5.625E-016 $ (2.999 -9 3 27)
VVdd Vdd Gnd DC 2.5
.tran 1n 400n
.probe
* Total Nodes: 15
.END
O0: * Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <Pad Comment>
M1 Vdd PS2bar O0 Vdd PMOS L=250n W=1.125u AD=2.109375p PD=6.5u AS=1.0546875p PS=3.25u $ (40 31 42 40)
M3 4 PS1 Vdd Vdd PMOS L=250n W=2.25u AD=1.125p PD=3.25u AS=1.3125p PS=3.75u $ (20 22 22 40)
M4 Vdd PS0 4 Vdd PMOS L=250n W=2.25u AD=1.3125p PD=3.75u AS=2.8125p PS=7u $ (10 22 12 40)
M5 O0 PS2bar 2 GND NMOS L=250n W=750n AD=1.40625p PD=5u AS=656.25f PS=2.5u $ (40 -6 42 0)
M6 2 PS3bar GND GND NMOS L=250n W=750n AD=656.25f PD=2.5u AS=890.625f PS=3u $ (30 -6 32 0)
M7 GND PS1 6 GND NMOS L=250n W=1.5u AD=890.625f PD=3u AS=750f PS=2.5u $ (20 -12 22 0)
M8 6 PS0 2 GND NMOS L=250n W=1.5u AD=750f PD=2.5u AS=1.875p PS=5.5u $ (10 -12 12 0)
* D2 Vdd Vdd D_lateral AREA=9.375E-017 $ (13 44 19 44.001)
VVdd Vdd Gnd DC 2.5
.tran 1n 400n
.probe
* Total Nodes: 10
.END
Netlist and Waveform Simulation for Next State Logic, NS3 (L-edit)
* Cell: NS3 Version 1.03
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <NMOS Capacitor>
* <PMOS Capacitor>
* <PCAP Capacitor>
* <Pad Comment>
M1 Vdd PS0bar 14 Vdd PMOS L=250n W=3.375u AD=4.21875p PD=9.25u AS=1.6875p PS=4.375u $ (58 13 60 40)
M2 14 PS1bar 12 Vdd PMOS L=250n W=3.375u AD=1.6875p PD=4.375u AS=1.6875p PS=4.375u $ (48 13 50 40)
M3 12 PS2bar NS3 Vdd PMOS L=250n W=3.375u AD=1.6875p PD=4.375u AS=1.6171875p PS=4.375u $ (38 13 40 40)
M4 NS3 PS3bar 4 Vdd PMOS L=250n W=2.25u AD=1.6171875p PD=4.375u AS=1.546875p PS=4.375u $ (28 22 30 40)
M5 4 PS0 Vdd Vdd PMOS L=250n W=2.25u AD=1.546875p PD=4.375u AS=1.546875p PS=4.375u $ (18 22 20 40)
M6 Vdd PS1 4 Vdd PMOS L=250n W=2.25u AD=1.546875p PD=4.375u AS=3.234375p PS=8.75u $ (8 22 10 40)
M7 NS3 PS0bar 1 GND NMOS L=250n W=750n AD=1.78125p PD=5.5u AS=656.25f PS=2.5u $ (58 -14 60 -8)
M8 1 PS1bar NS3 GND NMOS L=250n W=750n AD=656.25f PD=2.5u AS=656.25f PS=2.5u $ (48 -14 50 -8)
M9 NS3 PS2bar 1 GND NMOS L=250n W=750n AD=656.25f PD=2.5u AS=656.25f PS=2.5u $ (38 -14 40 -8)
M10 1 PS3bar GND GND NMOS L=250n W=750n AD=656.25f PD=2.5u AS=843.75f PS=2.875u $ (28 -14 30 -8)
M11 GND PS0 6 GND NMOS L=250n W=1.5u AD=843.75f PD=2.875u AS=750f PS=2.5u $ (18 -20 20 -8)
M12 6 PS1 1 GND NMOS L=250n W=1.5u AD=750f PD=2.5u AS=1.5p PS=5u $ (8 -20 10 -8)
* D2 Vdd Vdd D_lateral AREA=4.21875E-016 $ (70 13 70.001 40)
VVdd Vdd Gnd DC 2.5
.tran 1n 400n
.probe
.print tran v(NS3) v(PS0) v(PS1) v(PS2) v(PS3)
* Total Nodes: 14
.END

SEL 4743 Basic Digital VLSI: Project: IC Number Generator (Complete Report)

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

SEL 4743 Basic Digital VLSI: Project: IC Number Generator (Complete Report)

Uploaded by

Copyright:

Available Formats

SEL 4743

Basic Digital VLSI

Name : Lee Yee Hui

PS3 PS2 PS3 PS2

NS3 = PS1PS3+PS0PS3+PS0PS1PS2 NS2 = PS1PS2+PS0PS2 + PS0PS1PS2PS3

PS3 PS2 PS3 PS2

NS1 = PS0PS1+PS0PS1 NS0 = PS0

PS3 PS2 PS3 PS2

PS3 PS2 PS3 PS2

O1= PS0PS1PS2+ PS0PS1PS2+PS1PS3 O0 = PS2+PS1PS3+PS0PS3

Schematic Diagram For Top Level:

VVdd Vdd0001Gnd 0010

Let’s take O3 of the output logic for the comparison,

PS1 PS2 PS3

From netlist for O3:

C term Expression Value (fF) Value (fF)

Capacitor Contribution Value(fF)

tpLH = 0.69(R1.C1 + (R1+R2).C2 + (R1+R2+R3).CL)

= 0.69Rp (C1+2.C2 + 3.CL)

= 0.69* (31kΩ/13.5)(6.28fF+2*6.28fF + 3*5.57fF)

tpHL = 0.69(Rn.CL) +0.69[(Rp + Rn)C2 + (2Rp + Rn)C1]

From the simulation result (input transition from 000 → 001) :

From the simulation result, fall time, tf = 873.718ps

From the simulation result, rise time, tr = 789.028ps

Minimum pulse period that produce correct result:

PS3 PS2 PS1

PS1 PS2 PS3

PS1 PS3 PS0 PS3 PS0 PS2

PS2bar PS1 PS0bar

PS0 PS1 PS2 PS1 PS3 PS0 PS2

PS1 PS0 PS3 PS2 PS1 PS0

You might also like

= 0.69* (31kΩ/13.5)(6.28fF+26.28fF + 35.57fF)