MUX 4:1

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 7 / 1
-------------------------------------------------------------------------
Delay: 9.317ns (Levels of Logic = 4)
Source: i<1> (PAD)
Destination: o (PAD)

Data Path: i<1> to o

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.821 1.140 i_1_IBUF (i_1_IBUF)
LUT3:I0->O 1 0.551 0.000 o_F (N5)
MUXF5:I0->O 1 0.360 0.801 o (o_OBUF)
OBUF:I->O 5.644 o_OBUF (o)
----------------------------------------
Total 9.317ns (7.376ns logic, 1.941ns route)
(79.2% logic, 20.8% route)

=========================================================================
CPU : 8.20 / 8.56 s | Elapsed : 8.00 / 8.00 s

Device utilization summary:

---------------------------

Selected Device : 3s400tq144-4

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 97 7%
USER constraint file:

NET "a" LOC = "p92" ;

NET "b" LOC = "p96" ;
NET "i<0>" LOC = "p74" ;
NET "i<1>" LOC = "p76" ;
NET "i<2>" LOC = "p77" ;
NET "i<3>" LOC = "p79" ;
NET "o" LOC = "p137" ;

SELF generated TEXT fixture :

module mux41tf_v;

// Inputs
reg [0:3] i;
reg a;
reg b;

// Outputs
wire o;
 // Instantiate the Unit Under Test (UUT)
mux41 uut (
.i(i),
.a(a),
.b(b),
.o(o)
);

initial begin
// Initialize Inputs
i = 0;
a = 0;
b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule