The project plan involves 3 phases over 19 weeks: 1) a 2 week foundation on HDL concepts, 2) a 6 week focus on Verilog language constructs and tools through simulation and synthesis assignments, and 3) a 7 week project to design a processor through RTL design, functional simulation, and reporting. Work is tracked through a table of assignments, submissions, and signatures.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
The project plan involves 3 phases over 19 weeks: 1) a 2 week foundation on HDL concepts, 2) a 6 week focus on Verilog language constructs and tools through simulation and synthesis assignments, and 3) a 7 week project to design a processor through RTL design, functional simulation, and reporting. Work is tracked through a table of assignments, submissions, and signatures.
The project plan involves 3 phases over 19 weeks: 1) a 2 week foundation on HDL concepts, 2) a 6 week focus on Verilog language constructs and tools through simulation and synthesis assignments, and 3) a 7 week project to design a processor through RTL design, functional simulation, and reporting. Work is tracked through a table of assignments, submissions, and signatures.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
The project plan involves 3 phases over 19 weeks: 1) a 2 week foundation on HDL concepts, 2) a 6 week focus on Verilog language constructs and tools through simulation and synthesis assignments, and 3) a 7 week project to design a processor through RTL design, functional simulation, and reporting. Work is tracked through a table of assignments, submissions, and signatures.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
a. VLSI design flow for digital systems, b. Importance/significance of HDLs c. Types of HDL (VHDL, Verilog), their capabilities and limitations
2. Concepts of Verilog HDL (6 weeks – 1st Aug to 11th Sep)
(Learning language constructs, tools usage, assignments.) a. Simulation (4 weeks) b. Synthesis (2 weeks)
3. Project problem (7 weeks )
a. Design – Different methodologies (RTL), concepts of control unit and datapath unit. (2 weeks) b. Implementation – Functional Simulation (10 days ) c. Report (1 week ) Date Work Assigned Work Submitted Signature 30/07/2010 Introduction to verilog __ and Digital design 06/08/2010 Chapter – 1 and 2 Introduction (Samir palnitkar) 13/08/2010 Chapter – 3 and 4 Chapter – 1 and 2 (Samir palnitkar) (Samir palnitkar) 27/08/2010 Chapter – 5 and 6 Chapter – 3 and 4 (Samir palnitkar) (Samir palnitkar) 02/09/2010 Chapter – 1 and 2 Chapter – 5 and 6 (Bhaskar) (Samir palnitkar) 09/09/2010 Processor Chapter – 1 and 2 Morris mano(CH-8,9,10) (Bhaskar) 23/09/2010 Processor architecture Chapter- 8 (Ciletti) Digital processors and Architecture Ch- 7 and 8(M.M.) 28/10/2010 Architecture Processor Design, Started development and making report Instruction set complete format 04/11/2010 Summary, design Partial Report specification, design- documentation, assignments 09/11/2010 Verilog coding Summary, design specification, design- documentation, assignments 12/11/2010 Continue with single Multi cycle design cycle coding description 19/11/2010 Problems Progress Report
S.No. Period (Event) Work(s) Done Signature
1 Till MidSem Work Concepts of Verilog Hdl – Presentation Simulation and Synthesis Finalization of Topic for Minor Project 2. Between MidSem Viva and EndSem Viva References
1) David A Patterson And John l.Hennessy, Computer organization & design,
3rded Morgan Koffman Publishers, 2005
2) Morris Mano, Digital Design, Third Edition, Prentice Hall, 2002
3) Barry.B.Brey, Intel. Microprocessors 8086-8088,4th ed,Prentice Hall Inc 1997