Phase Locked Loop (PLL)

A phase-locked loop (PLL) is an electronic circuit that controls an oscillator so that it

maintains a constant phase angle relative to a reference signal. In communications, the
oscillator is usually at the receiver, and the reference signal is extracted from the signal
received from the remote transmitter. Phase-locked loops are widely used in space
communications for coherent carrier
tracking and threshold extension, bit synchronization, and symbol synchronization.

Digital Phase Lock Loop (DPLL)

A Digital PLL (DPLL) circuit may consist of a serial shift register which receives digital
input samples (extracted from the received signal), a stable local clock signal which
supplies clock pulses to the shift register to drive it and a phase corrector circuit which
takes the local clock and regenerates a stable clock in phase with the received signal by
slowly adjusting the phase of the phase of the regenerated clock to match the received
signal.

This circuit is useful when the data and clock are sent together over a common cable (as
in Manchester encoding), since it allows the receiver to separate (regenerate) the clock
signal from the received data. The regenerated clock signal is then used to sample the
received data and determine the value of each received bit.

Transistor matching: When an amplifier stage has two or more transistors, it is best to
have all devices of the same gain and output to better equalize power sharing and d.c.
current in each device. Other companies only offer matching of "Beta Codes" — hardly
what matching is really about.

Analog Circuits use matched transistors ! Where ?

Differential pairs want voltage matching on VGS

Current mirrors want current matching