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Vlsi Design - Department of Electronics and Communication
Vlsi Design - Department of Electronics and Communication
KINGS
COLLEGE OF ENGINEERING
PUNALKULAM.
QUESTION BANK
SUBJECT CODE : EC1401 SEM / YEAR : VII/ IV
UNIT – I
CMOS TECHNOLOGY
PART - A ( 2 marks)
PART-B
1. Explain the silicon semiconductor technology with various processes that are involved in
the sae. (16)
2. Differentiate the p-well CMOS process from n-well CMOS process. Explain the n-well
CMOS process to fabricate the n-switches. (16)
PART-B
All questions – Sixteen Marks:
1. Explain the n MOS and p MOS enhancement transistor with its physical structure.(16)
2. Derive and explain the
(I) Threshold voltage equation, (8)
(II) MOS DC equation. (8)
3. Explain that how the MOS transistor is to be analysed by the small scale models. (16)
UNIT – III
SPECIFICATION USING VERILOG HDL
PART - A ( 2 marks)
1. Explain the process flow that is followed to develop a project by any HDL with
example. (16)
2. Differentiate the various modes to develop the project and explain them with an
example. (16)
3. Develop the project using HDL to realize the function of a ripple carry adder and draw
its RTL. (16)
4. Design and develop a project in HDL to compare x5x4x3x2x1x0 with y5y4y3y2y1y0. (16)
5. Design a full adder by cascading two half adders and develop a project to realize it in
model simulator 6.0. (16)
6. Design and develop a HDL project in structural model to realize the priority
encoder. (16)
UNIT – IV
CMOS CHIP DESIGN
PART - A ( 2 marks)
PART-B
UNIT – V
CMOS TESTING
PART - A ( 2 marks)
2. List out all the methods of design strategies for test and explain any three methods. (16)
3. With the help of IEEE1149 BSA and TAPA explain the system level test technique. (16)
4. (i) How do you find IDDQ ?. Explain the same. (8)
(ii) Draw and explain the Data path test scheme for chip
level test methods. (8)
5. Write short notes on “need for CMOS testing”.