MJE:-V508T1Mi-V588T

M)(-V.5D8T/M)(-V588T

Contents

Area Suffix

U -------- Other Areas US -------- Singapore UT -- ---- -----. Taiwan US ------. Hong Kong UF ------------- China

DIGITAL AUDIO

[Q]o~m

DIGITAL AUDIO

[GRAPHICS)

[Q]o~m

[DIGITAL VIDEO)

PlayBack

Control

Safety Precautions ----------------------- 1-2 Instruction Book --------------------------- 1-4-27 Description of Major ICs ---------------- 2-1 Internal Connection of FL Display --- 2-16 Removal of Main Parts ------------------ 2-17 Flow of Functional Operation

Until TOC Read ---------- 2-30 Maintenance of Laser Pickup ---------- 2-31

Replacement of Laser Pickup ---------- 2-31 Main Adjustment -------------------------- 2-32

Self Diagnosis Function of CD --------·2-36 Block Diagrams - --. ----. - -- .-- - --. ------ - - 2-38 Schematic Diagrams --------------------- 2-39 Printed Circuit Boards ------------------- 2-49-55 Parts List -.-------.--------------------.----- 3-1-27

COPYRIGHT © 1998 VICTOR COMPANY OF JAPAN, LTD.

NO.20714 Aug. 1998

MX-V508T/MX-V588T

Description of Major ICs

• UPD7S044FGF-DS9(IC701 ):System Control Micon

1 . Trminal Layout 80 .... 65

1 l 24

64 l 41

25

40

2.Pin Function

Pin No. Symbol 1/0 Function Pin No. Symbol 1/0 Function
1-7 7G-1G 0 FL Grid control signal 39 +BCTL 0 5V switch
8 VDD - Power supply +5V 40 MRESET 0 Reset signal output.
9 SCKO 0 Serial Clock (PLL.SLC.VoI.C3) 41 OSCK 0 Clock signal to IC106
10 SDATAO 0 Serial data (PLL.SLC.VoI.C3) 42 OSCS 0 Chip select signal to IC106
11 FAUX 0 AUX Indicator control 43 OSD 0 Micon command data to IC251
12 LED TAPE 0 TAPE Indicator control 44 DSPSTB 0 Strobe changer control
13 SLC-STTA 0 Strobe Tape control 45 OS DATA 0 OS Data to IC106
14 MCLK 0 Sub code clock
15 MCMND 0 CD Mecha command data 46 POUT 0 Power on/off
16 MSTAT I Sub code data 47 REM I Remote control
17 REST I System reset signal 48 ICVss - To ground
18 PHOTO A I Tape A mechanism running detection 49 SMUTE 0 System mute
19 PHOTO B I Tape B mechanism running detection 50 MRDY 0 Ready signal to IC251
20 AVss - AD Ground 51 F.TU 0 Function TUNER
21 NC I TEST (Normally 'H') 52 Vdd - Power supply +5V
22 SAFETY1 I Trouble detection 53 VOL- I Volume encorder input (-)
23 SLC KEY3 I Tape A playback detect switch 54 VOL+ I Volume encorder input (+)
24 SLC KEY2 I Tape B playback detect switch 55 SPK 0 Speaker relay control signal
25 SLC KEY1 I Tape B playback/REC detect switch 56 PROTECTOR I Protector input
26-28 KEY3-1 I Key matrix input 57 BACKUP I Backup detect
29 AVdd - AD+5V 58 LATCH 0 Latch signal to IC302
30 AVREF - AD REF + 5V 59 PE~D 0 Tuner PLL strobe
31 XT1 I Sub clock 32.768kHz 60-70 S1-S11 0 FL segment control signal
32 XT2 0 Sub clock 32.768kHz 71 VLOAD - Supply voltage for FL drive
33 Vss - To ground 72-76 S12-S16 0 FL segment control signal
34 X1 I Main clock 4.19MHz 77-79 11G1-9G1 0 FL grid control signal
35 X2 0 Main clock 4.19MHz 80 8G 0 FL grid control signal
36 BEAT 0 Main clock shift
37 MSI I Music scan
38 MPX I Stereo detect 2-1

MX-V508T/MX-V588T

• AN8806SB(IC601):RF&Servo AMP

1.Treminal Layout

PD lD lDON lDP VCC RF-

RFOUT RF IN C.AGC ARF C.ENV C.EA CSBDO BDO CS BRT OFTR INRFDET GND

1 \_) 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19 PDAC PDBD PDF PDE PDER PDFR TBAl FBAl EFEFOUT TETEOUT CROSS TE BPF VDET lDOFF VREF ENV

2.Block Diagram

2-2

MX-V508T/MX-V588T

3. Functions

Pin No. Symbol 1/0 Functions and operations
1 PO I APC amp input terminal
2 LO 0 APC amp output terminal
3 LOON I APC ON/OFF control terminal
4 LOP -- Connect to ground
5 VCC -- Power supply
6 RF- I Inverse input pin for RF amp
7 RFOUT 0 RFamp output
8 RF IN I RF input
9 C.AGC 1/0 Connecting pin of AGC loop filter
10 ARF 0 RF output
11 C.ENV 1/0 A capacitor is connected to this terminal to detect the envelope of RF signal
12 C.EA 1/0 A capacitor is connected to this terminal to detect the envelope of RF signal
13 CSBOO I/O A capacitor is connected to detect the lower envelope of RF signal
14 BOO 0 BDO output pin
15 CS BRT 1/0 A capacitor is connected to detect the lower envelope of RF signal
16 OFTR 0 Of-track status signal output
17 /NRFDET 0 RF detection signal output
18 GNO -- Ground
19 ENV 0 Envelope output
20 VREF 0 Reference voltage output
21 LDOFF -- Connect to ground
22 VDET 0 Vibration detection signal output
23 TE BPF I Input pin of tracking error through BPF
24 CROSS 0 Tracking error cross output
25 TEOUT 0 Tracking error signal output
26 TE- I Inverse input pin for tracking error amp
27 FE OUT 0 Output pin of focus error
28 FE- I Inverse input pin for focus error amp
29 FBAL I Focus balance control
30 TBAL I Tracking balance control
31 PDFR 1/0 F I-Vamp gain control
32 PDER 1/0 E I-Vamp gain control
33 PDF I I-Vamp input
34 PDE I I-Vamp input
35 PDBD I I-Vamp input
36 PDAC I I-Vamp input 2-3

MX-V508T/MX-V588T

• BH3854AS(IC302):VOLUMElEQUALIZER

1.Block Diagram
II:
III
.. N N N N N N N N
~ Z Ir. Z Z 0 Z 0 .. o o U 11:
Z > > > ~ > .. CD U
Ir. CD CD .. .. 0 0 ... ... ... ... ... .. ... N .., • 0
z ... u .. .. .. ..
01 z ... z z 0 z 0 .. u U II: II: II: II: Z
Ir. > - > > ~ > In 0
Z CD CD CD .. .. 0 0 0 0 0 ,
< Do Do Do Do 0
2.Pin Function Pin Symbol Function Pin Symbol I/O Function
No. I/O No.
1 AGND - Analog system ground. 18 LATCH I Receive latch data.
2 IN1 I 1 ch volume input. 19 DATA I Termianl to receive data.
3 NF1 - Non connect 20 ClK I Terminal to receive clock.
4 BVN1 - 1ch low-frequency filter. 21-23 BC,TC,VC - Time constant attachment for switching
5 BIN1 - 1ch low-frequency filter. shock protection.
6 BV01 - 1 ch low-frequency filter. 24 OUT2 0 2ch volume output.
7 TIN1 - 1 ch High-frequency filter. 25 TV02 - 2ch high-frequency filter.
8 TV01 - 1 ch High-frequency filter. 26 TIN2 - 2ch high-frequency filter.
9 OUT1 0 1 ch volume output. 27 BV02 - 2ch low-frequency filter.
10 VCC - Terminal for power supply. 28 BIN2 - 2ch low-frequency filter.
11 SC - Time constant attachment for switching 29 BVN2 - 2ch low-freauency filter.
shock protection. 30 NF2 - Non connect.
12-15 PORT1-4 0 Terminal for port output. 31 IN2 0 2ch volume output.
16 DGND - Digital system ground. 32 FilTER I Terminal for filter.
17 VREF I 3.8V reference voltage output. 2-4

MX-V508T/MX-V588T

.BU1424K(IC104):Digital RGB Encoder

1.Terminal Layout
16 ..., 1
17 64 RO
l l GO/Y
32 49 BO/tN
33 ..., 48 ~u.K
RSl"B ;; w ;: i

e e e :ii

~.-.-.-.-.. -.~ .. _---_._._._._._-_.-.-._._._.-._._._._._.-

2.Block Diagram

_ PNlii; _!HS'I' _!'S'i

I

J+-=====~======~------------~---j~

I

-.-.-.-.-.-.-r-·l-l·~·-l-l-l-r-·l-}·-·-·-·-.-.-.-.-._.J

vocr \n.T ccer

3.Pin Function

Pin No. Symbol I/O Function Pin No. Symbol I/O Function
1 BOSD I OSD blue data input. 33 SLABEB Select master/slave.
2 YO I Green data BitO (LSB). 34 ADDH +0.5/-0.5 line at Non-Inter.
3 Y1 I Green data Bit1. 35 VREF - DAC Bias.
4 Y2 I Green data Bit2. 36 CGND - Chroma output ground.
5 Y3 I Green data Bit3. 37 COUT 0 Chroma output.
6 Y4 I Green data Bit4. 38 VGND - Composite output ground.
7 Y5 I Green data Bit5. 39 VOUT 0 Composite output.
8 Y6 I Green data Bit6. 40 AVSS - Analog ground (DAC,VREF).
9 GND Digital Ground. 41 AVDD - Analog (DAC) VDD.
10 Y7 Green data Bit7 (MSB). 42 IR I Reference resistor.
11 CO Blue data BitO (LSB). 43 AVDD - Analog (VREF) VDD.
12 C1 Blue data Bit1 (LSB). 44 YGND - Luminance output ground.
13 C2 Blue data Bit2 (LSB). 45 YOUT 0 Luminance output.
14 C3 Blue data Bit3 (LSB). 46 G4FSC 4FSC/32FSC at PALCD-G.
15 OSDSW OSD Enable/Disable. 47 GCLK Y-FILSEL THROU/FILON2
16 CDGSWB Select Video-CD(H)/CD-G(L). 48 YCDFF DAC (YOUT,COUT) OFF.
17 C4 Blue data Bit4 (LSB). 49 YFILON Y-FILSEL THROUIFILON1
18 C5 Blue data Bit5 (LSB). 50 PAL60B Normal/pal60 at palmode.
19 C6 Blue data Bit6 (LSB). 51 VCLK I Video clock input.
20 C7 Blue data Bit7 (LSB). 52 RSTB I Normal/ Reset.
21 GND - Digital Ground. 53 CLKSW SEL 1 CLKl2CLK.
22 NTB - Select NTSC/PAL Mode. 54 RDO I Red data BitO (LSB).
23 IMO I Select YUV /RGB. 55 RD1 I Red data Bit1 .
24 IM1 I Select DAC/NORMAL. 56 RD2 I Red data Bit2.
25 TEST1 - Normally pull down to GND. 57 ROSD I OSD red data input.
26 TEST2 - Select UN timing. 58 RD3 I Red data Bit3.
27 CVSY I/O V-SYNC input or output. 59 RD4 I Red data Bit4.
28 HSY I/O H-SYNC input or output. 60 RD5 I Red data Bit5.
29 PIXCLK - 1/2freq of BCLK. 61 VDD - Digital VDD.
30 BLKB 0 Internal clock output. 62 RD6 I Red data Bit6.
31 VDD - Digital VDD. 63 RD7 I Red data Bit7.
32 INT Interalce/Non interlace 64 GOSD I OSD green data input. 2-5

MX-V508T/MX-V588T

II BU2173F(IC1 05)

1.Terminal Layout

VDD TSTO XTALI XTALO CTRLA CTRLB CTRLC

TSTI VSS

2-6

1 18
2 17
3 16
4 15
5 14
6 13
7 12
8 11
9 10 3.Pin function

2.Block diagrams
XTA.I
AVDD FWT4
XTIlO 137!iHz
FPUT4 13. 3Itiz
VDDIO
FOUT1
TEST


FOUT2
VSSIO

FOUT3
AVSS FWT2

or

01'
ClR_C

CllUI A\l(l AVSS \l(l Io6S \l(lIO Io6SIO TBT TSTI rS10 RlJT3

Pin No. Symbol 1/0 Function
1 VDD - Digital VDD.
2 TSTO Use open this pin for normal operation.
3 XTALI I Reference oscillation input.
4 XTALO 0 Reference oscillation output.
5 CTRLA Frequency select for V-CD/CD-G.
6 CTRLB Force H for normal operation.
7 CTRLC PAUNTSC select for CD-G mode.
8 TSTI Force L for normal operation.
9 VSS - Digital GND.
10 AVSS - Analog GND.
11 FOUT3 Use open this pin for normal operation.
12 VSSIO - 1/0 GND.
13 FOUT2 0 Clock output (2).
14 TEST Force L for normal operation.
15 FOUT1 0 Clock output (1).
16 VDDIO - I/OVDD.
17 FOUT4 0 Clock output (4).
18 AVDD - Analog VDD. • BU4094BCF(IC304,IC303):SERIAL TO PARALLEL PROT EXTENSION

1.Terminal Layout

2.Block Diagram

STOROBE DATA

CLOCK 01 02 03 04 Vss

1 16
2 15
3 14
4 13
5 12
6 11
7 10
8 9 O's Os

Vdd

OUTPUT ENABLE 05

Q6

07

08

DATA CLOCK


2 10
8-STAGE
3 SHIFT REGISTER 9
)
~J
1 8-BIT
LATHES
~t
15 3-STATE
\ OUTPUTS
011 081
~ ~ STROBE

OUTPUT ENABLE

PARALLEL OUTPUT

• BA6897FP-W(IC801 ):4channel driver

CH1-INA 3 CH1-INB 4

CH2-INA 10 CH2-0UTB 11

,-----116 OP IN(+) .-----115 OP IN(-)

MX-V508T/MX-V588T

OlsISER'AL Os OUTPUT

2-7

MX-V508T/MX-V588T

• CL4SG-F1 (IC1 01 ):MPEG-1 AUDIONIDEO DECODER

Pin No. Symbol 1/0 Function Pin No. Symbol 1/0 Function
1 HA2 I Host address. 78-80 VD10-12 0 Video data terminal(G24IY24)
2 DS I Data strobe terminal. 81 IOVDD - Power supply for Input/Output.
3 W/R I I/O read terminal. 82-84 VD13-15 0 Video data terminal(G57IY57)
4 IRQ 0 Interact terminal. 85 CKTVSS - Connect to GND.
5 DTACK 0 Acknowledge data output. 86-89 VD16-19 0 Video data terminal(BOB3)
6 HDO I/O Host data terminal. 90 IOVSS - Ground terminal for Input/Output.
7 IOVDD - Power supply for input/output. 91-94 VD20-23 0 Video data terminal(B47)
8,9 HD1,2 I/O Host data terminal. 95 VSYNC I/O Vertical comparator/Composite
10 CKTVSS - Connected to GND. comparator output.
11-15 HD3-7 I/O Date data terminal. 96 HSYNC I/O Horizonatall synchronizing signal.
16 IOVSS - Ground terminal for Input/Output. 97 VOE I Video output enable signal.
17 TEST I Test terminal. 98 VCOVDD - Power supply of VCO.
18 XTLVSS I Oscillator ground terminal. 99 VCLK I/O Video clock terminal.
19 XTLiN I Oscillator input terminal. 100 VCOVSS - Ground of VCO.
20 XTLOUT 0 Oscillator output terminal. 101 RESET I Reset signal input.
21 XTLVDD - Power supply for oscillator. 102 IOVSS - Ground terminal for Input/Output.
22 CKTVDD - Power supply. 103 C2PO I Data error flag input.
23-28 MDO-5 I/O DRAM data / ROM data terminal. 104 CDLRCK I UR word clock input.
29 IOVDD - Power supply for Input/Output. 105 CDDATA I Bit serial data input.
30,31 MD6,7 I/O DRAM data/ROM data terminal. 106 CDBCK I Bit clock output.
32,33 MCE01 0 Chip enable output for ROM bank. 107 DALRCK 0 UR clock output.
34-37 MD8-11 I/O DRAM data/ROM data terminal. 108 DADATA 0 Bit serial PCM audio signal output.
38 IOVSS - Ground terminal for Input/Output. 109 DABCK 0 Bit clock output.
39-42 MD12-15 I/O DRAM data/ROM address terminal. 110 IOVDD - Power supply for Input/Output.
43 5VVDD - Power supply(+5V). 111 XCK I Bit clock input terminal.
44 LCAS 0 DRAM LCAS/ROM address terminal. 112 ·CKTVDD - Power supply.
45 LCASIN I DRAM LCAS input. 113 PI012 0 Interact 2 signal output.
46 CKTVSS - Connect to GND. 114 PI011 0 Non connect.
47 MWE 0 DRAM write enable signal output. 115 PI010 I Host enable signal input.
48 UCAS 0 DRAM UCAS/ROM address terminal. 116 PI09 I Boot ROM enable signal input.
49 IOVDD - Power supply for Input/Output. 117 PI08 0 Non connect.
50 UCASIN DRAM UCAS input terminal. 118 PI07 0 DAC emphasis signal output.
51,52 RASO,1 0 DRAM RASO,1 terminal. 119 PI06 I CD-DA emphasis signal output.
53-57 MA9-5 0 DRAM data/ROM address terminal. 120 PI05 0 Non connect.
58 IOVSS - Ground terminal for Input/Output. 121 PI04 0 FMV detect signal output.
59-63 MA4-0 0 DRAM data/ROM address terminal. 122 PI03 0 CD-DA video CD select signal
64 PIOO 0 ROM address extension terminal. output Low:Video CD.
65 IOVDD - Power supply for Input/output. 123 5VVDD - Power supply (+5V).
66-72 VDO-6 0 Video data terminal 124 PI02 0 Non connect.
(R6/CrCb6IYCrCb066) 125 IOVSS - Ground for Input/Output.
73 IOVSS - Ground terminal for Input/Output. 126 PI01 0 Non connect.
74-76 VD7-9 0 Video data terminal 127 HAO - Host address input.
(R7/CrCb7IYCrCb7)(GO,1IYO,1 ) 128 HA1 - Host address input.
77 CKTVDD - Power supply. 2-8

MX-V508T/MX-V588T

• LC72136N(IC2):PLL Frequency sinsesizer LSI 1. Layout

XT 1 <:» 22 TI

FM/AM 2 21 GNO

CE 3 20 LPFOUT

01 4 19 LPFIN

CLOCK 5 18 PO

DO 6 17 VCC

FM/STNCO 7 16 FMIN

AM/FM 8 15 AMIN

9 14

10 13 IFCONT

SOIN 11 12 IFIN

2. Block

r----------------------------------------------,

I

Data Shift Register & Latch

1 --------

7

3. Function

Pin Function Pin
No. Symbol 110 No. Symbol 110 Function
1 XT I X'tal oscillator connect (75KHz) 12 IFIN I IF counter signal input
- 0 LOW:FMmode 13 I FCONT 0 IF signal output
2 FM/AM
3 CE I When data outputlinput for 4pin(input) and 14 - Not use
6pin(output): H
4 01 I Input for receive the sirisl data from 15 AMIN I AM Local OSC signal output
controller
5 CLOCK I Sync signal input use 16 FMIN I FM Local OSC signal input
6 DO 0 Data output for Controller 17 VCC - Power suplly(VDD=4.5-5.5V)
Output port When power ON:Reset circuit move
7 FM/STNCC 0 'Low": MW mode 18 PO 0 PLL charge pump output(H: Local OSC
frequency Height than Reference frequency.
L: Low Agreement: Height impedance)
8 AM/FM 0 Not use 19 LPFIN I Input for active lowpassfilter of PLL
9 - Not use 20 LPFOUT 0 Output for active lowpassfilter of PLL
10 - I nput/output port 21 GND - Connected to GND
11 SDIN 1/0 Data input/output 22 XT I X'tal osciliator(75KHz) 2-9

MX-V508T/MX-V588T

•• LH531 HEG(IC1 02)

2.Block diagram

1.Terminal Layout

VCC A18 A17 A14 A13 A8 A9 All CE Al0 CE D7 D6 D5 D4 D3

A162 A15 3 A14 A13 A12 4 All Al0 A9 A8 A7 A6 A5 7 A4 8 A3 9 A2 1 Al 1 AO 1

a::

UJ o o o UJ o en

C/)

UJ a:: o o -c

MEMORY MATRIX

(131,072 X 8bit)

VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 Al AO DO Dl D2

GND

1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17 CE

vee

3.Pin Function

Pin No. Symbol 1/0 Function
1 VPP - Power supply.
2 A16 I Adress input.
3 A15 I Adress input.
4 A12 I Adress input.
5 .... 12 A7AO I Adress input.
13 .... 15 DOD2 0 Data output.
16 GND - Connect to GND
17 .... 21 D3D7 0 Data output.
22 CE I Chip enable input.
23 A10 I Adress input.
24 CE I Chip enable input.
25 A11 I Adress input.
26,27 A9,A8 I Adress input.
28,29 A13,A14 I Adress input.
30,31 D17,D18 0 Data output.
32 VCC - Power supply. 2-10

MX-V508T/MX-V588T

II MN171601 AK8J2(IClll ):HOST Micro Computer 1.Terminal Layout

1 l 16

48 l 33

64 ,... 49

17 ,... 32

2.Pin Function

Pin No. Symbol 1/0 Function
1 480RST 0 Reset signal output.
2 MREQ I Input the transfer request data signal.
3 ACTINT I Interact 2 signal input.
4 GDET I CD-G detect terminal H:CD-G
5 GND - Connected to GND.
6 DTACK I Acknowledge signal input.
7 GND - Connect to GND.
8 GND - Connect to GND.
9 DIR 1/0 Input/Output control for IC114.
10 N/PAL - Not use.
11 RGB 0 Video out control signal (H:RGB L:composite)
12 W/R 1/0 ReadIWrite signal input/output.
13""15 HA02 0 Address signal output for MPEG LSI.
16 DS 0 Data strobe signal output.
17""24 HD07 1/0 Data terminal for MPEG LSI.
25 ...... 39 SA014 0 SRAM address signal output.
40 SCS 0 SRAM chip select signal output.
41 ""48 SD18 1/0 SRAM data Input/Output terminal.
49 SRIW 110 SRAM readlwrite signal input/output.
50 PAL60 - Not use.
51 RESET I Reset signal input.
52 X1 - Non connect
53 X2 - Non connect.
54 VSS - Connect to GND.
55 OSC2 - Non connect.
56 OSC1 I Clock input terminal.
57 VDD - Power supply.
58 HREQ 0 Communication signal output.
59 SRCLK 0 Clock signal for data request.
60 M2HDT 0 Serial data output.
61 M2MDT I Serial data input.
62 HRDY 0 Communication signal output.
63 VCD/G 0 Video swith switching signal output.
64 PALCDG 0 CD-G PAUNTSC clock select terminal. 2-11

MX-V508T/MX-V588T

1. Terminal Layout

• MN35510(IC651):DIGITAL SERVO&DIGITAL SIGNAL PROCESSER

2.Block Diagram

LRCKIN(MSEL BCLK(SSEL SRDATAIN (PSEL

IOSEL CLVS CRC BLKCK CLDCK SBCK

SUBC DEMPH RESY

FLAG6(RESY

SSEL saCK SUBa

AVDD2

AVDD2 PCK EFM PLLF

DSLF IREF DRF ARF

RSEL PSEL

MLD

MCLK MDATA

CK384(EFM VCOF

BYTCK SMCK FCLK CSEL MSEL

X2 X1

ESTA

2-12

20 - 1

21

80

40

61

41 - 60

rih
-
)- PEM u,
) _ DIGITAL f---+ 8TIMES f-+ (R) _;," =:= I:: L..:,:.:., I -
OVER SAMPUNC f-
) ir DEEMPHSIS DIGITAL FILTER 1BIT ,., "" I ~.~Io •• r-
DAC .. I ....
LOGIC ~~
- S
PEM
r-
(L) I:: =:= m L..:,:.:., I

I ••
.....____ u~ ., ,., I ....
YK
I


)

- SUB
.: CODE f- EFM DIGITAL
- BUFFER DEMODULATION ~ ~ AUDIO
INTERFASE
-+ SYNC
INTERPOLATION -f+
:: DIGITAL
SUBCODE AUDIO
..... DSL. DEMODULATION INTERFASE
::
PLL -+ CIRC
-+ VCO ERROR
-+ CORRECTION '-- INTER POLATION
-+ DEINTERLEVE SOFT MUTING DIGITAL
- ATTENUATION
PEAK DETECTIVE
AUTO CUE
t ~


):=.. I vcol MICRO CLV I
- COMPUTER SERVO I
:: INTERFACE
ITUNING I D/A II
---'I GENERATION CONVERTER
---'I PITCH

---'I CONTROL
---'I




OUTPUT PORT

I I

I AID INPUT I SERVO
COVERTER TIMING GENERATOR
t t t t t t t t t t t t V V D D I I DS VVRT D S D SSE

D S T S 1 1 T

F T R

E E F

E N V

T V R D

C E

R T S

B D o

I R F D E

o F T

AVSS1 AVDD1 OUTR

OUTL

FLAG IPFLAG

TX

ECM

PC

LRCK SRDATA BCLK DMUTE

TRKV KICK VREF TRVSTR ECS TVD TRD FOD TBAL FBAL TOFS TES ITLOCK IFLOCK PLAY LDON WVEL SENSE

MX-V508T/MX-V588T

3 D

escnotlon
Pin 1/0 Pin 1/0 Description
No. symbol Description No. symbol
1 BCLK 0 Not used 41 TES 0 Tracking error shunt signal output(H:shunt)
2 LRCK 0 Not used 42 PLAY - Not used
3 SRDATA 0 Not used 43 WVEL - Not used
4 DVDD1 - Power supply (Digital) 44 ARF I RF signal input
5 DVSS1 - Connected to GND 45 IREF I Reference current input pin
6 TX 0 Digital audio interface output 46 DRF I Bias pin for DSL
7 MCLK I JJ. com command clock signal input 47 DSLF I/O Loop filter pin for DSL
(Data is latched at signal's rising point)
8 MDATA I JJ. com command data input 48 PLLF 1/0 Loop filter pin for PLL
9 MLD I JJ. com command load signal input 49 VCOF - Not used
10 SENSE 0 Sence signal output 50 AVDD2 - Power supply(Analog)
11 FLOCK 0 Focus lock signal output Active :Low 51 AVSS2 - Connected to GND(Analog)
12 TLOCK 0 Tracking lock signal output Active :Low 52 EFM - Not used
13 BLKCK 0 sub-code' block· clock signal output 53 PCK - Not used
14 SaCK I Outside clock for sub-code a resister input 54 PDO - Not used
15 SUBa 0 Sub-code a -code output 55 SUBC - Not used
16 DMUTE - Connected to GND 56 SBCK - Not used
17 STATUS 0 Status signal 57 VSS - Connected to GND(for X'tal oscillation
(CRC,CUE,CL VS,TTSTOP ,ECLV,SaOK) circuit)
18 RST I Reset signal input (L:Reset) 58 XI I Input of 16.9344MHz X'tal oscillation circuit
19 SMCK - Not used 59 X2 0 Output of X'tal oscillation circuit
20 PMCK - Not used 60 VDD - Power supply(for X'tal cscillation circuit)
21 TRV 0 Traverse enforced output 61 BYTCK - Not used
22 TVD 0 Traverse drive output 62 CLDCK - Not used
23 PC - Not used 63 FLAG - Not used
24 ECM 0 Spindle motor drive signal (Enforced 64 IPPLAG - Not used
mode output) 3-State
25 ECS 0 Spindle motor drive signal (Servo error 65 FLAG - Not used
signal output)
26 KICK 0 Kick pulse output 66 CLVS - Not used
27 TRD 0 Tracking drive output 67 CRC - Not used
28 FOD 0 Focus drive output 68 DEMPH Not used
29 VREF I Reference voltage input pin for D/A 69 RESY - Not used
output block (TVD,FOD,FBA,TBAL)
30 FBAL 0 Focus Balance adjust signal output 70 IOSEL - pull up
31 TBAL 0 Tracking Balance adjust signal output 71 TEST - pull up
32 FE I Focus error signal input(Analog input) 72 AVDD1 - Power supply(Digital)
33 TE I Tracking error signal input(Analog input) 73 OUTL 0 Lch audio output
34 RFENV I RF envelope signal input(Analog input) 74 AVSS1 - Connected to GND
35 VDET I Vibration detect signal input(H:detect) 75 OUTR 0 Rch audio output
36 OFT I Off track signal input(H:off track) 76 RSEL - pull up
37 TRCRS I Track cross signal input 77 CSEL - Connected to GND
38 RFDET I RF detect signal input(L:detect) 78 PSEL - Connected to GND
39 BDO I BDO input pin(L:detect) 79 MSEL - Connected to GND
40 LDON 0 Laser ON signal output(H:on) 80 SSEL - Pull up 2-13

MX-V508T/MX-V588T

• TA2057N(IC1):FM/AM IF AMP & Detector

1.Block Diagrams

Vstb

AM IF IN QUAD

AM OUT MPXIN

LPF 1

LPF2

VCO

AM RF IN AM S.SENS FM S.SENS AM OSC AM OSC OUT VCC

AGC

GND

OUi~EQ TUNER LED ST LED

ROUT

2.Pin Function

Pin Pin
No. 1/0 Symbol Function No. 1/0 Symbol Function
1 I AMRF AMRF signal input 13 0 Lch OUT Output Lch
2 AM S.SENS 14 0 VCO Voltage controlled terminal
3 FM S.SENS 15 0 LPF2 When voltage of terminal is MONO
4 - AMOSC AM local oscillation circuit at "H' and ST at 'L'
5 0 AMOSCOUT AM local oscillation signal output 16 0 LPF1 When voltage of terminal is AM at
6 - VCC Power supply 'H' and FM at 'L'
7 I AGC AGC voltage input terminal 17 I MPXIN Multi plex signal input
8 - GND Connect to GND 18 0 AM OUT AM detection signal output
9 0 IFOUT IF REO signal output to IC2 19 0 FMOUT FM detection signal output
10 0 TUIND Indicator drive output when tuning 20 I FMOUAD Bypass to FMIF
11 0 STIND Stereo indicator output 21 I AMIFIN Input of AMIF signal
'H'mono. 'L'stereo 22 - Vst Fixed voltage output terminal
12 0 Rch OUT Output Rch 23 0 AM MIX OUT Output terminal for AM mixer
24 I FM IFIN Input of FMIF signal 2-14

MX-V508T/MX-V588T

.TA8409S(IC851.IC852):Motor Driver 1.Block Diagram

I ~C_ _

I; Standby l

circuit I

I I I

--+- ~ I

I I

-----_j

2.Function

INPUT OUTPUT MODE
IN1 IN2 OUT1 OUT2 MOTOR
0 0 00 00 STOP
1 0 H L CW/CCW
0 1 L H CCW/CW
1 1 L L BRAKE 2-15

MX-V508T/MX-V588T

Internal Connections for FL Display Tube IIIQLF0047-001 (FL701)

Grid Assignment

9G 8G 7G

5G

5G

4G

3G

2G

1G

I I I I I I I I L
~~~ 0(0;0 110(0;0 118~O 1/ uiu fljOZU 1~'iOlU 118~0 110(0;0
~ UliOl UliOj UliOj UtijU I. UtijU j D°,DtijUj UliO/, u1o~ ~Ha:
(6~~ = MH~

~ <JC> 0000 (WJ~©) ~ [ ~oM~~ ~~ JJ [ ~o~©[Q)~ ~
g~l) cosr. ~~~[Q)OM (( ~ d) .o lr~ !Nl!EW~ ~[N]fO E()N
~ ~ ~ll PAGM CClOCC~ ~ RIECC 3llE[E[pJ MO~O ~lr
51 I___" 510-
I I 11 G

a

'u1!ub V~"Uc

d (8G----1G)

10G

ANODE CONNECT10N

<. llG 10G 9G 8G 7G 6G 5G 4G 3G 2G lG
PI <J ~ 1) d d d d d d d d
P2 C> ~ 51 n n n n n n n n
-
P3 ~ ((A.8ASS.EX~ S2 p p p p p p p P
P4 00 ~.~~~ 53 r r r r r r r r
P5 ~~) I (S.MODEJ) &l e e e e e e e e
P6 COOT. ~o~ S4 c c c c c c c c
P7 RANOOM 0 55 9 9 9 9 9 9 9 9
P8 c VA S6 m m m m m m m m
P9 =C> fNJlf:WS ~ f f f f f f f f
<>=
P10 2) ~fNJfO 57 b b b b b b b b
Pll ~ !£ON 58 k k k k k k k k
P12 All REC S9 j j j j j j j j
~-
P13 PRGM SLEEP - h h h h h h h h
P14 ClOC~ MONO - a a a a a a a a
P15 511 ST - - - - - - coO - ~H71
--_.
P16 - 510 - - - - - - Dp - ~~ 2-16

MX-V508T/MX-V588T

Self OiagnosisFunction of eo

1. Purpose

This function is designed to display an error to readily clarify the cause of such an error should any trouble occur in CD.

2. How to Use the Function

(1) Turn the microcomruter1action of the set to [TEST] mode.

(2) Press I CDSTOpl + +10 +IPOWERlon the remote control same time.

Confirm that all of the LCDs have been turned on when set to the [TEST] mode subsequent to the step in item (2).

(3) When the CD trouble has occurred after starting CD, an error code will be displayed on the display section of LCD, etc.

3. Error code and location in trouble

Error identified Flow charts Defective points Error identified Flow charts Defective points
time ~ time ~
t t

Effective only
During [TESll

( 3 sec timer J ErrS
NG- Servo system NG
Pickup NG

OK
Err1
Feed motor NG Err6
10 sec timer NG Reset switch NG 10 sec timer NG Servo system NG
GearNG Pickup NG
OK OK

( to sec timer J Err7
NG Servo system NG
Pickup NG
OK OK
~

OK
( 30 sec timer J NG
OK 2-36

Error identified time

+

Flow charts

~

y

y

y

y

MX-V508T/MX-V588T

DefectT points

Feed motor Motor

N - connection NG

GearNG

Y - Reset switch NG

Spindle motor

N - Motor connection NG

Tracking servo

N - Tracking actuator NG Pickup NG

N --1L L_a_s_e_rN_G ~

N - Focus actuator NG

2-37

MX-V508T/MX-V588T

• Block Diagrams

2-38

:-------------------M----------------~

, 1 ,

;:

OJ

'" ....

-c J: o W ~ Q. a:

.---.---.----- ...

-c J: o W ~ !D Q.

-----------------------------

,

1 -

II: o

o

~ II:

,------------------------------------------------.

,

VII.:!

, , ,

._-----------------------------------------------

7

Power Transformer Section

POWER SUPPLY BLOCK U/UB/UF/US/UT

AC110V/127V/220V/2 ~ 50/60Hz

6

5

4

3

2

r---- ---------------------------------------------

: I Frv1H-O 15-02

1

MAINS PLUG

Lt T999 FMTP66U8-65A

BRN

1

1,--------------.

: I Frv1H-O 15-03

------ 1

VOLTAGE SELECTOR LOCATION

1 1

------------- 1

AC220V

AC230 ~ 240V

AC110V

AC127V

A

E

B

c

o

'20V /230V-240V

MX-V508T/MX-V588T

U

UNIVERSAL EXCEPT ALL OF ABOVES

VERSION CODES

UB HONG KONG

UF CHINA

US SINGAPORE

UT TAIWAN

~ ~

AC110V/127V/ 220V/230V-240V - 50/60HZ

EXPLANATION OF OVERALL SCHEMATIC

MODEL

MX-V508T AND MX-V588T

SHEET MODEL
CIRCUITS DESCRIPTION
NUMBER NUMBER
1/10 MX-V508T PRIMARY CIRCUIT
MX-V588T
2/10 MX-V508T POWER AMP CIRCUIT
MX-V58BT
3/10 MX-V50BT PRE-AMP CIRCUIT
MX-V588T
4/10 MX-V508T MICON & FL DISPLAY CIRCUIT
MX-V588T
5/10 MX-V50BT MIC & HEADPHONE
MX-V588T
6/10 MX-V508T KARAOKE CONTROL CIRCUIT [DSP]
MX-V58BT
7/10 MX-V50BT CASSETE MECHA CONTROL CIRCUIT [SLC]
MX-V58BT
8/10 MX-V508T TUNER CONTROL CIRCUIT
MX-V588T
9/10 MX-V508T VIDEO CD CONTROL CIRCUIT
MX-V588T
10/10 MX-V508T CD CONTROL & SERVO CIRCUIT [VC3]
MX-V588T MODEL MX-V508T/MX-V588T

.&, Parts are safety assurance parts.

When replacing those parts make sure to use the specified one.

2-39

+
"
4. 7/50
6
§ "
0
0
Cl m
Cl m
OJ m
u IT 7

5

4

3

2

MX-V508T/MX-V588T

Power Amplifier & Regulator Section

r

C935

R950
ru
" "1 LD
rn
0 u -, '-l~:'
0 f r-.
-r +

R978

C9L

+-+-~,------'----It----R-9---4-'4'-:_- -- -+--+f--'--'''~~~~-~~~~~-'''''~''''''''''~::::~';;-~-+-'--''''~~~~--------::_-:::'-:::.=

"1- ---- .... -------1---------.--

821<

~I:--rl-i--I-++.----I-------I SW,3V REG

I

I

---- C}060800 0 1-- -

f-IW I- y: ~ (\J > l:J CN9G 1

1 :=J I- IT. 0- .._j __j lO <r B QG8252601-08 t[~Q(jjLLlL~

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CN900 QG82526Jl-"111?28c56~~f~61CO~ 11

<t HI-! 3:UlW

(f) (f) 8 (n :J ~

[f)

ro PRE-AMP CIRCUIT

TO PRE-AMP CIRCUIT

TO CN307 FMC-013A [SHEET

TO CN30B OF FMC-O 3A

~V10 1

A

D

E

B

c

2-40

FI938 R939 *1 ~ : 47011W] 1 0

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1
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0 0
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0 0 lSR139-20Q-T4

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-.-- ~ .. ----------------"I-------~·---F-""-I!,,'-, '-0-1 ;--L" ~" I

__ ~{['@~~, 'CMMW1031 ---

"W905

-08

NOTES

~ ~ EWR330-30LSV

SHEET 3/10J

011

TO CIRCUI

TO CN309 OF FMC-013A

OR :sov ~lYUR CAPACITOR.

.it. Parts are safety assurance parts.

When replacing those parts make sure to use the specified one.

_.... MAIN SIGNAL

CAPACITANCEi~F)/RATED VOLTAGE Ivf.

3/10 J

U., o

m m m :s: lJL

">

is IT 11.

6

Function & Main Amplifier Section

'voL"ml

I~

7

1-

I

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5

4

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1. VOLTAGES ARE I'IITH II DIGITAL VOLT

OR OSCILLOSCOPE \~ITHOUT Ir-,PUT SIGNAL

CONDITION --- CO MODE

VOLTAGE VALUE MARKED ;t 15 IN TUM,n POSITON

CN302 QGF1201C3~1O

FROM HICON SECTle

FROt<1 CN701 OF FMB ~1

TO CN405 OF SLC [SHEET 7/10 I

A

B

c

o

E

MX-V508T/MX-V588T

ITUNER REGI

0907 2SA1175ilWEI

1 pi
L____ 11
" .' MeMO

'0 NSTAT s

~~~~ ~

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r++·_t-+-+-++-H--H+-t-·--~--_,;;;;--~ j------

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OF" co BOMlO 1 SHEET 10/10)

CN316

TO TUNER SECTION

TO

l G2 ! I ( OJ

QGF1(:!O-lC3---17 1

_..,. CD/MAIN SIGNAL TAPE P.B. SIGNAL TUNER SIGNAL

> <0 tn :J

i-'-:r: 0 rr U 0 Q I- , ...

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FROM !>lICON SECTION

FROM CN702 I:::MB

4/10 I

F

G

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J

2-41

6

MX-V508T/MX-V588T

System controller & Operation Switch Section

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1. VOLTAGES ARE DC-MEASURED I'IITH A DIGITAL VOLT t.lETER OR OSCILLOSCOPE v/ITf-IOUT Ir-.1'\JT SIGNAL.

CONDIT ION re

2. UNlESS OTI-ER\~ISE SPECIFIED

RESISTORS N~E 1/41'1 ±5% CAP,SON F,[SISTOR VALUES ARE IN OH!~( 0).

Fiv1B~O 1

JOGIvOL I

I I ~ I ~ ~ I

I I

5<109

MODE~L

MX~V508T / MX~V588T

Ivi

7

6

5

4

3

2

Mic & Headphone Section

ICB52 1"-J,JM4580L

o

S

FW852

D1 r-, m IT

2.21<

m TO CN310 OF F

r-, "' m

u

A

B

c

121<

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m 0 u (\)

ru

" ~ to 0

m

0:

i.

VOLTAGES ARE DC-ME OR OSCILLOSCOPE WI CONDITION --- TAPE ( ) MEANS INVERT M

2. UNLESS OTHERWISE S i/4W ± 5% CARBON R ALL RESISTANCE VAL ALL CAPACITORS ARE OR MYLAR CAPAC TOR ALL CAPACITANCE VA ALL NDUCTANCE VAL ALL . CAPAC TORS A OF CAPACITANCE 1M ALL DIODES ARE iSS

3.91<

x MARK

~ L841/L842 C843/C844
C845/C846 C842
-
UT 47u 1000P 1000P
f---------
(JTHERS 30/6131 -- D

E

"25SLV

9V C

r

PRE-AMP CIRCUIT

310 OF FMC-013 ISHEET 3/10)

J80-00 1

FW851 LOUT GND ROUT

SPK SPK

E\~R35D-35LSV

FROM PO\~ER BOARD

MX-V508T/MX-V588T

FROM CN904 OF FMH-015-01 (SHEET 2/10J

C-MEASURED WITH A DIGITAL VOLT METER E WITHOUT INPUT Src3NAL_.

rAPE STOP MODE

RT MODE.

SE SPECIFIED. RES STORS ARE ,ON RESISTOR

VALUES ARE N OHMIc). ARE CERAMIC CAPACITOR TOR.

E VALUES ARE N ~FI F)

VALUES ARE IN ~Hlm=mH).

FiS NlE SHOWN N THE FORM

I ~ ) VOLTAGE I V).

1SS1

NODEL

MX-V508T/MX-V588T

F

G

H

J

2-43

7

6

5

4

3

2

DSP Section

MX-V508T/MX-V588T

r------------------------------------

-, n

n C

rJ1 In

o 0

M

--~(JO 1 A

FROM CN311 OF FMC-O

on OSCILLOSCOPE WITHOUT

MX-V5DElT

A

B

c

D

E

2-44

------j

FT~OM PRE-AMP Ll0ARD

FROM CN312 lJF FMC--O J:3 [SHEET3/10 l

-V5DElT/MX-V588T

F

G

H

J

7

Amplifier & Mechanism Control Section

I I

I

I

I

I

I

I

I

6

5

fl()RfI 75mA

CRD? 120'M

4

3

2

s'" :;'i; cesa "0"" • ~"

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I I I I I I I

L _

ARE DC-MEASURED WITH II

VOL T NETER IS INVERT rcoe

OR OSCILLOSCOPE I~ITHOUT INPlJT SIGNf,L.

2. UN:..ESS OTf-ERWISE SPECIFIED

ALL VALUES IN OHI·,(O I.

All CAPACITORS ARE CERANIC

ALL CAPACITANCE VALUES ARE IN INDUCTANCE VALUES ARE IN

Ap~l E.CAPACITORS ARE SHmlN IN THE FORr~ OF CAPACITANCE il,Fi/RATED VOLTAGE IVI. = Pl.YPROPYl.ENECAPACITOR

A

8

c

E

D

-------,

~

,L~ZX FA1L4MX FA.1A4lX I

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MX-V508T/MX-V588T

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MODEL MX-V508T/MX-V588T

F

G

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7

6

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DND AMI~(~- .. ~'k~~(----~--------------------------------------~--~---'

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R22 QAX0419- 330

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A

Co

Tr NO.

PIN NO.

_FM 87 ._5MHZ_~Q___ AM 531KHZ NO S

----_

B

c

o

E

2-46

L1

NOTES i.

DC-MEASURED WITH A DIGITAL,

CARBON RESISTOR.

VOL T METER.

ALl_ RESISTORS ARE 1/ 4W

3. ALl_ r~ESISTANCE VALUES ArlE IN OHM! Q I.

SHOWN

CAPASITANCE VALUES ARE IN t,FiP=pF).

DIDOES! 11>11 ARE ALL 155133T

I 4.

5.

I 6

I

!----

r'_____'--c'~~~Y----~-~- --<r--=-= - - - I

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FM

IN QUAD

DF

8.

OF DIGITAL TRANSISTORS ARE SHOWN AS FOLLOWS.

N (~r 18 bl c:::J II l-¢-J<;i

v

"T R ~ ~ [\1 c3

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OUT/CONTINO INC OUl

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OUT OUT

L-Cr-i OUT

r::-',:::.:~~+-+-.= ~~="" I TUNER GND

[c 18'1 4 'op TUNER R

ICi9! 4 'OP~,

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'-=;.....==========----j---+- TUNER +B DATA

MPX CI_OCI< PERIOD Vt/F'M+8

1'-'.pX LPF

IN 1

LPF 2

I~ lID m aJ 0 to In

t ~.,

x x z :z

TO PRE-AMP SE\CTION

I -!

FMITUNER MAIN SIGNAL AM SIGNAL

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