HDMI Mezzanine Card - Revision B: User's Guide


HDMI Mezzanine Card – Revision B


User’s Guide
September 2010
Revision: EB55_01.0
Lattice Semiconductor User’s Guide
Introduction
LatticeECP3 Video Protocol Board includes a daughter card connection to support applications that can be imple-
mented using SERDES. This daughter card connection includes three connectors for the signals of a whole
SERDES quad, the control/status signals and the power/ground pins.
The HDMI Mezzanine Card is a LatticeECP3 Video Protocol Board daughter card designed for demonstrating the
Lattice HDMI/DVI solution using LatticeECP3 SERDES. The scope of this user’s guide covers only revision B of the
HDMI Mezzanine Card. Please refer to EB52, LatticeECP3 Video Protocol Board Revision C User’s Guide for more
information about the LatticeECP3 device connection to the daughter card.
As shown in Figure 1, this card uses Single-Link 19-pin HDMI Type-A connectors. If using passive HDMI-to-DVI
cables, this card can also be used to support DVI video.
Figure 1. HDMI Mezzanine Card
Features
• Supports two different HDMI/DVI input paths, with or without the cable equalizer
• Supports HDMI/DVI output with TMDS level shifter
• TOSLINK fiber optic receiving module for S/PDIF audio input
• Headers for HPD, CEC controls and the EDID signals
• ESD protection devices for both HDMI/DVI inputs and HDMI/DVI outputs
Functional Description
There are four transmit channels and four receive channels in each of the LatticeECP3 SERDES quads. For imple-
menting a Single Link HDMI or DVI interface, which includes three data channels and one clock channel, all four
transmit channels and three receive channels are used. The clock channel on the receive side is connected to the
dedicated SERDES differential reference clock pins. Since the common mode voltage of the HDMI/DVI TMDS sig-
2
nals is different from the SERDES CML signals, and the TMDS coding scheme maintains the DC balance of the
signal, the AC coupling capacitors are used to block the DC component of the driving signal.
Figure 2 shows the functional block diagram of the HDMI Mezzanine Card. For validation purposes, this card is
designed to include two HDMI/DVI input ports. One of these input paths has a TMDS cable equalizer and the other
does not. The signals of both paths will go into the 2-to-1 TMDS MUX, then the AC coupling capacitors to the
SERDES input pins. Depending on which pins a shunt is installed on a 3-pin header, one of the two inputs will be
selected and the signals will be fed to the SERDES.
For meeting the HDMI/DVI’s strict electrical compliance test specification, a TMDS level shifter is added to the out-
put path. This level shifter can be removed if the design does not have this requirement. The ESD protector is
added on both the input and output HDMI/DVI ports. Other than the HDMI/DVI, an S/PDIF input interface is also
included for bringing in a digital audio stream through the TOSLINK connector.
Figure 2. Functional Block Diagram

Data Pairs
TMDS
Input 1
6 Equalizer 6 ESD
(STDVE001) Clock Protector
AC Coupling
Data Pairs 3.4 Gbps

TMDS 2 2
6 2:1 Switch
10 Gbps Mezzanine Connector
Clock (PI3HDMI1210-A)
4 Gbps Data Pairs
2
Input 2
6 ESD
Clock Protector
2 TMDS Clock
Data Pairs Data Pairs

AC Coupling
TMDS
Output
6 Level Shifter 6 ESD
Clock (STHDLS101T) Clock Protector
3.4 Gbps
2 2
Connector
Regular
100-mil
S/PDIF
TORX147
Figure 3 shows the HDMI Mezzanine Card installed on the LatticeECP3 Video Protocol Board. The two cables are
the HDMI cables connecting to J1 (HDMI/DVI input) and J3 (HDMI/DVI output) of the daughter card. A 12 mm tall
standoff is recommended for securing the HDMI Mezzanine Card on the LatticeECP3 Video Protocol Board
through screws.
3
Figure 3. HDMI Mezzanine Card Installed on the LatticeECP3 Video Protocol Board
Header Settings
This section describes the header settings on the HDMI Mezzanine Card. However, since the card uses SERDES
quad C when plugging into the LatticeECP3 Video Protocol Board, the VCCOB and the VCCIB of SERDES quad C
need to be powered properly. Please make sure shuts are installed on J18 and J22 of the LatticeECP3 Video Pro-
tocol Board.
As mentioned previously, the selection of the two HDMI/DVI inputs is done by a 3-pin header. Table 1 shows the
locations of where the shunt should be installed.
Table 1. MUX Selection Control

HDMI/DVI Shunt Installation
Input Mode MUX Select on H13
J1 Equalized HDMI/DVI Input High Pin 1/Pin 2
J2 Non-Equalized HDMI/DVI Input Low Pin 2/Pin 3
Other than the TMDS clock and data pairs, the HDMI/DVI interface includes CEC, HPD and the DDC clock and
data signals. By installing shuts on different locations of the 12 headers, these signals can be selected to be
bypassed from the HDMI/DVI input to the HDMI/DVI output, or they can be selected to be connected to the
LatticeECP3 FPGA on the LatticeECP3 Video Protocol Board.
Figure 4 shows the locations of these 12 headers on the HDMI Mezzanine Card and the signals these headers
control. The 12 headers are divided into four groups as shown in Figure 4. Each group includes three headers for
controlling one of the four signals. The black square is used to indicate pin 1 of each header.
4
Figure 4. Headers for CEC, HDP, S Settings, LatticeECP3 Video Protocol Board
J3 (HDMI Out) J3 (HDMI Out)
H12, H11, H10, H9

are associated with
HDMI Out
H12, H11, H10, H9

J2 (HDMI Input 2) J2 (HDMI Input 2)
H8, H7, H6, H5

are associated
H8, H7 H6, H5 with HDMI Input 2
TOSLINK (S/PDIF) TOSLINK (S/PDIF)
H4, H3, H2, H1

H4, H3, H2, H1
are associated with HDMI Input 1
H10, H6, H2 J3 (HDMI Out) H9, H5, H1 J3 (HDMI Out)

are for SDA are for SCL
control control
TOSLINK (S/PDIF) TOSLINK (S/PDIF)
H12, H8, H4 are for CEC control H11, H7, H3 are for HPD control
Figure 5 is a conceptual connection of the header connections. This applies to all four signals. An example of the
connection is shown in Figure 6. In this example, the shunts are installed on pin1/pin 2 of H9 ~ H12 and pin2/pin3
of H1 ~ H4. This will bypass the four signals between J1 and J3.
5
Figure 5. Conceptual Connection for Headers H1 to H12

H12, H11,
H10, H9
J3 (HDMI Out)
LatticeECP3
FPGA
H8, H7,
H6, H5
TMDS J2 (HDMI Input 2)
Equalizer
H4, H3,
H2, H1
J1 (HDMI Input 1)
Figure 6. Example for Bypassing CEC, HPD, SDA, SCL Between J1 and J3
H12, H11,
H10, H9
J3 (HDMI Out)
LatticeECP3
FPGA
H8, H7,
H6, H5
TMDS J2 (HDMI Input 2)
Equalizer
H4, H3,
H2, H1
J1 (HDMI Input 1)
Technical Support Assistance

Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
August 2010 01.0 Initial release.
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
6
5 4 3 2 1
COVER PAGE Figure 7. Cover Page
D D
HDMI MEZZANINE CARD - LATTICE SEMICONDUCTOR CORPORATION

Lattice Semiconductor
Page Description
Appendix A. Schematic
1 Cover Page
2 Revision History
3 Block Diagram
4 Power Scheme
C C
5 HDMI Input Ports
6 I2C, HPD, CEC Selection
7 HDMI Equalizer
8 TMDS Switch
9 HDMI Output Port
7
10 B To B Connectors and Audio Input
11 Board Accessories
B B
A Internal Version 0.02 A
GDA Technologies Ltd,

L & T Infotech Park, Tel: 91-44-2253 7900
Mount Poonamallee Road, Fax: 91-44-2252 3514
Manapakkam, Ch 89 www.gdatech.com
Title
COVER PAGE
Size Document Number Rev
B GDA09CB004B B
Date: Tuesday, March 02, 2010 Sheet 1 of 11

5 4 3 2 1
User’s Guide
5 4 3 2 1
REVISION HISTORY
D D
Figure 8. Revision History
Revision Verison Release Date Description
A 0.01 18-May-2009 Initial release
0.02 20-May-2009 Jumper options for DDC, HPD and CEC lines modified
C C
0.03 27-May-2009 HDMI signals swapping done for layout feasibility
0.04 29-May-2009 Single Ended signals swapping done at control signal connector
for layout feasibility
0.05 02-Jun-2009 Pin Mapping table added for Mezzanine and control signal connectors
0.06 03-Jun-2009 Pin mapping table modified. Pullups added for output signals
8
from ECP3 board. SPDIF data assigned to MZ_CTRL13
0.07 09-Jun-2009 Customer Feedbacks implemented

0.09 11-Jun-2009 Version change after customer modification of schematics for HDMI Equivalizer
B
0.10 15-Jun-2009 Customer Feedbacks implemented B

0.12 24-Jun-2009 Customer Feedbacks implemented on decoupling caps for U3, U8
B 0.01 11-Feb-2010 Clock cleaner is removed and eight 50ohms pullup resistors are added
for the HDMI output port as per customer requirement
0.02 2-Mar-2010 'GDA confidential' is removed from all pages as per customer feedback

Title
REVISION HISTORY
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
BLOCK DIAGRAM
D D
Figure 9. Block Diagram
C C
9
B B

Title
BLOCK DIAGRAM
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
POWER SCHEME
D D
Figure 10. Power Scheme
C C
10
B B

Title
POWER SCHEME
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
HDMI INPUT PORTS

VDD_5V0 VDD_3V3
VDD_5V0_HDMI1
U1
TP1 1 38 1
Test_Pad 1 HDMI1_ESDBYPASS NC 5V_SUPPLY
37 2
2
D1 ESD_BYP LV_SUPPLY
D 36 3 D
B340LA-13-F GND2 GND1
HDMI1_DATA2+ 35 4 HDMI1_DATA2+ HDMI1_DATA2+ [7]
TMDS_D2+_2 TMDS_D2+_1
HDMI Input -1 34 5
HDMI1_DATA2- TMDS_GND8 TMDS_GND1 HDMI1_DATA2-
33 6 HDMI1_DATA2- [7]
J1 TMDS_D2-_2 TMDS_D2-_1
1 HDMI1_DATA2+ HDMI1_DATA1+ 32 7 HDMI1_DATA1+ HDMI1_DATA1+ [7]
1 TMDS_D1+_2 TMDS_D1+_1
2 31 8
2 HDMI1_DATA2- HDMI1_DATA1- TMDS_GND7 TMDS_GND2 HDMI1_DATA1-
3 30 9 HDMI1_DATA1- [7]
3 TMDS_D1-_2 TMDS_D1-_1
Figure 11. HDMI Input Ports
4 HDMI1_DATA1+
4 HDMI1_DATA0+ HDMI1_DATA0+
5 29 10 HDMI1_DATA0+ [7]
5 HDMI1_DATA1- TMDS_D0+_2 TMDS_D0+_1
6 28 11
27K CEC1_PULL 1
6 HDMI1_DATA0+ HDMI1_DATA0- TMDS_GND6 TMDS_GND3 HDMI1_DATA0-
2K
2K
1K
7 27 12 HDMI1_DATA0- [7]
20 8
20 8 HDMI1_DATA0- HDMI1_CLK+ HDMI1_CLK+
21 9 26 13 HDMI1_CLK+ [7]
21 9 HDMI1_CLK+ TMDS_CK2+ TMDS_CK1+
22 10 25 14
22 10 HDMI1_CLK- TMDS_GND5 TMDS_GND4 HDMI1_CLK-
23 11 24 15
R1
R2
R3
R4
23 11 TMDS_CK2- TMDS_CK1- HDMI1_CLK- [7]
12 HDMI1_CLK-
12 CEC_HDMI1 CEC_HDMI1 CEC_HDMI_IN1
13 23 16 CEC_HDMI_IN1 [6]
13 SCL_HDMI1 CE_REMOTE_OUT CE_REMOTE_IN SCL_HDMI_IN1
14 22 17 SCL_HDMI_IN1 [6]
14 J1SCL R67 51E SCL_HDMI1 SDA_HDMI1 DDC_CLK_OUT DDC_CLK_IN SDA_HDMI_IN1
15 21 18 SDA_HDMI_IN1 [6]
15 J1SDA R68 51E SDA_HDMI1 HPD_HDMI1 DDC_DAT_OUT DDC_DAT_IN HPD_HDMI_IN1
16 20 19 HPD_HDMI_IN1 [6]
16 HOTPLUG_DET_OUT HOTPLUG_DET_IN
17
17 C1 C27
18
18 HPD_HDMI1 0.1uF 0.1uF
19
19 10V CM2021
10V
500254_1927
PIN NO NAME
C C
1 TMDS DATA2+
2 TMDS DATA2 SHIELD
3 TMDS DATA2-
4 TMDS DATA1+
5 TMDS DATA1 SHIELD
6 TMDS DATA1- VDD_5V0_HDMI2
7 TMDS DATA0+ VDD_5V0 VDD_3V3
11
8 TMDS DATA0 SHIELD
9 TMDS DATA0-
TP2 1 U2
2
10 TMDS CLOCK+ Test_Pad 1 D2
11 TMDS CLOCK SHIELD B340LA-13-F 38 1
HDMI2_ESDBYPASS NC 5V_SUPPLY
37 2
ESD_BYP LV_SUPPLY
12 TMDS CLOCK- 36 3
GND2 GND1
HDMI Input -2 HDMI2_DATA2+ HDMI2_DATA2+
13 CEC 35 4 HDMI2_DATA2+ [8]
J2 TMDS_D2+_2 TMDS_D2+_1
34 5
HDMI2_DATA2+ HDMI2_DATA2- TMDS_GND8 TMDS_GND1 HDMI2_DATA2-
14 NC 1 33 6 HDMI2_DATA2- [8]
B 2 B
2 HDMI2_DATA2- HDMI2_DATA1+ HDMI2_DATA1+
15 SCL 3 32 7 HDMI2_DATA1+ [8]
CEC2_PULL 1
4 HDMI2_DATA1+ 31 8
4 HDMI2_DATA1- TMDS_GND7 TMDS_GND2 HDMI2_DATA1-
16 SDA 5 30 9 HDMI2_DATA1- [8]
5 HDMI2_DATA1- TMDS_D1-_2 TMDS_D1-_1
6
27K
6 HDMI2_DATA0+ HDMI2_DATA0+ HDMI2_DATA0+
2K
2K
1K
17 DDC/CEC GROUND 7 29 10 HDMI2_DATA0+ [8]
20 8 28 11
20 8 HDMI2_DATA0- HDMI2_DATA0- TMDS_GND6 TMDS_GND3 HDMI2_DATA0-
18 +5V POWER 21 9 27 12 HDMI2_DATA0- [8]
21 9 HDMI2_CLK+ TMDS_D0-_2 TMDS_D0-_1
22 10
22 10 HDMI2_CLK+ HDMI2_CLK+
23 11 26 13
R5
R6
R7
R8
19 HOT PLUG DETECT 23 11 TMDS_CK2+ TMDS_CK1+ HDMI2_CLK+ [8]
12 HDMI2_CLK- 25 14
12 CEC_HDMI2 HDMI2_CLK- TMDS_GND5 TMDS_GND4 HDMI2_CLK-
13 24 15 HDMI2_CLK- [8]
13 TMDS_CK2- TMDS_CK1-
14
14 J2SCL R69 51E SCL_HDMI2 CEC_HDMI2 CEC_HDMI_IN2
15 23 16 CEC_HDMI_IN2 [6]
15 J2SDA R70 51E SDA_HDMI2 SCL_HDMI2 CE_REMOTE_OUT CE_REMOTE_IN SCL_HDMI_IN2
16 22 17 SCL_HDMI_IN2 [6]
16 SDA_HDMI2 DDC_CLK_OUT DDC_CLK_IN SDA_HDMI_IN2
17 21 18 SDA_HDMI_IN2 [6]
17 HPD_HDMI2 DDC_DAT_OUT DDC_DAT_IN HPD_HDMI_IN2
18 20 19 HPD_HDMI_IN2 [6]
18 HPD_HDMI2 HOTPLUG_DET_OUT HOTPLUG_DET_IN
19
19 C2 C28
500254_1927 0.1uF 0.1uF
10V 10V CM2021
Note
----------
The 5V Supply of the HDMI Input connectors are not used
in the Mezz card since there is no EDID EEPROM available in the card GDA Technologies Ltd,
Title
HDMI INPUT PORTS
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
HPD, CEC, I2C SELECTION

SCL_HDMI1_EQ_EXT
SCL_HDMI1_EQ_EXT [7]
SCL_HDMI_IN1
SCL_HDMI_IN1 [5]
SCL_HDMI_IN2
SCL_HDMI_IN2 [5]
SDA_HDMI1_EQ_EXT
SDA_HDMI_IN1 SDA_HDMI1_EQ_EXT [7]
SDA_HDMI_IN2 SDA_HDMI_IN1 [5]
SDA_HDMI_IN2 [5]
D HPD_HDMI1_EQ_EXT D
HPD_HDMI_IN1 HPD_HDMI1_EQ_EXT [7]
HPD_HDMI_IN2 HPD_HDMI_IN1 [5]
HPD_HDMI_IN2 [5]
CEC_HDMI1_EQ_EXT
CEC_HDMI_IN1 CEC_HDMI1_EQ_EXT [7]
CEC_HDMI_IN2 CEC_HDMI_IN1 [5]
CEC_HDMI_IN2 [5]
SCL_HDMIOUT_CM2020INT
SCL_HDMIOUT_LEVSHIFT SCL_HDMIOUT_CM2020INT [10]
SCL_HDMIOUT_LEVSHIFT [10]
SDA_HDMIOUT_CM2020INT
SDA_HDMIOUT_CM2020INT [10]
SDA_HDMIOUT_LEVSHIFT
SDA_HDMIOUT_LEVSHIFT [10]
HPD_HDMIOUT_CM2020INT
HPD_HDMIOUT_CM2020INT [10]
HPD_HDMIOUT_LEVSHIFT
HPD_HDMIOUT_LEVSHIFT [10]
CEC_HDMIOUT_CM2020INT
Figure 12. I2C, HPD, CEC Selection
CEC_HDMIOUT_MEZZCONN CEC_HDMIOUT_CM2020INT [10]

CEC_HDMIOUT_MEZZCONN [11]
1x3 1x3 1x3 1x3
CEC_HDMIOUT_MEZZCONN 3 HPD_HDMIOUT_LEVSHIFT 3 SDA_HDMIOUT_LEVSHIFT 3 SCL_HDMIOUT_LEVSHIFT 3

CEC_HDMIOUT_CM2020INT 3 HPD_HDMIOUT_CM2020INT 3 SDA_HDMIOUT_CM2020INT 3 SCL_HDMIOUT_CM2020INT 3
2 2 2 2
JMP_CEC 2 JMP_HPD 2 JMP_SDA 2 JMP_SCL 2
1 1 1 1
1 1 1 1
C H12 H11 H10 H9 C
1x3 1x3 1x3 1x3

3 3 3 3
CEC_HDMI_IN2 3 HPD_HDMI_IN2 3 SDA_HDMI_IN2 3 SCL_HDMI_IN2 3
2 2 2 2
CEC_HDMI1_EQ_EXT 2 HPD_HDMI1_EQ_EXT 2 SDA_HDMI1_EQ_EXT 2 SCL_HDMI1_EQ_EXT 2
1 1 1 1
1 1 1 1
H8 H7 H6 H5
12
1x3 1x3 1x3 1x3
3 3 3 3
CEC_HDMI_IN1 3 HPD_HDMI_IN1 3 SDA_HDMI_IN1 3 SCL_HDMI_IN1 3
2 2 2 2
2 2 2 2
1 1 1 1
1 1 1 1
H4 H3 H2 H1
B B

Title
I2C, HPD, CEC SELECTION
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
HDMI EQUALIZER
VDD_3V3
D D
11
2
15
21
33
40
46
26
U3
HDMI1_CLK+ HDMI_EQ_CLK+
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
[5] HDMI1_CLK+ 39 22 HDMI_EQ_CLK+ [8]
HDMI1_CLK- IN_D1+ OUT_D1+ HDMI_EQ_CLK-
[5] HDMI1_CLK- 38 23
VDD_INT
IN_D1- OUT_D1- HDMI_EQ_CLK- [8]
VDD_EXT
Figure 13. HDMI Equalizer
[5] HDMI1_DATA0+ HDMI1_DATA0+ 42 19 HDMI_EQ_DATA0+

HDMI1_DATA0- IN_D2+ OUT_D2+ HDMI_EQ_DATA0- HDMI_EQ_DATA0+ [8]
[5] HDMI1_DATA0- 41 20 HDMI_EQ_DATA0- [8]

IN_D2- OUT_D2-
IN_D3+ OUT_D3+ HDMI_EQ_DATA1+ [8]
[5] HDMI1_DATA1- HDMI1_DATA1- 44 17 HDMI_EQ_DATA1-
IN_D3- OUT_D3- HDMI_EQ_DATA1- [8]

HDMI1_DATA2- IN_D4+ OUT_D4+ HDMI_EQ_DATA2- HDMI_EQ_DATA2+ [8]
[5] HDMI1_DATA2- 47 14 HDMI_EQ_DATA2- [8]
IN_D4- OUT_D4-
[6] SCL_HDMI1_EQ_EXT
SCL_HDMI1_EQ_EXT 9
SCL_EXT
STDVE001A SCL_INT
28 SCL_HDMI1_EQ_INT
SCL_HDMI1_EQ_INT [11]
SDA_HDMI1_EQ_EXT 8 29 SDA_HDMI1_EQ_INT
[6] SDA_HDMI1_EQ_EXT SDA_EXT SDA_INT SDA_HDMI1_EQ_INT [11]
[11] DDC_EN_EQUALIZER DDC_EN_EQUALIZER 32

DDC_EN
HPD_HDMI1_EQ_EXT 7 30 HPD_HDMI1_EQ_INT HPD_HDMI1_EQ_INT [11]
[6] HPD_HDMI1_EQ_EXT HPD_EXT HPD_INT
CEC_HDMI1_EQ_EXT 3 4 CEC_HDMI1_EQ_INT CEC_HDMI1_EQ_INT [11]
[6] CEC_HDMI1_EQ_EXT CEC_IO CEC_IO_INT
[11] OE#_HDMI_EQUALIZER OE#_HDMI_EQUALIZER 25 10 PRE_EQUALIZER [11]
OE# PRE
[11] HDMI_EQ_BOOST1 HDMI_EQ_BOOST1 34 6 REXT_EQ
HDMI_EQ_BOOST2 EQ_BOOST1 REXT
[11] HDMI_EQ_BOOST2 35
EQ_BOOST2
C C
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
E_PAD
STDVE001A
1
5
12
18
24
27
31
36
37
43
49
VDD_3V3 VDD_3V3 R9
4.70K
B3 3000mA 1%
47K
47K
47K
47K
47K
47K
47K
47K
4.7K
4.7K
4.7K
4.7K
4.7K
AGND
nm
nm
13
R65
R64
R13
R12
R11
R10
R63
R66
B1 3000mA
R62
R14
R15
R56
R57
HDMI_EQ_BOOST1
HDMI_EQ_BOOST2 CEC_HDMI1_EQ_INT
HPD_HDMI1_EQ_EXT HPD_HDMI1_EQ_INT AGND
SCL_HDMI1_EQ_EXT SCL_HDMI1_EQ_INT
SDA_HDMI1_EQ_EXT SDA_HDMI1_EQ_INT
CEC_HDMI1_EQ_EXT PRE_EQUALIZER
B B
OE#_HDMI_EQUALIZER
DDC_EN_EQUALIZER
VDD_3V3 VDD_3V3
CD59 CD60 CD61 CD62 CD63 CD64 CD65 CD66 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16
0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF
10V 50V 10V 50V 10V 50V 10V 50V 10V 50V 10V 50V 10V 50V 10V 50V
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF

Title
HDMI EQUALIZER
B GDA09CB004B B
De-Caps for HDMI Equalizer
5 4 3 2 1
User’s Guide
5 4 3 2 1
TMDS SWITCH
D VDD_3V3 VDD_5V0 D
Figure 14. TMDS Switch
1
7
14
31
40
22
U4
HDMI2_DATA2+ 48
[5] HDMI2_DATA2+ D0+A
VDD5V
HDMI2_DATA2- 47
[5] HDMI2_DATA2- D0-A
VDD3V3_1
VDD3V3_2
VDD3V3_3
VDD3V3_4
VDD3V3_5
HDMI2_DATA1+ 46
NOTE: Place capacitors nearer to J4 as close as possible
HDMI2_DATA1- 45
[5] HDMI2_DATA1- D1-A
HDMI2_DATA0+ 44
HDMI2_DATA0- 43 3 DATA2+ C3 0.1uF HDMIIN_DATA2+ HDMIIN_DATA2+ [11]
[5] HDMI2_DATA0- D2-A D0+
4 DATA2- C4 0.1uF HDMIIN_DATA2- HDMIIN_DATA2- [11]
HDMI2_CLK+ D0-
[5] HDMI2_CLK+ 42
HDMI2_CLK- CLK+A DATA1+ C5 0.1uF HDMIIN_DATA1+
[5] HDMI2_CLK- 41 5 HDMIIN_DATA1+ [11]
CLK-A D1+ DATA1- C6 0.1uF HDMIIN_DATA1-
6 HDMIIN_DATA1- [11]
D1-
HDMI_EQ_DATA2+ 39 9 DATA0+ C7 0.1uF HDMIIN_DATA0+ HDMIIN_DATA0+ [11]
[7] HDMI_EQ_DATA2+ D0+B D2+
HDMI_EQ_DATA2- 38 10 DATA0- C8 0.1uF HDMIIN_DATA0- HDMIIN_DATA0- [11] VDD_3V3
[7] HDMI_EQ_DATA2- D0-B PI3HDMI1210-A D2-
HDMI_EQ_DATA1+ 37 11 HDMIIN_CLK+ C15 0.1uF HDMIIN_CLEANED_CLK+
[7] HDMI_EQ_DATA1+ D1+B HDMI CLK+ HDMIIN_CLEANED_CLK+ [11]
HDMI_EQ_DATA1- 36 12 HDMIIN_CLK- C14 0.1uF HDMIIN_CLEANED_CLK- DATA2+ R72 51
[7] HDMI_EQ_DATA1- D1-B CLK- HDMIIN_CLEANED_CLK- [11]
C HDMI_EQ_DATA0+ 35
SWITCH DATA2- R73 51 C
[7] HDMI_EQ_DATA0+ D2+B
VDD_3V3 HDMI_EQ_DATA0- 34
[7] HDMI_EQ_DATA0- D2-B DATA1+ R74 51
HDMI_EQ_CLK+ 33
H13 [7] HDMI_EQ_CLK+ CLK+B
HDMI_EQ_CLK- 32 DATA1- R75 51
[7] HDMI_EQ_CLK- CLK-B
1
1 TMDSSWITCH_CHAN_SEL DATA0+ R76 51
2 8
2 SEL
3
3 DATA0- R77 51
VDD_3V3 R16 4.7K TMDS_SW_0B1 29
1x3 R17 4.7K TMDS_SW_1B1 0B1 HDMIIN_CLK+ R78 51
27
1B1 TMDS_SW_A0 R18 4.7K
18
R19 4.7K TMDS_SW_0B2 A0 TMDS_SW_A1 R20 4.7K HDMIIN_CLK- R79 51
28 20
R21 4.7K TMDS_SW_1B2 0B2 A1
26
1B2
R22 4.7K TMDS_SW_EN# 23 2 TMDS_SW_CP1
NOTE: Place resistors closer to AC coupling caps
14
R23 4.7K TMDS_SW_IN EN# CP1 TMDS_SW_CP2
21 16
IN CP2 TMDS_SW_CP3
24
CP3
GND1
GND2
GND3
GND4
GND5
GND6
C9 C10 C11
PI3HDMI1210-A 0.1uF 0.1uF 0.1uF
13
15
17
19
25
30
10V 10V 10V
Note
---------
HDMI Input Channel Select Side Band Channel Disabled
SEL Pin = Low Equalized HDMI Channel ----> TMDS Switch Output
B B
SEL Pin = High Un Equalized HDMI Channel ----> TMDS Switch Output
VDD_3V3
De-Caps for TMDS Switch
CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26
0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF
10V 50V 10V 50V 10V 50V 10V 50V 10V 50V
VDD_5V0
CD27 CD28
0.1uF 1000pF
10V 50V

Title
TMDS SWITCH
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
HDMI OUTPUT PORT

VDD_3V3
VDD_3V3 VDD_5V0 VDD_5V0_HDMIOUT

D D
2
11
15
21
26
33
40
46
U8
R42
3 4.7K U7 C25 0.1uF
FUNCTION1
4
FUNCTION2
34 1 38
VCC3V3_1
VCC3V3_2
VCC3V3_3
VCC3V3_4
VCC3V3_5
VCC3V3_6
VCC3V3_7
VCC3V3_8
FUNCTION3 ANALOG2 R71 nm 4.7K 5V_SUPPLY 5V_OUT CM2020_ESDBP C18 0.1uF
35 10 2 37
FUNCTION4 ANALOG2 LV_SUPPLY ESD_BYP
3 36
GND1 GND2
Figure 15. HDMI Output Port
TMDSOUT_DATA2+ 4 35 TMDSOUT_DATA2+
HDMIOUT_CLK+ C16 3.3uF ST_HDMIOUT_CLK+ TMDSOUT_DATACLK+ TMDS_D2+_1 TMDS_D2+_2
[11] HDMIOUT_CLK+ 39 22 5 34
HDMIOUT_CLK- C17 3.3uF ST_HDMIOUT_CLK- IN_D1+ OUT_D1+ TMDSOUT_DATACLK- TMDSOUT_DATA2- TMDS_GND1 TMDS_GND8 TMDSOUT_DATA2-
[11] HDMIOUT_CLK- 38 23 6 33
IN_D1- OUT_D1- TMDS_D2-_1 TMDS_D2-_2
HDMIOUT_DATA0+ C19 3.3uF ST_HDMIOUT_DATA0+ 42 19 TMDSOUT_DATA0+ TMDSOUT_DATA1+ 7 32 TMDSOUT_DATA1+
[11] HDMIOUT_DATA0+ IN_D2+ OUT_D2+ TMDS_D1+_1 TMDS_D1+_2
HDMIOUT_DATA0- C20 3.3uF ST_HDMIOUT_DATA0- 41 20 TMDSOUT_DATA0- 8 31
[11] HDMIOUT_DATA0- IN_D2- OUT_D2- TMDS_GND2 TMDS_GND7
TMDSOUT_DATA1- 9 30 TMDSOUT_DATA1-
HDMIOUT_DATA1+ C21 3.3uF ST_HDMIOUT_DATA1+ 45 TMDSOUT_DATA1+ TMDS_D1-_1 TMDS_D1-_2
[11] HDMIOUT_DATA1+ 16
HDMIOUT_DATA1- C22 3.3uF ST_HDMIOUT_DATA1- 44 IN_D3+ OUT_D3+ TMDSOUT_DATA1- TMDSOUT_DATA0+ TMDSOUT_DATA0+
[11] HDMIOUT_DATA1- 17 10 29
IN_D3- STHDLS101T OUT_D3- TMDS_D0+_1 TMDS_D0+_2
11 28
HDMIOUT_DATA2+ C23 3.3uF ST_HDMIOUT_DATA2+ 48 TMDSOUT_DATA2+ TMDSOUT_DATA0- TMDS_GND3 TMDS_GND6 TMDSOUT_DATA0-
[11] HDMIOUT_DATA2+ 13 12 27
HDMIOUT_DATA2- C24 3.3uF ST_HDMIOUT_DATA2- 47 IN_D4+ OUT_D4+ TMDSOUT_DATA2- TMDS_D0-_1 TMDS_D0-_2
[11] HDMIOUT_DATA2- 14
IN_D4- OUT_D4- TMDSOUT_DATACLK+ TMDSOUT_DATACLK+
13 26
OE#_HDMI_LEV_SHIFT 25 TMDS_CK1+ TMDS_CK2+
[11] OE#_HDMI_LEV_SHIFT 14 25
OE# TMDSOUT_DATACLK- TMDS_GND4 TMDS_GND5 TMDSOUT_DATACLK-
15 24
TMDS_CK1- TMDS_CK2-
HPD_HDMIOUT_MEZZCONN 7 30 HPD_HDMIOUT_LEVSHIFT CEC_HDMIOUT_CM2020INT 16 23 CEC_OUT
[11] HPD_HDMIOUT_MEZZCONN HPD_SOURCE HPD_SINK VDD_3V3 SCL_HDMIOUT_CM2020INT CE_REMOTE_IN CE_REMOTE_OUT SCL_OUT
17 22
SDA_HDMIOUT_CM2020INT DDC_CLK_IN DDC_CLK_OUT SDA_OUT
18 21
SCL_HDMIOUT_MEZZCONN SCL_HDMIOUT_LEVSHIFT HPD_HDMIOUT_CM2020INT DDC_DAT_IN DDC_DAT_OUT HPD_OUT
C [11] SCL_HDMIOUT_MEZZCONN 9 28 19 20 C
SCL_SOURCE SCL_SINK HOTPLUG_DET_IN HOTPLUG_DET_OUT
SDA_HDMIOUT_MEZZCONN SDA_HDMIOUT_LEVSHIFT R58
[11] SDA_HDMIOUT_MEZZCONN 8 29
SDA_SOURCE SDA_SINK nm 4.70K C26 R43
1% CM2020 0.1uF 15K
HDMIOUT_DDC_EN 32 6 REXT_HDMI_LEVSHIFT
[11] HDMIOUT_DDC_EN DDC_EN REXT
R44
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
EPAD
4.70K
STHDLS101T 1%
1
5
12
18
24
27
31
36
37
43
49
B4 3000mA
VDD_3V3
15
VDD_3V3
VDD_5V0_HDMIOUT
47K
47K
47K
47K
4.7K
4.7K
4.7K
4.7K
4.7K
HDMI Output
VDD_5V0_HDMIOUT J3
TMDSOUT_DATA2+ 1
1
2
2
R49
R50
R51
R60
R61
R48
R47
R46
R45
HDMIOUT_DDC_EN TMDSOUT_DATA2- 3
TMDSOUT_DATA1+ 3
4
OE#_HDMI_LEV_SHIFT 4
B 5 B
TMDSOUT_DATA1- 5
PIN NO NAME 6
SDA_HDMIOUT_MEZZCONN SCL_HDMIOUT_CM2020INT TMDSOUT_DATA0+ 6
7
27K
7
8 20
8 20
4.7K
4.7K
SCL_HDMIOUT_MEZZCONN SDA_HDMIOUT_CM2020INT 1 TMDS DATA2+ TMDSOUT_DATA0- 9 21

TMDSOUT_DATACLK+ 9 21
10 22
HPD_HDMIOUT_MEZZCONN HPD_HDMIOUT_CM2020INT 10 22
2 TMDS DATA2 SHIELD 11 23
TMDSOUT_DATACLK- 11 23
12
12
R52
R53
R54
VDD_3V3 CEC_HDMIOUT_CM2020INT 3 TMDS DATA2- CEC_OUT 13

13
14
De-Caps for HDMI Level Shifter SCL_OUT 14
4 TMDS DATA1+ 15
SDA_OUT 15
16
16
5 TMDS DATA1 SHIELD 17
17
18
CD51 CD52 CD53 CD54 CD55 CD56 CD57 CD58 HPD_HDMIOUT_LEVSHIFT HPD_OUT 18
HPD_HDMIOUT_LEVSHIFT [6] 6 TMDS DATA1- 19
0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF SCL_HDMIOUT_LEVSHIFT 19
10V 50V 10V 50V 10V 50V 10V 50V SDA_HDMIOUT_LEVSHIFT SCL_HDMIOUT_LEVSHIFT [6] 500254_1927
SDA_HDMIOUT_LEVSHIFT [6] 7 TMDS DATA0+
CEC_HDMIOUT_CM2020INT
8 TMDS DATA0 SHIELD
SCL_HDMIOUT_CM2020INT CEC_HDMIOUT_CM2020INT [6]
SDA_HDMIOUT_CM2020INT
SCL_HDMIOUT_CM2020INT [6] 9 TMDS DATA0-
HPD_HDMIOUT_CM2020INT SDA_HDMIOUT_CM2020INT [6]
VDD_3V3
De-Caps for HDMI Level Shifter VDD_3V3 HPD_HDMIOUT_CM2020INT [6] 10 TMDS CLOCK+
11 TMDS CLOCK SHIELD
12 TMDS CLOCK-
CD42 CD43 CD44 CD45 CD46 CD47 CD48 CD49 CD67 CD68 CD69 CD70 CD71 CD72 CD73 CD74
13 CEC
0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 14 NC
10V 50V 10V 50V 10V 50V 10V 50V GDA Technologies Ltd,
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 15 SCL Tel: 91-44-2253 7900
L & T Infotech Park,
16 SDA Mount Poonamallee Road, Fax: 91-44-2252 3514
17 DDC/CEC GROUND Title
De-Caps for HDMI Level Shifter HDMI OUTPUT PORT
18 +5V POWER
19 HOT PLUG DETECT Size Document Number Rev
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
B TO B CONNECTORS AND AUDIO IN
H16
1 2 SCL_HDMIOUT_MEZZCONN [10]
1 2
[10] SDA_HDMIOUT_MEZZCONN 3 4 OE#_HDMI_LEV_SHIFT [10]
3 4
[10] HDMIOUT_DDC_EN 5 6 PRE_EQUALIZER [7]
5 6
[7] OE#_HDMI_EQUALIZER 7 8 SCL_HDMI1_EQ_INT [7]
7 8
D [7] SDA_HDMI1_EQ_INT 9 10 HDMI_EQ_BOOST2 [7] D
9 10
[7] HDMI_EQ_BOOST1 11 12 DDC_EN_EQUALIZER [7]
11 12 S/PDIF_DATA
13 14
13 14 VDD_3V3_TOSLINK
15 16
15 16 VDD_3V3
17 18
17 18
19 20
19 20
2x10
L1 47uH
Control Signal Connector

4.7K
CD50
0.1uF
10V
3
M1
R59
VCC
4 1 ST_S/PDIF_DATA R55 0E S/PDIF_DATA
NC1 OUT
5
NC2
GND
TORX147PL(F,T)
2
Figure 16. B to B Connectors and Audio In
C C
S/P DIF CONNECTOR
16
VDD_5V0 VDD_3V3
B CB6 CB7 B
47uF + 47uF +
J4 20V - 20V -
[8] HDMIIN_DATA0+ 1 13 HDMIOUT_DATA0+ [10]
1 13
[8] HDMIIN_DATA0- 2 14 HDMIOUT_DATA0- [10]
2 14
3 15
4 16
5 17 H17
6 18
[9] HDMIIN_CLEANED_CLK+ 7 19 HDMIOUT_CLK+ [10] 1 2
7 19 1 2
[9] HDMIIN_CLEANED_CLK- 8 20 HDMIOUT_CLK- [10] 3 4
8 20 3 4
9 21 5 6
9 21 5 6
10 22 7 8
10 22 7 8
11 23 9 10
11 23 9 10
12 24
12 24 2x5
25
26
27
0750030005 CEC_HDMI1_EQ_INT [7]
[10] HPD_HDMIOUT_MEZZCONN
25
26
27
[7] HPD_HDMI1_EQ_INT CEC_HDMIOUT_MEZZCONN [6] Power Connector
H14
1x1
1
Mezzanine Card Connector

1

Ground Post Title
B TO B CONNECTORS AND AUDIO IN
B GDA09CB004B B

5 4 3 2 1
User’s Guide
5 4 3 2 1
BOARD ACCESSORIES
D D
Figure 17. Board Accessories
Z1
165 mil Pad Size
Z3 Z4 Z5 Z6
40mil Pad 40mil Pad 40mil Pad 40mil Pad
1
1
1
1
1
1
1
1
1
1
Mounting Hole
Fiducials
C C
17
Z7 Z8
100mil Drill Size 100mil Drill Size
1
1
1
1
Tooling Holes
B B

Title
BOARD ACCESSORIES
B GDA09CB004B B

5 4 3 2 1
User’s Guide

HDMI Mezzanine Card - Revision B: User's Guide

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HDMI Mezzanine Card – Revision B

Figure 1. HDMI Mezzanine Card

Figure 2. Functional Block Diagram

Data Pairs 3.4 Gbps

Data Pairs Data Pairs

Table 1. MUX Selection Control

J3 (HDMI Out) J3 (HDMI Out)

H12, H11, H10, H9

H12, H11, H10, H9

H8, H7, H6, H5

J1 (HDMI Input 1) J1 (HDMI Input 1)

TOSLINK (S/PDIF) TOSLINK (S/PDIF)

H4, H3, H2, H1

H10, H6, H2 J3 (HDMI Out) H9, H5, H1 J3 (HDMI Out)

J2 (HDMI Input 2) J2 (HDMI Input 2)

J1 (HDMI Input 1) J1 (HDMI Input 1)

TOSLINK (S/PDIF) TOSLINK (S/PDIF)

Figure 5. Conceptual Connection for Headers H1 to H12

Technical Support Assistance

COVER PAGE Figure 7. Cover Page

HDMI MEZZANINE CARD - LATTICE SEMICONDUCTOR CORPORATION

A Internal Version 0.02 A

GDA Technologies Ltd,

Date: Tuesday, March 02, 2010 Sheet 1 of 11

Revision Verison Release Date Description

A 0.01 18-May-2009 Initial release

0.07 09-Jun-2009 Customer Feedbacks implemented

0.11 17-Jun-2009 Customer Feedbacks implemented

A Internal Version 0.02 A

GDA Technologies Ltd,

Date: Tuesday, March 02, 2010 Sheet 2 of 11

A Internal Version 0.02 A

GDA Technologies Ltd,

Date: Tuesday, March 02, 2010 Sheet 3 of 11

A Internal Version 0.02 A

GDA Technologies Ltd,

Date: Tuesday, March 02, 2010 Sheet 4 of 11

HDMI INPUT PORTS

7 TMDS DATA0+ VDD_5V0 VDD_3V3

Date: Tuesday, March 02, 2010 Sheet 5 of 11

HPD, CEC, I2C SELECTION

CEC_HDMIOUT_MEZZCONN CEC_HDMIOUT_CM2020INT [10]

1x3 1x3 1x3 1x3

CEC_HDMIOUT_MEZZCONN 3 HPD_HDMIOUT_LEVSHIFT 3 SDA_HDMIOUT_LEVSHIFT 3 SCL_HDMIOUT_LEVSHIFT 3

C H12 H11 H10 H9 C

1x3 1x3 1x3 1x3

A Internal Version 0.02 A

GDA Technologies Ltd,

Date: Tuesday, March 02, 2010 Sheet 6 of 11

[5] HDMI1_DATA0+ HDMI1_DATA0+ 42 19 HDMI_EQ_DATA0+

[5] HDMI1_DATA0- 41 20 HDMI_EQ_DATA0- [8]

[5] HDMI1_DATA2+ HDMI1_DATA2+ 48 13 HDMI_EQ_DATA2+

[11] DDC_EN_EQUALIZER DDC_EN_EQUALIZER 32

HPD_HDMI1_EQ_EXT HPD_HDMI1_EQ_INT AGND

A Internal Version 0.02 A

GDA Technologies Ltd,

A Internal Version 0.02 A

GDA Technologies Ltd,

Date: Tuesday, March 02, 2010 Sheet 8 of 11

HDMI OUTPUT PORT

VDD_3V3 VDD_5V0 VDD_5V0_HDMIOUT