IMPLEMENTATION OF PHYSICAL LAYER

TRANSMITTER IN P.C.I EXPRESS

 P.C.I EXPRESS
• HIGH PERFORMANCE I/O BUS.
• USED TO INTERCONNECT PERIPHERAL DEVICES.
• IT IMPLEMENTS SERIAL, POINT –TO-POINT INTERCONNECT.
• SERIAL INTERCONNECT RESULTS IN FEW PINS AND REDUCES
DESIGN COST AND DESIGN COMPLEXITY.
• POINT-TO-POINT INTERCONNECT LIMITS ELECTRICAL LOAD
ON THE LINK.
• POINT-TO-POINT CONNECT PERMITS MUCH HIGHER
TRANSMISSION FREQUENCIES.
• P.C.I EXPRESS TRANSMISSION DATA RATE IS 2.5 Gbits/SEC.
 PURPOSE OF PROJECT
• IMPROVE BUS PERFORMANCE.

• REDUCE OVERALL SYSTEM COST.

• TAKE ADVANTAGE OF NEW DEVELOPMENTS IN

COMPUTER DESIGN.
 PHYSICAL LINK LAYER
• CONNECTS DATA LINK LAYER AND EXTERNAL LAYER.
• Establishment and termination of a connection to a
communications medium.
 FIFO(first in first out)

• TWO TYPES OF FIFO’S ARE USED.

• TLP FIFO IS USED WHEN PCI EXPRESS ACTS AS

TRANSMITTER.

• DLLP FIFO IS USED WHEN PCI EXPRESS ACTS AS

RECEIVER.
 MULTIPLEXER
• SELECTS ONE OF MANY INPUT SIGNALS.

• GATES PACKET CHARACTERS FROM TRANSMISSION

BUFFER TO BYTE STRIPPING LOGIC.
 BYTE STRIPPING LOGIC
• USED TO STORE DATA UNTIL IT GETS 2 BYTES OF
DATA.

• IT TRANSFERS THE DATA INTO 2 LANES AT A TIME.

• IF SINGLE LANE IS USED NO NEED OF BYTE

STRIPPING.
 SCRAMBLER
• SCRAMBLER ELIMINATES REPITITIVE PATTERNS OF
THE TRANSMITTED DATA STREAM.
 LANE REGISTER
• MAINLY USED TO XOR THE DATA COMING FROM
BYTE STRIPPING LOGIC AND SCRAMBLER.

• WE HAVE TO LANE REGISTERS LANE 0 AND LANE 1.

• THE XORed OUTPUT IS SENT TO ENCODER.

ENCODER
SERIALIZER
 SMC
• SMC CONTROLS ALL OTHER BLOCKS.

• CONTROLS INPUT ENABLE SIGNALS OF ALL

THE BLOCKS.

• BASED ON ENABLE SIGNALS THE BLOCKS

STARTS FUNCTIONING.