Chapter 6.

3
• Have seen 1-stage operational
transconductance amplifier (OTA)
• Will do 2-stage
– Higher gain implies greater accuracy
– Needs frequency compensation
– Will consider
• Input offset voltage (Systematic)
• Slew rate
 Voltage Gains
Figure 6.16 page 426
vg 6
Stage 1: Av1  Av1  Gm1  rds 2 rds 4 
vi
where Ro1   ro 2 ro 4 

Stage 2: Av 2 
v0 A2  Gm 6  rds 6 rds 7 
vg 6

Av (dc)  Av1 Av 2
 About rds
• We have used: rds 
1
ID
• Recall: VA  dX d 
1
rds  VA  Leff 
ID 
dV
 DS 
L
• rds proportional to ID
 Offset: First Stage
ID5
Output voltage
corresponding to zero offset

v id
Q 1 Q 2
iOUT  0 when vid  0

VD3 VD4 True if:

IOUT1 VD 4  VD 3
Q 3 Q 4

VD 4  Vt  Veff 3 ID3 ID5 2

VD 4  Vt  Veff 4 ID 4 ID 5 2
 Offset: Second Stage
•High gain stage
I D7
VD 6
VG 6 •VD6 centered in its
Q6
From
Output range only if:
Stage 1
VG 6  Vt  Veff 6 ID ID 7

VG6 must be the value

corresponding to ID7=ID6
Minimize Systematic Offset
We have: VG 6  VD 4 and
VG 6  Vt  Veff 6 ID ID 7 VD 4  Vt  Veff 3 ID 3 ID 5 2

Veff 4 ID 4 ID 5 2  Veff 6 ID 6 ID 7 (Eq. 6.64)

I D5 2I D7 I D 7  WL  7
  W
Cox  WL  4  Cox  WL  6 I D5  L  5

So we want:  WL  6  WL  7
2 W (Eq. 6.66)
 WL  4  L 5
 Frequency Response
• Modify A1 A1  g m1Z OUT 1
– note: now has negative sign
1
• ZOUT 1   rds 2 rds 4 
sCeq

• Where Ceq is Miller input capacitance

Ceq  CC  1  A2  Since A2 is negative
 Approximation
g m1
Av ( s )  A2 A1  A2
sCC A2
Valid for    p1
1
where  p1 
(rds 2 rds 4 )CC A2
A1 A2 g m1
GBP   p1 A1 A2  
(rds 2 rds 4 )CC A2 CC
 Unity-gain Frequency

Unity-gain
Gain, frequency is
dB
extrapolated
fta Therefore,
unity-gain
frequency is
GBP
 Assignment
• 6.11 (except Part f)
• 6.15 (no SPICE)
• 6.16
• We will discuss these problems, including
input common-mode voltage range, in
class.