Alternate Precomputation

Architectures
Precomputation architecture based on
Shannon’s decomposition
 Design issues in precomputation logic
technique
• Basic design steps
• Select permutation architecture
• Determine precomputed inputs R1 and gated
inputs R2 given the function f(x).
• With R1 and R2 selected, find a precomputation
logic function g(x). Since g(x) is not unique the
choice greatly affects the power efficiency. The
function g(x) may also fail to exist for poor
choices of R1 and R2
 contd..
• Evaluate the probability of precomputation
condition and the potential power savings.
Make sure that the final circuit is not
overwhelmed by the additional logic circuitry
and power consumption required to compute
g(x).
Precomputation for multiple output boolean
functions
• This technique can be generated by treating
each output signal j independently and derive
the bit precomputation function gj(x).
• Actual precomputation function g(x) is the
product of gj(x) over all j
 Issues
• If the input signal statistics is unknown, the
precomputation method cannot be applied because
it is impossible to evaluate the power savings
resulted from gating some inputs.
• Availability of CAD tools for area and power
estimation.
• The power saved from input gating and additional
power dissipated in precomputation logic have to be
assessed carefully so that the area overhead can be
justified
 Issues
contd..
• The number of precomputed inputs R1 should be much
smaller than the gated inputs R2 for gross power saving.
• Precomputation by definition is creating redundant
logic. The logic circuits that perform precomputation
generally pose difficulties in testing
• Ex: load disable signal is not observable unless we
implement a full scan of the flip flops
• Besides testability, timing may also become a problem
because the precomputation logic might be on a critical
delay path of the circuit, limiting its performance.