Professional Documents
Culture Documents
Erbe Service Manual Icc200 Icc300h-E Icc350
Erbe Service Manual Icc200 Icc300h-E Icc350
ICC 200
ICC 300 H-E
Service manual
ICC 350
09.2004
ICC 200, ICC 300 H-E, ICC 350
SERVICE MANUAL
10128-002, 10128-009, 10128-010, 10128-015, 10128-016
10128-023, 10128-025, 10128-027, 10128-028, 10128-036
10128-051, 10128-054, 10128-055, 10128-056, 10128-058
10128-061, 10128-064, 10128-065, 10128-066, 10128-070
10128-071, 10128-072, 10128-073, 10128-074, 10128-075
10128-076, 10128-077, 10128-078, 10128-080, 10128-081
10128-082, 10128-083, 10128-200, 10128-202, 10128-204
10128-205, 10128-206, 10128-213, 10128-214, 10128-300
10128-301, 10128-303, 10128-304, 10128-305, 10128-306
10128-307,10128-310, 10128-403
09.2004
This service manual was created by
Michael Grosse
Dipl.-Phys. (Physicist)
Tel (+49) 70 71 / 755–254
Fax (+49) 70 71 / 755–5254
E-Mail mgrosse@erbe-med.de
Net http://www.erbe-med.de
All rights to this service manual, particularly the right to reproduction, distribution and translation,
are reserved. No part of this service manual may be reproduced in any form (including photocopying,
microfilm or other means), or processed, reproduced or distributed by means of electronic systems
without prior written permission from ERBE Elektromedizin GmbH.
The information contained in this service manual may be revised or extended without prior notice
and represents no obligation on the part of ERBE Elektromedizin GmbH.
5 / 266
6 / 266
Chapter 1
Test programs
and
adjustments
Test programs
ERBOTOM ICC 350, 300, 200
Version 4.0 / 3.0 / 2.0
13 not assigned
14 not assigned
15 not assigned
18 not assigned
19 not assigned
20 not assigned
21 not assigned
Art. No.: 80116-201
22 not assigned
09 / 2004
, , ,,
, ,
,,, ,, ,
, ,
, , ,, ,
1 2
3 4 5 7 8 9 11 12 14 15 16
Calling up
Press key 3 (Roll) when switching on the power and hold it down.
adjustable using
0 0s
Test program 23
1 0.5 s
2 1s
Auto Cut 90 s
Auto Coag 1 90 s
Auto Coag 2 90 s
Auto Bipolar 90 s
adjustable using
NESSY version no. NE 1 | || *)
Test program 7
adjustable using
FORCED voltage version 1
Test program 12
Brightness of the adjustable using
10
seven-segment display Test program 17
END O C UT ON
Basic programming
ICC 200 without ENDO CUT option
Basic programming
ICC 200 E and ICC 200 E/A
END O C UT ON
General description
Using this test program, any front panel setting can be made. This setting is known as the basic setting.
After termination, the basic setting is stored internally. Only completely saved channels are stored. The
basic setting display flashes. Acknowledge by pressing any key.
Termination
Using “Power off”.
General description
The ICC units are equipped with a system for error detection, error indication and error memory. Every error
receives an error number (ERROR no.). The unit stores the last 10 ERROR numbers. Test program 2 displays
the stored ERROR numbers. The most recent error occurring chronologically is in memory location 1.
Display
Example
After starting the test program with key 3, for example, Error no. 2 appears at memory location 1 with the
following display:
Display
Err. 1 2
General description
Test of all D-flipflop (D-FF) circuit memories. After starting the test with key 3, you will see the following display:
Display
(ICC 350, ICC 300)
Display
(ICC 200)
buS*) (D-FF-Test Nr. 0) tests the external control bus for signal lines d0–d7. The signal lines d0–d7 are
switched on and off one after another. The switching statuses can be displayed on the bar graph (adapter
board 30183-102).
Using the keys 8 (Up) or 9 (Down), you can call up D-FF tests 1-11. You will see the following display:
Display
(ICC 350, ICC 300)
Display
(ICC 200)
The D-FF signal lines d0-d7 are switched on and off one after another. The signals can be measured at the
D-FF outputs. There is an error if
Art. No.: 80116-201
*)
buS is the seven-segment display for the word „BUS“.
1 D-FF IC 2 Motherboard
2 D-FF IC 3 Motherboard
7 D-FF IC 10 Senso-board
General description
Using this program, you can test the optical displays on the front panel. After starting the test program, you
will see the following display:
All optical signals on the front panel are switched on. The 7-segment displays show “8.” for all numbers.
Art. No.: 80116-201
09 / 2004
General description
Using this program, you can test and set all available sounds. After starting the program, you will see the
following display:
Display
ton 0 ... 4
Using the keys 8 (Up) or 9 (Down), you can set a test number from 0 to 4. The following correspondence
applies between the test numbers and the sounds:
Tone generation
0
switched off
1 Basic tone 1 Volume adjustable
General description
Using this program, all relays can be actuated. The NESSY measurement monitor is switched off. After
ending the test program, relay no. 1 is switched on for the power starting current limitation.
Test program no. 6 is also intended for safety testing of the unit. With this test, there may be a brief
failure of the power supply due to the external intervention. If the test program is activated, the test
program is automatically called up again after a brief power failure of up to approx. 15 seconds. However,
if the power failure is longer than 15 seconds, this will not occur.
After starting the test program, you will see the following display:
Display
rEL 0 ... 1
Test no. 0
Switch off all relays
Power starting
Rel. 1, motherboard switched off
current limitation
Test no. 1
Switch on all relays
Power starting
Rel. 1, motherboard switched on
current limitation
depending on
dongle installed
switched on
Rel. 2, motherboard capacitance
or off
grounded
(only ICC 350)
All relays on PCBs additionally required for the ERBOTOM ICC 350 MIC are switched on.
Art. No.: 80116-201
09 / 2004
General description
Using this program, you can set four NESSY versions. After starting the test program, you will see the
following displays when you activate key 3:
Display
NE.1 || or |
At the end of the test, the NESSY version number is stored. Version number 1 is the standard version set
when the unit is delivered. In case of memory failure, version no. 1 is automatically set. When switching on
the power, version no. 2, 3 or 4 is displayed briefly if this is set. The standard version no. 1 is not displayed.
General description
Using this program, you can display the software version, while on the ICC 350 and ICC 300, you can also
see the display of an option identification number.
After starting the program, you will see the following display:
Display
Snr x.xx y
Explanation:
x.xx Software version no. (e.g. 2.0)
y Option code no. (e.g. 8).
Code
no. means
16
32
64
128
Art. No.: 80116-201
256
Example
Code no. 2 means ICC 350 Neurotest TUR
Code no. 9 means ICC 350 Neurotest ZMK + Endocut
1 + 8
General description
This program activates displays in the standby mode or during activation. With key 3, Test program no. 9 is
started.
After starting, you will see the following display:
Display
nr. 0
Within Test program no. 9, 22 subprograms for displaying specific data can be called up, while subprograms
16 to 22 are intended only for use by the manufacturer.
These subprograms can now be set using keys 8 (Up) or 9 (Down). Once the required display program has
been selected, it is reactivated using key 3. The selected display program remains activated until the power
is switched off.
Display
nr. 0 ... 22
The selected display program now displays the required data during regular operation of the unit. To do
this, the appropriate operating modes must be set and the accessories activated.
The display program remains activated until the power is switched off. To return to normal operation, the
unit must be switched off for a short time and switched back on again.
ttt P2 P3 tst
ttt tst
Art. No.: 80116-201
uuu iii P3 UI
uuu USt
uuu iii P3 UI
uuu Unt
iii Ist
iii Int
ppp P
iii Real part of the measurement value from the HF output current
cos cos-j value from the table (ICC 350 only)
ppp HF power output [W] for ICC 350
IC Abbreviation of the test title (Current measurement and cos j measurement)
iii I
uuu U
cos Cos
uuu P2 P3 br
rda P2 P3 br
uuu br
rda br
rtr P2 P3 br
rtr r
NOTE
Display programs nos. 13 and 14 are not assigned. The program nos. 17–22 are only intended for internal
use by the manufacturer.
General description
Using this program, you can change the time limit for the ICC 200, 300 and 350. The setting range varies
from 3 to 960 seconds.
Using the appropriate “Up” or “Down” keys, the time limit restriction for every current quality can be set
individually.
For the ICC 350, various time limit settings can be stored in the individual program memories for each user.
This occurs after selecting the program number with program memory key 2 and then changing the respective
current qualities using the appropriate “Up” or “Down” key.
After termination of Test program 10 using key 3, the settings made are stored.
In case of memory failure, as well as in the delivery condition, the max. time limit for all programs and
current qualities (CUT, COAG 1, COAG 2, BIPOLAR) is set at 90 seconds.
After starting Test program 10 with key 3, you will see the following display:
t1 t2 t3 t4
Using the following keys, you can adjust the max. time limit (see page 1-4):
Using this program, you can measure the internal supply voltages and the temperature of the unit. In addition,
you can display all analog direct measurement channels 1, 2, 3 and 4 as well as analog multiplex measurement
channels.
After starting the test program, you will see the following display:
U 0 XX.X
U– 1 XX.X
U 2 XX.X
Ch 4 … 22 yyy
Using the keys “Up” (8) or “Down” (9), call up the subprograms U, U-, tPt and Ch 4 … 22.
U0 is the low voltage controlled to +15 volts ±10%
U–1 is the low voltage controlled to –15 volts ±10%
U2 is the low voltage controlled to 24 volts ±10%
tPt is the temperature display of the output stage ±15%
Ch4 … 22 are the analog measurement channels according to the following table:
U.15 XX.X
–15 XX.X
U.24 XX.X
tPt ttt
C.aa yyy
Using the “Up” (8) or “Down” (9) keys, call up the subprograms U, U-, tPt und C. 4-22.
U0 is the supply voltage controlled to +15 volts
U–1 is the supply voltage controlled to –15 volts
U2 is the supply voltage controlled to +24 volts
tPt is the temperature display of the output stage
C. 4 … 22 are the analog measurement channels according to the following table.
General description
When this program is called up, the set FORCED version is displayed. Using the “Up” (8) or “Down” (9)
keys, you can set one of three (V2.0) or four (V4.0) FORCED versions.
With FORCED coagulation, the ST pulse generator produces short pulses with a high no-load voltage. The
high no-load voltage has both advantages and disadvantages which are described in this section with the
features.
Using Test program 12, the no-load voltage can be changed relative to the set power limitation.
After starting the test program, you will see the following display:
For. vs nr
Forced version vs nr 1
A power limitation of 1 to 30 watts increases the no-load voltage constantly up to approx. 1,300 Vp.
Above 30 watts power limitation, the no-load voltage is limited to approx. 1,300 Vp.
FORCED version vs nr 2
Art. No.: 80116-201
A power limitation of 1 to 30 watts increases the no-load voltage constantly up to approx. 1,300 Vp. Above
30 watts power limitation, the no-load voltage continues to increase:
09 / 2004
Characteristics of version vs nr 2
The characteristics are between those of the vs nr 1 and those of the vs nr 3.
Characteristics of version vs nr 3
• Image interferences on monitors possible.
• Danger of burns from contact with a terminal possible.
• Heavy spark formation with coagulation via a terminal.
• Heavy spark formation also at a 30 watts power setting.
To direct high-frequency power into the tissue, the tissue must not necessarily be contacted (current flow or
powered transmission [see vs nr 2] possible via arc).
Characteristics of version vs nr 4
• Image interference on monitors possible.
• Danger of burns from contact with a terminal possible.
• Heavy spark formation with coagulation via a terminal.
• Heavy spark formation also at a 30 watts power setting.
To direct high-frequency power into the tissue, the tissue must not necessarily be contacted (current flow or
powered transmission [see vs nr 2] possible via arc).
Important notes
• The vs no set only applies to FORCED AUTO COAG 1, FORCED AUTO COAG 2 and for programs
0 to 11.
• For the MIC program, vs nr 1 is automatically set.
• In case of memory failure, vs nr 1 is automatically set.
When switching on the power supply, vs nr 2, vs nr 3 or vs nr 4 (V4.0) is briefly displayed. The standard vs
nr 1 is not displayed.
Measuring equipment
To service equipment from the ICC series, various meters are necessary. The following list summarizes
recommended measuring equipment for a quick overview.
ATTENTION !
Individual parts and boards are at supply voltage potential. After removing the housing cover, there is risk of
electrical shock due to unintentional contact with the power plug connected.
The HF power meter, the oscilloscope and the frequency counter must be operated as floating.
The unit contains a lithium battery which must only be discarded in battery collection containers in completely
discharged condition (i.e. after use). Otherwise, care must be taken to prevent shorting in accordance with
the battery regulations.
HF power meter —
Frequency counter —
09 / 2004
General information
On the display board, there are slots for jumper which, by plugging in so-called “jumpers”, can activate
special software by which our HF surgical units from the ICC series can be adapted to prescribed special
conditions (such as are necessary in various countries) or by means of which specific tests can be performed
by the testing department and service.
WARNING
These jumpers are already positioned during production and must never be changed randomly. For a software
update, make certain that the jumpers are correctly plugged in. Back-up plugs are in the bag with the spare
fuses.
J3–J6
3 6
Connector
to the CPU
LED display LED display LED display LED display
J7–J10 J7–J10
7 10 7 10
Only at right on
ICC 300
Two blocks are available to receive jumpers: At the top right is a block with the slots J3–J6, at the bottom
left (ICC 300: bottom right) is the block with the slots J7–J10.
Block 1
J5 J5 functions together with J6. (see following explanation) (see following explanation)
J6 J6 functions together with J5. (see following explanation) (see following explanation)
The J5 and J6 slots are read by the CPU as a binary number. In this way four different functioning methods,
independent from one another, are programmable by plugging in these jumpers:
plugged free Contact monitor is blocked and AUTO START display is "off".
During activation, another activation signal from some other source has switched off
free plugged
the unit activation (Spanish regulation).
F leakage current > 150 mA, but < 300 mA:
Triple visual and acoustic alarm is triggered.
plugged plugged
HF leakage current > 300 mA:
Art. No.: 80116-201
Deactivation of ERROR 30
Low-resistance load operation possible for BIPOLAR COAG
< 5 ohms triggers ERROR 30 (as of V 2.00):
ERROR 30 warning appears
to protect accessories and - after 4 s red LED (output
due to delivery status
J8 generator. error)
(not USA, ERROR 30
ERROR 30 can be - Output current max. 1.5 A
deactivated here).
deactivated here when - no ERROR indication
activating AUTO BIPOLAR. (This specification especially
applies to the USA.)
Regardless of the selection, special settings are necessary for specific countries. These can be found in the
following matrix. Explanation:
1 Jumper must be plugged in,
o Jumper must not be plugged in,
x (according to the description for Block 1).
Country J5 J6 J7 J8
European countries
(excepted: o o no function per above table
see below)
USA x x no function 1
WARNING
For a power setting greater than 20 W, there is a danger of destroying the HF generator after approx. 1
minute during short-circuit operation. There is no warning if the ERROR 30 error message is switched off.
Art. No.: 80116-201
09 / 2004
General description
All adjustment work is performed solely with the help of this test program. Here the sequence from
Adjustment 1 to Adjustment 13 must be followed.
Ending the test is only possible at the setting Adjustment 0 (as of 0 in the display).
If Test program 16 is activated, the test program is automatically called up again if there is a brief power
failure lasting up to approx. 15 seconds. If the power failure lasts longer than 15 seconds, the test program
is no longer automatically called up.
This text describes only the function of the program. The unit is adjusted according to the adjustment
instructions. These adjustment instructions are a component of the service documents.
After starting the test program with key 3, you will see the following display:
Ab xx (0 … 13)
Ab xx
Using the “Up” (8) and “Down” (9) keys, call up an adjustment test number. Start the adjustment test with
key 3.
Art. No.: 80116-201
09 / 2004
Procedure
• Unplug power cable from the ERBOTOM ICC.
• Pull off the black lines on the bridge-connected rectifier BR 1 on the motherboard and connect an
adjustable isolating transformer to BR 1 in its place, the output voltage of which is adjusted to 0 V.
With well prebalanced boards, a transformer with a fixed voltage of approx. 155 V AC can also be
used.
ATTENTION !
For units which are set to 120 V, you must absolutely make certain that the Erbotom ICC is operated via an
isolated transformer. In addition, the connection between J15 and J20 on the motherboard must be removed
from J15.
• Connect 200 ohms load resistance (e.g. APM 600) to MP1 = GND and MP2 on the power module
(slot J5).
• Connect the oscilloscope to MP1 = GND and MP2 = probe on QC power stage end stage (slot J4).
• Plug the power cable for the Erbotom ICC back in and activate Test program 16, Adjustment 1.
• Activate using the yellow pedal on the footswitch (AUTO CUT).
• Slowly increase the output voltage on the isolating transformer. With a correct setting, the voltage
characteristic corresponds to the graph illustrated below, whereby the small dip (approx. 20 V) next
to the square-wave edges represent a good criterion of evaluation for this.
• Set the phase angle using TP13 (control board, slot J3). For the final setting, the square-wave voltage
must be increased to approx. ±100 V. (Display in AUTO CUT approx. 205).
• After the setting is complete, disconnect the ERBOTOM ICC from the power, remove the cable from
the isolating transformer to BR1 and connect the two black lines again to the bridge-connected
rectifier.
T
1>
1) Ch 1: 50 Volt 500 ns
ICC 350
ICC 300
ICC 200
09 / 2004
Procedure
• Connect 500 ohms load resistance (APM 600) to MP1 = GND and MP2 = +U on “Power Module”
board (slot J5).
• Plug in the power cable on the ICC.
• Call up Test program 16, Adjustment 2.
• Activate ERBOTOM ICC using the yellow footswitch pedal (AUTO CUT).
• Set TP2 on the control board (slot J3) in such a way that 100 W (tolerance +0% / –7%) can be
measured at the HF power meter and a power supply current of 447 mA (tolerance 444...455 mA) is
displayed in the AUTO COAG 1 display. In the AUTO CUT display, a power supply voltage of 223
V (tolerance 223…227 V) is displayed.
• Disconnect the ICC from the power and remove the connecting cable from MP1 and MP2.
ICC 350
ICC 300
ICC 200
Procedure
• Measure the actuation pulse TS1 on the control board (slot J3) with an oscilloscope at measuring
point MP6 = GND and MP2 = probe tip.
• Switch on the ICC and call up Test program 16, Adjustment 3.
• Using TP14 on the control board (slot J3), set a pulse length of 350 ns.
ATTENTION: Pulse is inverted.
• Disconnect the ICC from the power.
• Remove the probe from MP6 and MP2.
ICC 350
ICC 300
ICC 200
5 V/Div
100 ns/Div
Art. No.: 80116-201
Procedure
• Switch the ICC back on and call up Test program 16, Adjustment 4.
• With probe 100 : 1, the no-load HF output voltage between the active and neutral electrode must be
measured; for 2 monopolar outputs: Output CUT / COAG 2.
• Activate the ICC using the yellow footswitch pedal (AUTO CUT).
• Observing the output voltage form, increase the power supply voltage in the CUT field (AUTO CUT
display corresponds to the set power supply voltage; AUTO COAG 1 display corresponds to the
actual power supply voltage). Using TP15 on the control board (slot J3), a symmetrical sine-wave
characteristic must be set.
• At a maximum power supply voltage (= 250 V), make the final adjustment. At the same time, set a
good symmetrical sine-wave shape and a minimum power supply current (= display in AUTO BIPO-
LAR field), which means a minimal no-load power loss (see Fig.). CAUTION: The best possible
sine-wave characteristic has priority over the absolute current minimum.
ICC 350
ICC 300
ICC 200
300 V/Div
500 ns/Div
Art. No.: 80116-201
Procedure
• Call up Test program 16, Adjustment 5.
• Connect the HF power meter, e.g. APM 600 (set to 500 ohms) via active cable to active and neutral
electrode output sockets on the ICC; for 2 monopolar outputs: CUT / COAG 2 output and NE socket.
• Activate the unit with the yellow pedal of the footswitch (AUTO CUT).
• Using TP3 on the control board (slot J3), the HF output voltage is set in such a way that a power of
100 watts is indicated on the HF power meter and a value of 223 volts HF effective voltage (tolerance
220…223 volts) in the display on the AUTO CUT field.
• Under certain conditions, TP 4 (HF current limitation) must be turned back far enough before this
setting so that no current limitation is effective.
• Using TP4 on the control board (slot J3), the HF current limitation is set in such a way that a value of
447 mA effective HF current (tolerance 439…447 mA) with constant power output appears in the
AUTO COAG 1 field.
• Insofar as the measurement of the phase angle between HF voltage and HF current produces a value
greater than 98 (which is 100 · cos j) at this setting in the AUTO COAG 2 field, a value of 100 watts
HF power output is displayed (tolerance 97...100 watts) in the AUTO BIPOLAR field after correct
adjustment of voltage and current.
• For the voltage characteristic at a 500 ohms load, see Fig.
ICC 350
ICC 300
Ab 5 UI before activation
ICC 200
UI before activation
U HF I HF after activation
100 V/Div
Fig.: HF voltage at
R = 500 ohms
Art. No.: 80116-201
500 ns/Div
09 / 2004
*)To avoid decimal places, the value of the table value of cos j is indicated times 100, such that 100 means cos j = 1.
Procedure
• Call up Test program 16, Adjustment 6.
• With the same setup as for Adjustment 5, the unit is activated. At the same time, 5 watts (tolerance
4.5…5.5 watts) should be output at the HF power meter.
• Using TP 5 on the control board (slot J 3), the amplified HF voltage measurement is set in such a way
that a value of 50 volts HF output voltage is displayed in the AUTO CUT field.
• Using TP 6 on the control board, the amplified HF current measurement is set. The value 100 mA Hf
output current is displayed in the AUTO COAG 1 field when set correctly.
• In the Auto Bipolar field, the emitted active power is displayed.
• In the Auto Coag 2 field, the phase angle cos j is displayed.
ICC 350
ICC 300
Ab 6 UI before activation
ICC 200
UI before activation
U HF I HF after activation
Procedure
• Call up Test program 16, Adjustment 7.
• Using ERBE original cable, connect the APM 600 (set at 500 ohms) to the ICC; with 2 monopolar
connections: Connect active output socket: CUT / COAG 2 (ICC 300 / 350) and NE socket.
• Connect a capacitor with 1 nF (e.g. ERBE component no. EE 51103-026) with short lines across the
active electrode and NE sockets on the HF power meter.
This produces a phase shift between voltage and current of 45° at a frequency of 340 kHz.
• Activate the cut footswitch.
• Using TP 7 on the control board (slot J3), the unit is set in such a way a value of 73 (display is
100 · cos j) is displayed in the AUTO CUT field and a value of 120 (analog / digital converter
measured value) is displayed in the AUTO COAG 1 field.
ICC 350
ICC 300
ICC 200
Procedure (also applies to the units without HIGH CUT or ENDO CUT)
• On the ICC 300 and ICC 200 without ENDOCUT, TP8 should be set to the upper limit (to do this,
turn TP8 clockwise).
• Call up Test program 16, Adjustment 8.
• A DC voltage of 70 volts is fed into the patient circuit between the center control for the active AE
socket (with 2 monopolar outputs: Output CUT / COAG 2) and the neutral electrode NE socket (AE =
+, NE = –). To do this, the ERBE TESTBOX 70 volts is recommended (ERBE Order no. 20100-019).
• Adjust TP8 on the control board (slot J3) is set in such a way that a measurement value of 77 is
indicated for the A/D converter, and a value of 70 volts DC is displayed in the AUTO COAG 1 field.
On the ICC 200 ENDOCUT, this value appears in the AUTO CUT field, while the A/D converter
value is not shown.
ICC 350
yyy FU Standby
Procedure
• Call up Test program 16, Adjustment 9.
• Connect an NE cable to the NE input receptacle on the ICC system.
• Connect the other end of the NE cable between 120 ohms of resistance.
• Set TP9 on the control board (slot J3) in such a way that a measurement value of 200 for the A/D
converter is displayed in the AUTO CUT field and a resistance of 120 ohms is displayed in the AUTO
COAG 1 field.
• Now exchange the terminating resistor for a resistance value of 40 ohms. Now verify the measurement
at this resistance; a resistance of 40 ohms (tolerance 37...43 ohms) must be displayed in the AUTO
COAG 1 field.
ICC 350
ICC 300
xxx R üb r Standby
ICC 200
xxx R üb Standby
ICC 350
• ppp Set SOFT COAG power which can be changed during activation.
• xxx Measurement value of the HF leakage current measurement.
Using the power setting in the AUTO COAG 1 field, set the HF leakage current flowing to ground at
Ieff = 150 mA. This is not assigned for the ICC 200 and 300 since no HF leakage current monitor is
available there.
I
3 m cable HF leakage
Art. No.: 80116-201
09 / 2004
Procedure
• Call up Test program 16, Adjustment 11.
• At the BIPOLAR output of the ICC, the ERBE bipolar Testbox for the bipolar automatic starter (EE
20100-017 ) or appropriate fixed resistors (1.2 kOhm and 2.5 kOhm with a capacity of 15 watts as
well as 18 kOhm, 1 watt) is connected via the EE bipolar original cable.
• With a resistance of 2.5 kOhm (socket 1–2), a value of 25 must be displayed in the AUTO CUT field.
(Display = resistance divided by 100). The setting of the switch-on threshold with PT11 on the PCB
control board (slot J3) proceeds in such a way that, at a load resistance of 2.5 kOhm, the display in
the AUTO COAG 2 field changes from “OFF” to “ON”.
• Now the short-circuiting monitor is set by connecting a 6 ohm resistor (capacity = 0.5 watts) to the
BIPOLAR outlet. Then, the display »rLo« appears on the AUTO COAG 1 display. Using TP12 on the
PCB control board J3, the display is set to a measurement value of 100 in the AUTO CUT display.
• Testing the shutdown response: To do this, exit Test program 16 briefly by selecting Test program 0.
The ICC operates in the normal mode. Switch on AUTO START 1. Set the bipolar power to 1 watt.
The BIPOLAR outlet is connected to sockets 1 and 3 on the ERBE Testbox and thereby charged with
1.2 kOhm. The BIPOLAR generator must automatically be activated after the delay time. Now press
pushbutton 1 on the Testbox. This raises the capacity resistance to 18 kOhm. The BIPOLAR generator
must now shut down.
• This test must be repeated at the power settings 20 watts, 40 watts, 50 watts (or without AAMI
standard up to 120 watts).
ICC 350
ICC 300
ICC 200
• uuu Standby measurement value of the contact monitor at a preset bipolar power of 10 watts
• rda Calculated contact resistance at activation [W/100]
• iii Amplified output current at contact resistance < 1 kW
• rLo Display if resistance measured at activation < 1 kW
Procedure
• Call up Test program 16, Adjustment 12.
• Measure actuation impulse TSI_STE at measuring point MP 3 on ST output stage (slot J6) with the
oscilloscope (measuring point MP1 = GND).
• Using TP16, set this to a pulse length of 200 ns (±50 ns).
IMPORTANT! The pulse time is measured at average amplitude, i.e. at approx. 7.5 volts level.
ATTENTION! The pulse is inverted.
• The repetition frequency at TP17 is set in such a way that the value 0 (tolerance 0...4) is displayed in
the AUTO CUT field.
• Now exit the test program and return the ICC to normal operating condition.
• To check the performance, connect the HF output to the HF power meter, setting 500 ohms.
• Activate the ICC using the blue footswitch pedal at the SPRAY and FORCED normal settings. The
power output in watts should correspond to the display in the AUTO COAG 2 field.
• Check whether the maximum emitted output power with SPRAY and FORCED is within the tolerance
limits (120 W ± 15 %). If necessary, conform the pulse length to the PCB control board using TP16.
TP17 must no longer be changed.
ICC 350
ICC 300
ICC 200
5 V/Div
50 ns/Div
Fig. : Transistor switching pulse ST
Art. No.: 80116-201
output stage
09 / 2004
Procedure
• Call up Test program 16, Adjustment 13.
• Set the jumper to the “capacitance grounded” operating mode (place jumper J3 on display board).
• Perform adjustment using ERBE TESTBOX 2 or another 50 Hz sine-wave current source.
• Between the neutral electrode output and the potential equalization, feed a 50 Hz sine-wave current
of 45 µA (see Figure).
• Using TP1 on the motherboard, set the leakage current monitor in such a way that the display in the
AUTO CUT field changes just from 0 to 1 at 45 µAeff.
Reset jumper to previous condition.
ICC 350
x I nF Standby
Measurement setup
Battery-powered
measurement unit
only!
INF
+
ICC ERBE
Power
Testbox 2 18
AE NE N supply
LI
110 V
PE 115 V
19 230 V
TP1
ATTENTION
On the ZMK version, there is a display only during activation and if the Neurotest circuit is closed. On the
TUR version there is a display as soon as the NT LED lights up on the remote control.
Test setup
At the Neurotest output, connect up a test resistor of 1 kOhm, 0.5 W and 1%. On the TUR version, the
Neurotest output is between the neutral electrode and the CUT/COAG 2 output. The TUR version is activated
with the yellow pedal of the dual-pedal footswitch. On the ZMK version the Neurotest output is between the
neutral electrode and the Neurotest output. The ZMK version is activated with the ZMK fingerswitch.
The setting is performed at intensity 3. For this setting the set feedback frequency must be adjusted to 73. If
the electronic fuse trips, the display of feedback frequency is approx. 40.
Current measurement
SPH 1 52 42 75
SPH 2 91 81 100
3
SPH 73 63 83
(Set value 73)
SPH 4 64 54 74
SPH 5 59 49 69
ATTENTION!
Don't forget to remove the jumper!
High-voltage test
The high-voltage test is conducted according to the specifications in the test record.
Testing the activation signals
The TUR version is activated with the yellow pedal of the double-pedal footswitch. The ZMK version is
activated with the ZMK fingerswitch.
Neurotest output. Measure the square-wave voltage on the 1k test resistor. (1mA corresponds to 1V) The
tolerance range of output currents is +25% to –25%. Larger deviations generate an output error display.
09 / 2004
ATTENTION!
On the ZMK version, there is a display only during activation and if the Neurotest circuit is closed. On the
TUR version there is a display as soon as the NT LED lights up on the remote control.
3
SPH 24 21 28 62 57 67
(Set value 73)
SPH 4 32 29 36 45 43 49
SPH 5 38 37 60 38 37 40
Setting the feedback frequency for intensity adjustment can also be performed without the ICC unit by
supplying +15 V to the remote control and measuring the feedback frequency using the frequency meter.
High-voltage test
The high-voltage test is performed using the specifications in the test record.
The probes of no. 2 are only suitable for coagulation and CUT remains inhibited.
Inr. Nr. p3 nd
ATTENTION!
The original ERBE TEM connecting cable EE 20192-086 has a cable impedance of 1 Ohm per cable, which
produces a series resistance of 2 Ohms for the instrument detection. In the line to and from the unit the
instrument test line must have a series resistance of < 0.5 Ohm. Since on the V4.00 version only the TEM
instrument no. 1 and MIEN probe no. 1 are connected up, it is sufficient to perform the balance only for
these instruments.
With jumper JP4 on the front panel the measurement display is activated.
Measurement display
I measurement I no.
0R 0 0…2
10 R 1 3…20
Art. No.: 80116-201
30 R 2 21…45
09 / 2004
51 R 3 set value 52
62 R 4 70…91
ATTENTION!
Never forget to remove jumper JP4.
NE1 Effect 3
500 Ohm 40 ± 15 %
CUT 40 W
ATTENTION!
The measuring system will be damaged beyond repair if the HF lines are connected up to the APM incorrectly.
The output error display is activated at 40 W and 500 Ohm. Activation of the BIPOLAR CUT function
is also possible without the neutral electrode.
• Compressed air control
At instrument 1 the compressed air valve is opened during CUT activation. The compressed air valve
controls the needle of the TEM instrument. After activation the needle reset time elapses. After needle
reset time has elapsed the compressed air valve closes and the needle is reset. Needle reset time is
indicated in test program 23. Check the compressed air valve to make sure that it operates properly
and to ensure there are no leaks.
• Check monopolar coagulation
Activation of the SOFT function and the FORCED function is performed using the blue footswitch.
ATTENTION!
The measuring system will be damaged beyond repair if the HF lines are connected up to the APM incorrectly.
Effect 3
NE1 CUT 500 Ohm 15 ± 3 (W)
15 Watt
The output error display is activated at 40 W and 500 Ohms. Activation of the bipolar CUT function is also
possible without the neutral electrode.
• Test bipolar SOFT coagulation
The SOFT function is activated with the blue footswitch.
500 Ohm
NE1 CUT SOFT 15 Watt 7 ± 2 (W)
No-load voltage 84 ± 5 Vp
ATTENTION!
As soon as the voltage limitation is activated, current flows through the protective diodes and the diodes heat
up. The duration of the test from the moment of voltage limitation must not exceed 5 seconds or else the
protective diodes break down and the circuit will have to be repaired.
General description
Using this program, you can adapt the brightness of the 7-segment displays in 10 stages to the lighting
conditions of the room.
After starting the test program, you will see the following display:
Int xx
General description
Using this program, you can change the specifications for the delay time when activating AUTO START.
The delay time is the time which passes after the forceps contacted the tissue and the HF generator is
actuated.
So that the operating surgeon can know whether the forceps have contacted the tissue, the AUTO BIPO-
LAR activation display (blue triangle in the AUTO-BIPOLAR field) switches on at contact. Then the delay
time starts. After the delay time has passed, the HF generator and the activation tone are switched on.
In case of error in the memory medium, the following basic settings have been preset:
ICC 350 and ICC 300: AUTO START 0: 0 seconds,
AUTO START 1: 0.5 seconds,
AUTO START 2: 1 second;
ICC 200: AUTO START: 0.5 seconds.
After starting Test program 23, you will see the following display:
SEt Up tt.t
Time setting
Possible from 0.1 to 10 seconds in the following time steps:
You can set and store the delay time for every user-specific program 0 to 9 and for every AUTO-START
time (0, 1 and 2).
Since the AUTO-START time 0 can be no longer than AUTO-START time 1, it is best to proceed from the
longest time for AUTO START 2 and then set the times for AUTO START 1 and AUTO START 0.
NOTE
You will find the assignment of keys with the numbers given below on pages 1-4 (Calling up of the test
program mode) of this Service Manual.
For every AUTO START time (0, 1 and 2), you can set and store a delay time. Since the AUTO-START time
0 cannot be any longer than the AUTO-START time 1, it is best to proceed from the longest time for AUTO
START 2 and then set the times for AUTO START 1 and AUTO START 0.
1. Using key 14 Set AUTO START 2
Art. No.: 80116-201
SEt Up tt.t
For the AUTO START function, you can set and store a delay time.
1. Using the “Up” or “Down” key Set the required time
2. Using key 3 The set values are stored and the test program is
exited.
ATTENTION!
Only use original fuses of the same specification.
If these efforts bring no results, there is probably an error within the unit. You should then contact the
Art. No.: 80116-201
technical service.
For a malfunction with a properly functioning display but with no indication of an ERROR number in the
09 / 2004
display, the error may be located in defective accessories. It is possible, for example, that there may be a
defect in the fingerswitch or footswitch, or a disruption in the associated connecting cable. The cause of the
error may be determined by exchanging the accessories used.
To determine other causes of errors, an ERROR number in the unit display indicates the course of further
action according to the following table.
Error
no. Designation and remedies
Error
no. Designation and remedies
14 (not assigned)
15 (not assigned)
16 (not assigned
Activate unit only after switching on power. Check fingerswitch and footswitch as to whether a
22
key or pedal is stuck or the switch is defective.
Otherwise equipment defect: Technical Service.
Error
no. Designation and remedies
Error
no. Designation and remedies
Self-check.
46 Error within the permissible limits during comparison of the power supply unit voltage with the
09 / 2004
Error
no. Designation and remedies
49 not assigned
A key on the front panel is depressed.
50
Operating field key is depressed or defective during the power start-up phase. If it cannot be
to 70
corrected, then equipment defect: Technical Service.
Interface error for ICC 350 DOKU: Start or stop bit error or number of bits incorrect.
71
Equipment defect: Technical Service.
Interface error for ICC 350 DOKU: Signal in receiving register has not been read out.
72
Equipment defect: Technical Service.
Interface error for ICC 350 DOKU: Parity sign placed incorrectly.
73
Equipment defect: Technical Service.
Interface error for ICC 350 DOKU: No connection to PC available.
74
Equipment defect: Technical Service.
Interface error for ICC 350 DOKU: Sign stays in transmitter buffer. SIO module not transmitting.
75
Equipment defect: Technical Service.
Interface error for ICC 350 DOKU: Interface storage takes too long; hard disk is too slow.
76
Equipment defect: Technical Service.
77
not assigned
to 79
ICC 350 NEUROTEST: No valid frequency for the 5-stage intensity setting.
80 Replace remote control.
Otherwise equipment defect: Technical Service.
ICC 350 NEUROTEST: The intensity setting was set to 0 during activation.
81 Do not set anything during activation.
Otherwise equipment defect: Technical Service.
ICC 350 NEUROTEST: NESSY measurement: NE impedance > 120 ohms.
82 Test the neutral electrode and supply line or position of the NE on the patient.
Otherwise equipment defect: Technical Service.
Error
no. Designation and remedies
ICC 350 NEUROTEST: Output current too high, but still within the permissible limits.
83
Equipment defect: Technical Service.
ICC 350 NEUROTEST: Output current too high; outside permissible limits.
84
Equipment defect: Technical Service.
ICC 350 NEUROTEST: No output current. Interruption of the circuit or failure of the frequency
feedback system.
85 Check the neurotest cable supply lines or the handle, NE and cable and replace if
necessary.
Otherwise equipment defect: Technical Service.
ICC 350 NEUROTEST: Output current too low, but within the permissible limits.
Check the neurotest cable supply lines, or the handle, NE and cable, and replace if
86
necessary.
Otherwise equipment defect: Technical Service.
ICC 350 NEUROTEST: Output current too low; current is below the permissible limit.
87 Check neurotest cable.
Otherwise equipment defect: Technical Service.
ICC 350 NEUROTEST: Max. time limit has run out. The time limit monitor is a safety measure.
88
Only activate unit if necessary.
ICC 350 NEUROTEST: When switching on the power, already a neurotest activation signal.
89
Equipment defect: Technical Service.
ICC 350 NEUROTEST: Electronic fuse triggered or frequency feedback system has failed.
90
Equipment defect: Technical Service.
ICC 350 NEUROTEST: After switching on the neurotest function using the intensity adjuster, a
test determined that the electronic fuse was not triggered or the frequency feedback system
91
has failed.
Equipment defect: Technical Service.
Art. No.: 80116-201
09 / 2004
LED D2 lights red when the relay REL 1 is actuated and thus serves as a control.
09 / 2004
J 15 free
J 16–J 20 grey
J 17–J 21 brown
J 18–J 22 yellow
J 19 free
In the 115 volt range, the bridge-connected rectifier BR1 operates with the electrolyte capacitors C6, C7 as
a voltage doubler. The wire bridges must be connected as follows:
J 15–J 20 grey
J 16 free
J 17 free
J 18–J 21 brown
J 19–J 22 yellow
For the low voltage supply, there is a transformer TR 1 with rectifier BR2 and filter capacitor C15 on the
motherboard. Here an unregulated DC voltage is provided in the 24 volt range.
Since data are present on the databus for all parts of the circuit simultaneously, it is necessary to separately
determine for which part of the circuit the currently output data is intended. This is realized by the “Chipselect
method” by which the chip to be addressed is selected and addressed using a special “Chipselect signal.”
This signal activates only one among a number of addressable modules. These signals are generated within
the Multiplexer IC 4 and converted in the transistor arrays IC10 and IC11 to 15 volt CMOS level.
The PIO (Parallel Input Output module) produces data in a brief period of time for many different target
assemblies. While the data are only present briefly at the PIOs, the data for target assemblies should be
present longer. For this an independent external control bus and independent control lines are used. The
data for the signal lines are stored in the D-flipflops IC2 and IC3 and brought to the 15 volt CMOS level in
the transistor arrays IC8 and IC9.
For the external control bus, the PIO data only need to be brought to the 15 volt CMOS level in IC7.
an inductivity of the coils results which limits the high-frequency leakage current with this inductive
impedance.
With the ICC high-frequency surgical units, the low-frequency leakage current to the patient is measured.
At the first malfunction, this must not exceed 50 mA. Once this condition is ensured, the unit is permitted
to carry the CF designation (Cardiac Floating). If the possible low-frequency leakage current is under 500
09 / 2004
mA in the first case of malfunction, the unit is therefore not suitable for operations on the heart and has the
designation BF (Body Floating).
Initially the ICC is capacitance-grounded via capacitors C30 and C31 and the relay contact REL 2. The
advantages of capacitance ground are fully exploited. The low-frequency leakage current is measured via
the prescribed simulation R25, C28. If for any reason a low-frequency leakage current should appear, it is
then evaluated. If it exceeds the limit of 50 mA, the relay contacts REL 2 are then opened and thus a low-
frequency leakage current can no longer flow. The ICC thus fulfills the CF requirement for cardiac surgery
in every situation.
The voltage occurring in the simulation is proportional to the current and is compared in the operation
amplifier IC14 functioning as a comparator to the maximum permissible value that is prescribed and
adjustable via the resistor divider R22 and TP1. The signal for switching over the relay REL 2 is present at
the BF / CF output.
tone signal in this case is reproduced with the maximum amplitude at the tone output amplifier IC 2.
The R37, C9, C10, C11, R39 network is used for sound shaping, so that a pleasant sound results in the
09 / 2004
For example, if area 1 is activated, the emitter from transistor T2 is set high and gives its output voltage via
the trim potentiometer TP 11, resistor R45 and diode D2 to the measurement line U_NETZT, which also
leads at the power module to the sensor line of the switched-mode power supply's output voltage, but at the
same time also to the measurement system of the processor (trim potentiometer TP1 on the control board).
Transistor T2 can therefore be regarded as an extra-low voltage power supply, the output voltage of which
the HF generator of the power module uses to produce a minimal HF voltage and emit this as a test voltage
to the bipolar socket.
The internal impedance of this mini power supply unit is adjusted via the trim potentiometer TP11.
If the generator is now loaded with the tissue in the forceps (or with a 2.5 kOhm impedance), the supply
voltage at the internal impedance of the mini power supply unit collapses by a specific amount.
This voltage collapse is measured by the processor system and compared with the prescribed set values. If
they agree, the main power supply unit is switched on and the HF generator supplies the preset power.
The mini power supply unit cannot be fed in reverse due to the diode D2 (protective diode).
Since the internal impedance can be changed via the trim potentiometer TP11, the starting point of the
contact monitor can be adjusted here relative to the loaded impedance of the generator (tissue impendance).
The circuit receives the start-up signal and thus the necessary starting pulse from the processor via its PIO
on the CPU board and the transistor array IC8 on the motherboard.
09 / 2004
The HF_EIN signal is directed to the comparator IC14 on the control board, the output of which remains at
logical HIGH during activation.
When starting up, the ascending signal is differentiated via the RC element R19, C73 and moves to the gate
of the transistor T4 which then briefly connects through and triggers the monoflop IC16. This is the starting
pulse at which the generator begins to operate. Using the trim potentiometer TP15, the pulse length of the
first monoflop in the IC16 can be set and resulting in a symmetrical sine-wave characteristic for the generator
signal (adaptation to the parallel oscillating circuit).
The resetting of the first monoflop IC16 triggers a secondary pulse in the second monoflop IC16 which
represents the true actuation pulse for the output stage driver. The length of this actuation pulse is adjustable
using the trim potentiometer TP14.
The power module generator is therefore always only initiated at the start of a half oscillation through the
actuation pulse. Due to the oscillating circuit as load resistance, the oscillation is extended into a complete
sine wave.
For all further oscillations during an activation phase, the generator is fed back via the resulting sinus
signal. A part of the output voltage U_PRIM of the parallel circuit is directed to the comparator IC14, the
output pulses of which now trigger the monoflops IC16.
The power module generator therefore continues to oscillate as a feedback generator until the activation
signal HF_EIN is reaccepted by the processor.
In this way, it is ensured that the generator always oscillates exactly at the resonance frequency of the
oscillating circuit and the operating frequency need not be manually adapted to the production-related
tolerances of the oscillating circuit elements.
is no longer switched through for actuation of the QK output stage, but instead the output signal of the
comparator IC9, PIN 12.
This comparator detects the zero crossings of the high frequency current of the QK output stage and provides
a pulse at the rate of the HF at the priority encoder which switches this rate through to the actuation with
sufficient current flow of the output stage. In this way, the actuation has now been switched over from free-
wheeling by means of the start generator in a no-load case to feedback current control in a load case.
output stage:
• Is there an enable signal from the processor?
09 / 2004
sparking which occurs during the cutting and coagulation process at the active electrode. Both control
principles have concrete applications.
The control of spark intensity can be activated via the “HIGH CUT” key.
On the Senso-board, the DC voltage U_FUNKE occurring during a spark is gathered via an isolation
amplifier (description there) and directed to the control-board.
The required set value of the spark intensity is transmitted via the control bus to the digital analog converter
IC8. Its analog output signal is combined and compared at the comparator IC4 with the actual value of the
spark U_FUNKE. If the actual value is greater than the set value, output 12 tilts to frame potential and
illuminates the red LED D1. In addition, the output signal moves to the input Pin 2 of the NOR circuit IC5.
The gate IC7 with the monoflop IC10 switches off the QK output stage for a minimum period of time. In
this way, the supply voltage for the HF generator is reduced and therefore also the intensity of the spark.
stage is addressed. The output signals A and B thus serve in the selection of currently active transistors.
From the previously doubled frequency, the short start and stop pulses are produced for the respectively
active transistor.
The first part of the monoflop IC17 produces the start pulse, the second part the stop pulse.
The first part of the D-flipflop IC21 is additionally actuated by an ON_OFF signal for the safety circuits. In
this way, all start pulses can be suppressed on the one hand, while on the other, it is ensured that the
transistors can still be shut off in any case.
The arrangement of selection pulses for the individual transistors with the on/off pulses is made in the
NAND gate IC1 on the QK output stage.
Art. No.: 80116-201
09 / 2004
Circuit principle
The complementary output stage consists of two N channel MOS-FET transistors, T1 and T2, which are
operated alternately as switches. The amplified digital output signal is present at the source of transistor T1
and simultaneously at the drain of transistor T2, since these connections are conductively connected to each
other. However, since a sinusoidal output signal is a required condition, the output of the output stage is
switched to an oscillating circuit (which is located on the next PCB).
The QC output stage is actuated between the gate and source of the respective transistor, which always
leads to electric potential problems with this circuit logic, since the actuation signal has to be superimposed
on the output signal.
This problem can be solved by actuating the relevant transistor via a transformer. If this method is used for
both output stage transistors, it has the advantage that the actuation circuit can be completely isolated from
the output circuit and the high output voltages occurring in the event of a defect cannot damage the actuation
circuit.
The disadvantage, however, is that the transformer cannot transmit any DC signals.
This is where the gate-source capacitance of the MOS-FETs proves useful. Since this capacitance is of high
quality, the gate-source capacitance can maintain an applied charge for a sufficient length of time. The
clamping circuit consisting of diodes D8, D9, D10 and D5, D6, D7 has the effect that the gate-source
capacitance can be charged with a short positive pulse. This positive pulse is fed via diode D8 to the gate of
transistor T1 and charges the GS capacitance sufficiently for the transistor to be switched to a conducting
state.
This charge cannot then flow back into the actuation circuit after the actuation pulse has ended, since diode
D8 acts as a block and diode D9 also permits no reverse current due to its Z-diode characteristic. The result
is that the transistor remains in a conducting state as long as its GS capacitance has sufficient charge.
If, on the other hand, a sufficiently large negative pulse comes from the actuation circuit, the Z-diode
voltage at diode D9 is exceeded and the GS capacitance can be discharged again. Transistor T1 thereby acts
as a block.
It can thus be seen that a MOS-FET transistor can be operated in switching mode via such a clamping
circuit by means of a pulse transformer with short start and stop pulses.
Capacitors C4 and C5 are connected in parallel to the GS capacitance and support the effect described.
Since their capacitance is significantly higher than the corresponding gate-source capacitances, the circuit
becomes largely independent of parameter scatter of the gate-source capacitances of different production
batches.
It is the task of actuation to time the actuation process in such a way that each of the two power transistors
receives a short start pulse and, after a defined pause, a stop pulse at the right time. It must be ensured that
the two transistors are never switched to a conducting state simultaneously, since a short circuit of the
supply voltage would result!
Circuit description
The actuation signals are generated on the control board (30128-357). These signals are short pulses for
starting and stopping the output stage transistors and two additional pulses, one for selecting the upper
output stage transistor and the other for selecting the lower output stage transistor.
These pulses come via connector J1 to the NAND gates ½ IC1 and IC4 on the QC board. There the "Start"
and "Transistor A" pulses, for example, are brought together (as are "Stop" and "Transistor A"). The following
pulse sequences are thus present at the outputs of IC 1:
• Start transistor A
• Stop transistor A
• Start transistor B
• Stop transistor B.
These pulses are each preamplified in the triply parallel gates of the NOR circuits IC 2 and IC3. The outputs
of IC2 and IC3 actuate the driver stages, each consisting of two parallel transistors T3 to T10. The output
Art. No.: 80116-201
signal of the four parallel drivers is then amplified to such a level that the pulse transformers UE1 and UE2
can be operated with sufficient energy.
09 / 2004
In the case of a complementary output stage, it must be strictly ensured that the two output stage transistors
are not simultaneously in the activated state, as this would cause a short circuit across the two transistors
and damage the output stage beyond repair.
Therefore, the stop pulses generally have the highest priority. They ensure a safe state of the output stage
during undefined operation. The start pulses are separated in the actuation logic to ensure that only one
output stage transistor is actuated at any one time.
An undefined state could, however, occur in rare cases if the +15 V operating voltage is too low at any point
in time. For this possibility, in which the logic might operate undefined, a "Power-on time-delay circuit"
avoids undefined starting of the output stage transistor.
With transistor T11, the supply voltage VDD = + 15 V is monitored. If this voltage is missing, capacitor C10
is quickly discharged via diode D12. This logical LO signal is sent to the two NAND gates ½ IC 1 and
blocks the starting pulses. If the supply voltage is present, capacitor C10 is charged to 15 V via transistor
T11 and resistor R8 in a predefined delay time. This HI signal reaches the two NAND gates again (see
above) and enables the start pulses for the output stage.
On the secondary side of the driver transformers, short, steep spikes occur, initially a positive pulse for
starting, then a negative pulse for stopping the corresponding output stage transistor.
These spikes reach the gates of the MOS-FET transistors via the clamping circuit described above, and
switch the gates.
The amplified output signal is tapped at the two mutual connection points of the transistors.
Power module UL
Slot J5
The following assemblies are found on the PCB:
• Serial oscillating circuit for the QC power stage
• Generation of the operating voltage for the HF generator
• Driver and output stage of the HF generator
• Output circuit of the HF generator
• Measurement of various operating parameters
voltage can be taken from the transformer. This is required to operate the ST output stage to generate
especially high voltage peaks. This high voltage is switched off to protect the HF output stage by means of
the second contact from relay REL1.
Power module UL
Slot J5
Driver and output stage of the HF generator
The actuation signal for the HF output stage is generated on the control board (IC16) and fed to the power
module driver IC1 via the motherboard.
Due to the high-gate source capacitance of the output stage transistors T1 and T2, the driver must be able to
emit and accept high reactive currents when transferring this capacitance. That is why two drivers are
switched in parallel. The output current of the driver is restricted by the resistors R1 and R19 to protect the
driver.
The output stage transistors T1 and T2 are switched in parallel due to the necessary high current and
operate on output transformer UE1.
ST power stage
The ST power stage is used to generate high pulses for coagulation without a cutting effect, particularly for
quick superficial coagulation.
The designation “ST” output stage is derived from the abbreviation of spray generator for TUR.
The power control and the generation of actuation pulses are found on the control board.
The actuation pulses (TSI-STE) move to the driver IC4 and then to the ST output stage transistor T1. This
operates on the output transformer UE1, the secondary side of which emits the high frequency via the
capacitors C1 and C2 as well as the relays REL1, REL2 and REL3 at the connections AE and NE. The
emitted high frequency is fed to the outputs via the Senso-board.
The capacitors C1 and C2 serve as a high-pass for suppression of faradic effects and are also an additional
protection in isolating the patient circuit from the equipment circuit. Due to the necessary high electric
strength, two relay contacts each are switched in series.
The output relay is actuated via the relay driver IC7 which receives its actuation signals via the bus and the
target memory IC6 (D-flipflop).
The ST power stage is supplied with voltage that is switched with relay REL19 from the power module via
the connectors J2 and J3.
The integrated counter IC1 subdivides the frequency of the actuation signal of the ST output stage to a low
frequency, so that the frequency in the CPU can be determined by means of a counting loop.
Since the processor prescribes the actuation frequency, it receives feedback in this way as to whether the set
and actual values agree. This is important since the output power of the ST power stage is controlled via the
repetition frequency of the individual pulses.
Art. No.: 80116-201
09 / 2004
The spark monitor for monitoring the spark cycle at the electrodes
During the cutting process, for example, there is sparking at the active electrode. To maintain a consistant
quality for the cut, the spark must be recorded and controlled in its intensity.
Our generators produce sine-wave output voltages with a very low distortion factor. If a spark occurs in a
patient circuit, harmonic frequencies of the output signal are thus produced by the nonlinear characteristic
of the spark channel. Harmonics can be either harmonics or DC voltage. This is why one can also say
“rectifier effect of the spark”.
The DC voltage resulting in this way moves from the patient circuit to the spark monitor of the ICC. It
moves via the resistors R1, R2, R4 and R5 to the Z-diodes D1 and D2, switched antiserially, which limit the
signal to 15 volts. Then follows the operation amplifier IC2, switched as an isolation amplifier, which
makes the DC voltage signal durable.
The DC voltage proportional to the spark intensity in the patient circuit must now be evaluated by the unit
and fed isolated to the unit circuit. The remainder of the circuit is in principle an isolation amplifier: DC
voltage signal is chopped, fed isolated via a transformer to the unit circuit and then rectified again.
The oscillator module IC1 produces a square-wave signal with a pulse duty factor of 1:1, present at outputs
10 and 11 of the IC1. This is the chopper frequency which actuates the transistor T1 and T2 in push-pull
Art. No.: 80116-201
operation. This push-pull amplifier functions on the output transformer UE5, which is operated via the
isolation amplifier IC1 using the spark voltage as the operating voltage.
09 / 2004
In this way, the spark voltage is chopped from the transistors T1,T2 and fed via the transformer UE5 as an
isolation at the secondary side to the unit circuit as AC voltage.
Diode D15 then follows on the secondary side, which again rectifies the alternating signal thus resulting
and smoothes this by means of the capacitor C22.
In this way there is another DC voltage, proportional to the spark intensity, which is reduced via the resistor
divider R32, R33 and then fed to the isolation amplifier IC9. The output signal U_FUNKE moves from
there via the control board to control the processor.
The electronic components of this isolation amplifier within the patient circuit require an isolated voltage
supply to function. For this, a DC/DC converter is used which consists of a Colpitts oscillator (circuit
around Transistor T6), the alternating signal of which is transferred from the transformer UE6 to the secondary
side and rectified by diodes D4 and D6. The DC voltages thus resulting are limited to 9.1 volts by the Z-
diodes D3 and D5 respectively.
In this way, voltages of +9.1 volts and –9,1 volts are available to the electronic circuit within the patient
circuit which is identified with I+9 and I–9.
The symmetry of HF current on the halves of the neutral electrode is measured by a symmetrical transformer,
the output voltage of which is a function of current symmetry.
Implementation: The circuitry is found on the Senso-board. The oscillator is designed as a frequency-
selective feedback amplifier: The amplifier IC6 actuates the push-pull stage, consisting of the transistors T4
and T5, and passes the amplified output signal to the frequency-selective serial circuit made of capacitor
C20, coil L1 and the inductivity from the primary side of transformer UE4.
One part of the output signal at the transformer UE4 is picked up via the resistor R18 and fed to the active
bandpass from the operation amplifier IC5 and its wiring. The center frequency is equal to the resonance
frequency of the previously mentioned serial circuit.
One part of the output signal from the active bandpass is fed again in proper phase to the amplifier IC6,
such that the entire arrangement fulfills the oscillation condition and oscillates at the resonance frequency
as an oscillator.
The oscillator can be switched off via the transistors T7 and T8 by means of the disable signal OSZI_DIS
from the processor.
The resistance of the neutral electrode is determined by loading this oscillator with the resistance to be
measured. The voltage collapses on the internal impedance of the oscillator according to the load. Thus
every oscillator voltage can be assigned an appropriate resistance value.
The oscillator voltage is present at the input of the active bandpass and can be picked up at the output of the
operation amplifier IC6.
After peak rectification by diode D30 and capacitor C34, the measurement voltage U_NESSY can be
picked up at the isolation amplifier IC9 and moves via the adjustment on the control board (trim potentiometer
TP9 ) to the processor to determine the resistance of the neutral electrode.
The high-frequency output voltage for the neutral electrode is balanced by the capacitors C2 and C3 on
both lines to the neutral electrode, i.e. divided equally.
Whether the current on both lines to the neutral electrode is now of equal size, depends on whether the two
electrode halves of the split neutral electrode are applied with the same surfaces to the patient. By measuring
the symmetry of the current and the resistance, it is therefore possible to receive information as to whether
the electrode is applied well to the patient with this entire surface.
The high-frequency current flows via the two primary windings 1 and 2 of the transformer UE3 in such a
manner that the resulting magnetic flow is cancelled out by equally strong currents. Thus in this case, no
voltage is induced at winding 3 of the transformer UE3. The reverse is true: The more unsymmetrical the
Art. No.: 80116-201
using diode D9 and filtered with capacitor C57, then amplified using the operation amplifier IC9, so that a
signal U_SYM is available which moves via the control board to the processor for evaluation.
The current density is calculated mathematically from the following dimensions, now known:
• High-frequency current,
• Symmetry of the high-frequency current at the neutral electrode,
• Contact resistance of the neutral electrode to the body of the patient.
If, on the other hand, a key on the handle is pressed, a voltage needle for the converter voltage is dampened
by the Si diode integrated into the handle, so that the transmitter diode for the coupler IC1 can no longer be
09 / 2004
illuminated for the affected voltage needle and the appropriate transistor is no longer connected through at
exactly this voltage needle.
The output signal from the receiving transistor is directed to the two data inputs for the D-flipflops of the
IC3. These two D-flipflops additionally receive the actuation signals for the converter transistors, so that a
definite assignment is possible here between the dampened voltage needle and the actuation signal. The
two D-flipflops therefore function as a scanning circuit in proper phase, the output signal of which can be
assigned to the switched key in the handle.
Since a diode is switched in series for each of the two pushbuttons on the handle, although both diodes have
a definite and opposite polarity, this circuitry can be detected exactly via the dampened half-wave after
pressing a pushbutton, as to whether and which button was activated. Outputs 2 or 12 on the IC3 therefore
provide reliable information as to whether the “cutting ” or “coagulating” key was pressed. The information
that no key was pressed is just as possible as the information that both keys were pressed simultaneously.
Isolation of the fingerswitch monitor is complete via the transformer UE1 and via the optocoupler IC1.
The function of the second fingerswitch monitor is equivalent.
The two relays REL 1 and REL 2 are also found on the same PCB which safely separate the two output
sockets for the active electrodes from the generator circuit when the unit is not activated, while connecting
only the activated output socket to the generator when the unit is activated.
Due to the higher electrical strength that can be achieved, two relay contacts are switched in series.
The two relays are activated from the CPU via the target memory D-flipflops IC8 and the transistors T3,
T4.
through the transistor T21 and forming the operating board bus B1BUS, which now addresses the target
memory of the display board in conjunction with the corresponding independent chipselect signal from the
inverter IC8 and the required assemblies.
09 / 2004
The rows of the keyboard are multiplexed via the target memory IC1; this produces the row actuation
pulses TZ1 to TZ4 (keyboard row).
If a specific key is now activated, this sends its answer during its activation time via the row actuation pulse
as an output signal via a line for the keyboard columns TS2 to TS3 to the keyboard encoder IC11, which
forms a 4 bit binary number from this and directs it via its output to the CPU for evaluation.
Target memory and drivers for rows and columns of the display matrix
The LED matrix is actuated by the already described internal bus system B1BUS of the display board.
The 8-fold D-flipflops IC2, IC3 and IC12 are used as target memories for columns (IC2) and rows (IC3).
The columns of the lamp matrix LS1 to LS6 are activated via the driver transistors T2, T20, T11, T10, T4
and T9 switched as emitter followers in a multiplex method and each switched for a brief time to +5 volts.
The current is then led via the appropriate LED and directed via the necessary current limitation resistors as
well as the transistor array IC4 to chassis.
The blue LEDs D36 and D37 for display of the coagulation channels are an exception, the anodes of which
are permanently at +5 volts via the current limitation resistors and are switched on via the transistor array
IC13.
The “upper wiring module” PCB directs the rectified supply voltage from the motherboard via the plug J14
as a supply voltage to the QC power stage. In addition, this PCB is used as a connection between the QC
power stage and the power module, since currents of this dimension cannot be directed via the motherboard.
The lines between the QC power stage and the motherboard are directed through a ferrite core to reduce
interferences from the QC power stage into the network.
CAUTION
This PCB is at supply voltage potential
Art. No.: 80116-201
09 / 2004
Gezeich. = Drawn
Geprüft = Checked
V 2.0 / V 4.0
Freigabe = Approv.
Datum = Date*
Name = Name
Maßstab = Scale
Datei = File
Projekt = Project
Benennung = Title
Nummer = Number
V 2.0 / V 4.0
Gezeich. = Drawn
Geprüft = Checked
Freigabe = Approv.
Datum = Date*
Name = Name
Maßstab = Scale
Datei = File
Projekt = Project
Benennung = Title
Nummer = Number
V 2.0 / V 4.0
Gezeich. = Drawn
Geprüft = Checked
Freigabe = Approv.
Datum = Date*
Name = Name
Art. No. 80116-201
Maßstab = Scale
Datei = File
09 / 2004
Projekt = Project
Benennung = Title
Nummer = Number
DBUS
A13
178 / 266
VNOT
IC1 IC2 IC3
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
A0-A15 A14 1 D0-D7
68nF
68nF
68nF
68nF
68nF
68nF
68nF
68nF
68nF
68nF
N.C.
30 28 A0-A15 10 11 D0-D7
M1
27 M1 A0 VCC 11 A0 D0
D0 9 12
A1 31 12 A1 D1
A0-A15 10 D1 8 13
19 MREQ A2 32 A0 13 A3 D2
GND MREQ D2
33 9 7 15
IORQ
20 IORQ A3 A1 15 A2 D3
8 D3 6 16
21 RD A4 34 A2 16 A4 D4
RD D4 VNOT
CPU PCB
Vcc VNOT Vcc Vcc Vcc Vcc Vcc 35 7 5
A5 17
C11 +5V WR
22 WR A5 A3 17 D5 30128-052
+24V +5V +5V +5V +5V +5V 6 D5 4 18
A6 36 A4 18 A6 D6
R14 5 D6 3 19
GND 28 RFSH A7 37 A5 19 JP1 A7 D7
68nF 4 D7 25
5k6 A8 38 A6 A8
R3
R12
R11
R10
R6
R13
39 3 24 20
8k2
5k6
5k6
5k6
5k6
5k6
IC10 WAIT
18 HALT A9 A7 A9 CE
2 40 25 21
A10 A8 20 A10 OE 22
VNOT R5 24 CE1 CE_OUT 23
3 5 24 WAIT A11 1 A9 26 A11
VCC BAT ON CE2
1 15 2 21 2
VBAT RES RES 5k6 A12 A10 22 A12
23 OE 26
16 RES 16 INT A13 3 A11 27 A13
RES INT R/W
10 4 2 27
PFD 17 NMI A14 A12 A14
9 C15 1
R1
PF1 14 A15 5 5864 A15
2k2
WD0
11 WDI 26 RESET
WD1 RES 27C512
13 10nF CE_IN Vcc D0 14
CE IN WR
+5V 25 15
BUSREQ D1
23 BUSACK D2 12
7 IC8 Vcc IC11
+
OSC D3 8
CE OUT 12 CE_OUT +5V 4
3V
6 CLK D4 7 DMUX 15 6
BT1
8 LOW LINE 6 CLK A13 1 0 5 &
OSC SEL D5 9 0 14
GND 4 A14 2 0 1
D6 10 G 13 74HC00
MAX691 A15 3 7 2
D7 13 2 12
Vcc 3
R4
D2
+5V 4 11
1k
6 &
1N4148
Z84C00 D0-D7 10
GND GND GND GND GND 4 5
GND 9 IC15
5 6 CE_IN
MREQ 7 4
7 6
PIC-CLK 5 &
74HC138 IC15
SIO-CLK
1 74HC00
IC12 3
R21 2 &
CLK 10 9
CLK Q1
220R 7 IC9 74HC00
Q4
Q5 5 DMUX 15 CS4
Vcc Vcc A3 1 0
IC13 4 0 14
R20
+5V IC13 +5V Q6 A4 2 0 1 CS5
220R
Vcc IC16 10 6 G 13
4 S 9 Q7 A5 3 7 2 CS6
+5V S 2
ICC 200, 300, 350
G 5 11 13 12 CS7
1 EN OUT 5 3 C Q8 3
C 12 12 11
2 D 8 Q9 6 & 4 CS8
D 6 13 14 M1 10
1 R Q10 4 5 CS9
SG531P R 15 GND 9
Q11 R19 5 6 CS10
74HC74 1 7
74HC74 Q12 J2/7C 7 CS11
IORQ
2 220R
Q13
11 3 74HC138
RES R Q14
74HC4020
5
Vcc Vcc Vcc
Diese Zeichnung ist urheber-
+5V IC11 +5V IC15 +5V IC15 B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
1 9 12 Weitergabe und Vervielfltigung ICC
3 8 11 Gezeich. 29.07.92 M.Fritz ohne unsere Genehmigung
2 & 10 & 13 & unzulssig
Gepr ft Benennung/Title
74HC00 74HC00 74HC00
LP un.: 40128-026 CPU
LP bs.: 30128-052
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 1 von 3 30128-052
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
ABUS
5
DBUS
CIRCUIT DIAGRAMS
IORQ IORQ 31 31 PIC-RTCC 31 FUSS-B1 31 J2/25A
B4 MC-FREI B4 B4 B4
35 32 35 32 J1/22 35 32 FISCH-B2 35 32 J2/26C
RD RD B5 J2/7C RD RD B5 RD RD B5 RD RD B5
33 33 J1/21 33 FUSS-A2 33 J2/26A
B6 WDI 25 B6 25 B6 25 B6
25 CLK CLK 34 CLK CLK 34 CLK CLK 34
CLK CLK 34 B7 J2/8C B7 FISCH-B3 B7 J2/27C
B7 J2/6C
23 23 23 23
INT INT INT INT INT INT INT INT
24 BRDY 21 24 BRDY 21 24 BRDY 21
Vcc
+5V
24 BRDY 21 IEI_5 IEI IEI_6 IEI IEI_7 IEI
IEI BSTB 17 BSTB 17 BSTB 17
22 BSTB 17 22 22 22
IEI_5 IEO IEI_6 IEO IEI_7 IEO IEO
Vcc
+5V Vcc
+5V
DBUS IC14
R18 IC11 IC11
6 J2/9A
D0-D7 D0 9 12
+
1k RES 8 11
7 10 & 13 & M1_PIO
D1 AIN1 4 R17 M1
C20
C14
8
R9
R7
J2/8A
68nF
15uF
D2
22k
680k
9 3 74HC00 74HC00
D3 AIN2 1k
17 R16 D1
D4 GND GND
18 J2/7A
D5 AIN3 2 1k 1N4148
19
D6 R15
20
+
ABUS D7 D AIN4 1 J2/6A
A0 22 A 1k
R8
C13
A0
5M6
15uF
A1 21
ICC 200, 300, 350
A1
Vcc
+5V GND GND
5
4
3
2
9
8
7
6
10
RD RD VREF+ 14
15
C16
C17
C18
C19
WAIT RDY
180nF
180nF
180nF
1nF
16 13
RN1
8*1k
CS8 CS VREF-
GND
AD7824
1
GND GND GND GND GND
179 / 266
R24
J1/8 J1-8
2k2 VNOT J3
J1 Vcc 1 2
R23 R26 R25 +5V J2 CS9
J1-9 1 2 3 4
J1/9 C1 A1 CS10 M1_PIO
GND Vcc
180 / 266
2k2 2k2 3 4 2k2 5 6
+5V C2 A2 RES WR
R22 5 6 A10 7 8 A9 ABUS
F-GND C3 A3 ABUS
J1/10 J1-10 7 8 J1-8 A8 9 10 A7
C4 A4 GND
2k2 9 10 J1-10 A6 11 12 A5
J1-9 C5 A5
11 12 J1-12 A4 13 14 A3
J1-11 C6 A6
13 14 J2/6C J2/6A
J1-13 J1-14 A2 15 16 A1
C7 A7 J2/7A
15 16 J2/7C A0
J1-15 J1-16 C8 A8 17 18 RD
17 18 J2/8C J2/8A
CPU PCB
J1-17 J1-18 A11 19 20 A12
C9 A9 J2/9A
30128-052
19 20 A13 21 22 A14
J1-19 C10 A10
21 22 J1-22 A15 23 24
J1-21 C11 A11 SIO-CLK
8*2k2 23 24
J1/11 J1-11 J1-24 D4 25 26 D3 DBUS
8 9 C12 A12 DBUS
J1-12 25 26 J1-26 D5 27 28 D6
J1/12 7 10 J1-25 C13 A13
27 28 J2/13C FUSS-A1
J1/13 J1-13 J1-27 J1-28 D2 29 30 D7
6 11 C14 A14 FUSS-B1
29 30 FISCH-A2 D0 D1
J1/14 J1-14 J1-29 J1-30 C15 A15 31 32
5 12 FISCH-B2 FUSS-A2
J1-15 31 32 J1-32 33 34
J1/15 4 13 J1-31 C16 A16 INT CS11
33 34 FISCH-B3 FUSS-B2
J1/16 J1-16 J1-33 J1-34 C17 A17 35 36 IORQ
3 14 FISCH-A3 FISCH-A1 MREQ
J1-17 35 36 F-GND 37 38
J1/17 2 15 J1-35 C18 A18
37 38 J2/18C FISCH-B1
J1/18 J1-18 F-GND C19 A19 39 40
1 16 J2/19C
39 40
Vcc
+5V
+5V
Vcc
RA3 J1-40 C20 A20 GND GND
J2/20C
8*2k2 C21 A21
J1/19 J1-19 Vcc
8 9
J1-21 +5V C22 A22
J1/21 7 10
J1-22 C23 A23 J2/23A
J1/22 6 11 SICHER
J1-24 C24 A24 J2/24A
J1/24 5 12 J2/24C
C25 A25
C12
J1/25 J1-25 J2/25C J2/25A
68nF
4 13
J1-26 C26 A26 J2/26A
J1/26 3 14 J2/26C
GND C27 A27
J1/27 J1-27 J2/27C J2/27A
2 15
J1-28 IC17 C28 A28 J2/28A
J1/28 1 16 J2/28C
RA2 17 RA0 RB0 6 FISCH-A1 C29 A29 J2/29A
MC-FREI J2/29C
8*2k2 18 RA1 RB1 7 FISCH-B3 C30 A30 J2/30A
FISCH-B1 J2/30C
J1/29 J1-29 1 8 C31 A31
8 9 FUSS-B2 RA2 RB2 FISCH-B2
J1-30 +24V J2/31C
J1/30 7 10 2 9 C32 A32
Vcc SICHER RA3 RB3 FISCH-A2 RES
J1/31 J1-31 +5V R2 10
6 11 RB4 FUSS-A1
J1/32 J1-32 11
5 12 15 OSC2 RB5 FUSS-B1
J1/33 J1-33 2k2 12
4 13 PIC-CLK
16 OSC1 RB6 FUSS-A2
J1/34 J1-34 3 13
3 14 PIC-RTCC RTCC RB7 FISCH-A3
J1/35 J1-35 4
2 15 RES MCLR
RES J1-40
1 16
RA1 PIC16C54
ICC 200, 300, 350
5
Diese Zeichnung ist urheber-
B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC
Gezeich. 29.07.92 M.Fritz ohne unsere Genehmigung
unzulssig
Gepr ft Benennung/Title
CIRCUIT DIAGRAMS
ICC 200, 300, 350
CPU PCB (bare)
40128-026
Art. No. 80116-201
09 / 2004
C47 C32
ec380_17
+ ec380_17
+
GND
GND
1000uF 1000uF
R34 R33 R26 R25
$plname $plname $plname $plname
GND
GND
ec50r25
+ ec50r25
+
GND
GND
D7 2u2 2u2
$plname C37
2
GND
5V6
$plname
ec50r25
+
GND
R42
4
2u2
14
$plname C35
3
1
GND
T2
100R 13
ec50r25
+
SOFT
GND
C52
BC557
2u2
PFAIL
C34
VSTART
11
+ 2
ec50r25
VREF RD
+
GND
ec50r25
4
2u2
GND
14
C50 2u2
5 10
13
+ 6
GND
ec50r25 C38
INP SYNCIN
SOFT
GND
$rpname
$plname
2u2 15
PFAIL
GND
C49
IC1
VSTART
11
$plname
2 16
GND
VREF RD
330pF
L4972
ec50r25
+
GND
6
FCOMP
GND
GND
C53 22k
INP SYNCIN
22nF
$rpname
$plname
15 R28
GND
IC6
17 1
$plname
16 $plname
GND
330pF
L4972
GND
36k
BOOTS
$plname
FEEDB
OUT
$plname $plname
RESOUT
FCOMP
GND
GND
R36
20
17 1
$plname
D2
GND
36k
BOOTS
C55 $plname
GND
U_IN
18 SB340
R OSC C
FEEDB
OUT
$plname
C41 C42
GND
2n2 R29
9
$plname
C17
20
$plname $plname
GND
$plname 1000uF
UE1
GND
$plname $plname
GND
$plname $plname
GND
$plname
L3
2 8
GND
U_NEG
7
$plname 2n2
200uH
8
30121-037 R17
R12
INP
$plname
OSC
14
$plname
GND
nderung
15k
4
F.COMP
GND
GND
GND
GND
$plname
L4962
GND
EN_5V
c100 c100
10
+
FEEDB
ec50r25
Datum
15
SOFT
GND
GND
GND
C59 C46
D1
ec130r50
+ ec130r50
+
GND
GND
$plname
Name 100uF 100uF
GND
SB340
C60 C45
A
R13 C26
ec130r50
+ ec130r50
+
$plname
GND
GND
$plname
0.7
0.7
100uF 100uF
GND
100R 1nF
L1A
Blatt
Gepr ft
C61 C44
5
$plname
LP un.:
L1
ec130r50
+ ec130r50
+
GND
GND
100uH
100uF 100uF
8
20-07-94
Gezeich. 20-07-94
$plname $plname
$plname $plname R22 R23
GND
GND
1 von 2
+5V
Vcc
$plname $plname
Vdd
+15V
40121-060
GND
4k7 18k
L1B
Name
1.0
LP bs.: 30128-410
40121-060
M.Fritz
C28
J.Beller
c100
U_NEG
GND
1uF
C29
unzulssig
ec130r50
+
GND
Diese Zeichnung
$plname
100uF
2n2
C67
D6
C30
MUR120
GND
MP4
C63
100uF
$plname
+ ec130r50
daher
GND
220R
R50
220uF C31
ist urheber-
$plname 100uF
2
GND
100nF
I
LED6 R15
$plname
ICC
$plname
$plname
to220l
GND
1 rot 3k3
G
D5
79xx
-15V
IC10
+24V
Gert/UNIT
GND
1N4148
C62
30128-410
Benennung/Title
3
+ $plname
GND
1uF
Vee
LED1 R19
Zeichnungsnummer/DWG.NO
-15V
$plname $plname
GND
rot 2k2
Kleinsp.Netzteil
0.7
Kleinsp.-Netzteil
30128-410
Low Voltage Supply
ICC 200, 300, 350
Art. No. 80116-201
09 / 2004
Vdd
5
IC4
+15V MP1
4
R1 RES IC8
7
DCH R5 R10
6 2 1 1 1
10k TP2 R4 THD OUT 3
2 10k 5k1
TRG
10
200k 100k 5 13
CV 4066 1
n.best
1
2 J2
4066
NE555 BS170
1
n.best
T1
IC8
R11
12
2
51k
TP1
C3
C4
3
1
3
10nF
10nF
GND GND 4
11
IC5 5
R16
100k
4 MP2 Vdd
R2 RES IC8 +15V
30128-410
7
DCH R7
6 3 1 1 4
10k TP3 R6 THD OUT 3 IC2 1
2 J3
TRG 10k GND +
C10 TDA7052 5 1
200k 100k 5 5
CV 4066 2 2
NE555 8 3
6n8
GND 4
+
Vdd
3 6 +15V
C5
C6
R37
C11
R39
C9
n.best
CIRCUIT DIAGRAMS
1uF
10nF
10nF
2k2
68nF
5k1
+
GND GND
GND GND GND GND GND GND
C16
IC7
3u3
4 MP3 J1
R3 RES GND
7
IC8
DCH A1
Low Voltage Supply
9 8 R9
10k TP4 6
THD OUT 3
1 1 A2
R8
2 10k A3
TRG GND
200k 100k 5 6 A4
CV 4066 +24V
A5
NE555 Vee
-15V Vdd A6
+15V A7
C1
C7
C8
Vcc A8
68nF
10nF
10nF
GND GND GND
+5V
A9
IC9 A10
TON1
R24 A11
1 TON2
RESET R TON-CPU
9 A12
CS-TON C1 10k TON3
A13
ALARM
3 2 A14
TON1 1D TIMEROFF
4 5 A15
TON2 RESERVE
6 7 A16
TON3
11 10 A17
ALARM
13 12 A18
TIMEROFF CS-TON
14 15 A19
RESERVE RESET
A20
40174 TON-CPU
A21
ICC 200, 300, 350
A22
RN1 A23
2
RESET
3 A24
CS-TON Vdd
9 A25
TON1 +15V
8 +24V A26
TON2 1
7 A27
TON3
6 A28
ALARM
5 A29
C2
R21
TIMEROFF
A30
68nF
n.best
4 MUR120
RESERVE GND
8*10k A31
U_IN
D4 A32
C18
C65
C66
68nF
68nF
68nF
LP un.: 40121-060 Kleinsp.Netzteil
GND
LP bs.: 30128-410
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 2 von 2 30128-410
183 / 266
Vdd IC4
+15V MP1
4
R1 RES IC8
7
DCH R5 R10
6 2 1 1 1
10k TP2 R4 THD OUT 3
184 / 266
2 10k 5k1
TRG
10
200k 100k 5 13
CV 4066 1
n.best
1
2 J2
4066
NE555 BS170
1
n.best
T1
IC8
R11
12
2
51k
TP1
C3
C4
3
1
3
10nF
10nF
GND GND 4
11
IC5 5
R16
40121-060
100k
4 MP2 Vdd
R2 RES IC8 +15V
7
DCH R7
6 3 1 1 4
10k TP3 R6 THD OUT 3 IC2 1
2 J3
TRG 10k GND +
C10 TDA7052 5 1
200k 100k 5 5
CV 4066 2 2
NE555 8 3
6n8
GND 4
+
Vdd
3 6 +15V
C5
C6
R37
C11
R39
C9
n.best
10nF
10nF
2k2
1uF
68nF
5k1
+
GND GND
GND GND GND GND GND GND
C16
IC7
3u3
4 MP3 J1
R3 RES GND
7
IC8
DCH R9 A1
6 9 1 1 8
10k TP4 R8 THD OUT 3 A2
2 10k A3
TRG GND
200k 100k 5 6 A4
CV 4066 +24V
A5
Vee
Low Voltage Supply (bare)
NE555
-15V Vdd A6
+15V A7
C1
C7
C8
Vcc A8
68nF
10nF
10nF
GND GND GND
+5V
A9
IC9 A10
TON1
R24 A11
1 TON2
RESET R TON-CPU
9 A12
CS-TON C1 10k TON3
A13
ALARM
3 2 A14
TON1 1D TIMEROFF
4 5 A15
TON2 RESERVE
ICC 200, 300, 350
6 7 A16
TON3
11 10 A17
ALARM
13 12 A18
TIMEROFF CS-TON
14 15 A19
RESERVE RESET
A20
40174 TON-CPU
A21
A22
RN1 A23
2
RESET
5
3 A24
CS-TON Vdd
9 A25
TON1 +15V
8 +24V A26
TON2 1
7 A27
TON3
6 A28
ALARM
5 A29
R21
C2
TIMEROFF
A30
n.best
68nF
4 MUR120
RESERVE GND
8*10k A31
U_IN
D4 A32
C18
C65
C66
68nF
68nF
68nF
LP un.: 40121-060 Kleinsp.Netzteil
GND
LP bs.: 30128-410
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 2 von 2 30128-410
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
+15V
5
U_INP
MP1
C20
NT_EIN
Vdd IC12
68nF
+15V R67
Vdd Vdd IC18 1 GND IC13
+15V +15V =1 3
5 2
AST 1k 11
4
AST 12 &
6 4030
-TRIG 10
C15
R51
R58
8 10
R52
100pF
Q
7k5
560R
+TRIG 13
1k
5 12
G GND R
- GND RTRIG 15 9
IC9 9 Q 11 CX
12 MR
20k
LM319 GND 2
RX
C21
4 13 14
TP13
33pF
+ OSC OUT RX/ CX
3 1 GND
CX
4528
1
D11
D12
R53
R88
30128-357
IC11
C28
10R
8k2
R65
1N4148
100pF
3
43k
GND GND GND GND RCX EA
6
4047 IA0
5
Vdd Vdd Vdd IA1
OA 7 IC21 IC21
Control board
R59
R69
EIN_AUS D 2 D 12
2 B
4k7
1k
CIRCUIT DIAGRAMS
IC13 S1 4
R 10
R
10
- 5
IC9 10 GND GND
7 4 & IB0 4013 4013
LM319 GND 11
R56 6 IB1
9 12 OB 9
+ 3 IB2 AN
8 R 13
1k 1 7 IB3 Vdd
CX IC17 +15V IC17
EB
R60
5 11
180R
4539
R68
C16
15 Vdd 4 12
9k1
GND GND 2 GND & &
2n2
RX/ CX +15V GND 6 10 AUS
4528 3 13
R R
1 7 15 9
Vdd
CX CX
+15V
R77
R86
C31
C32
5k6
5k6
2 14
33pF
33pF
Vdd Vdd RX/ CX RX/ CX
+15V +15V
4528 4528
R49
R54
R57 D10 Vdd Vdd Vdd
2k2
4k7
10 +15V +15V C30 +15V
-
10k 1N4148 IC4 7
GND
IPB Vdd
LM319 68nF
+15V
R78
9 + GND
1k
8 IC16 IC16
5 11
R70
R61
R50
R48
4 12
C10
4k7
& & MP2
820R
10k
560R
2n2
5 6 10
GND GND GND GND GND - 3
IC14 3 13
12 R R
ICC 200, 300, 350
D16
D15
T4 CX CX
4 2
1N4148
1N4148
+ BS170
3
TP15
TP14
5k
C22
5k
C29
1
2 14
100pF
100pF
D14
3V6
R72
R71
R73
D17
D13
3V6
33k
100R
1k
1N4148
4528 4528
U_PRIM GND GND GND Vdd GND GND GND
+15V
R81
R80
470R
1k
R76
C19
Vdd
1k
220pF
Vdd Vdd Vdd +15V
+15V C12 +15V C9 +15V C18
R74
68nF 68nF 68nF
10k
11 11 11 Diese Zeichnung ist urheber-
10 C Datum Name rechtlich gesch tzt, daher
Gert/UNIT
+ + + HF_EIN -
Weitergabe und Vervielfltigung
IC9 IC4 IC14 IC14 7 Gezeich. 15.02.94 Fritz ohne unsere Genehmigung ICC
LM319 LM319 LM319 LM319 GND unzulssig
Gepr ft 28-11-94 Hagg Benennung/Title
- - - 9 +
6 C11 6 C8 6 C17 8
C 3584 C37,C38=330pF 30-1-96 Fritz
LP un.: 40128-095 CONTROL-BOARD
GND GND GND
R75
68nF 68nF 68nF
10k
Vee Vee Vee B 3371 R12=10R 11-94 Fritz LP bs.: 30128-357 Zeichnungsnummer/DWG.NO
-15V -15V -15V GND GND
Nr. nderung Datum Name Blatt 1 von 3 30128-357
185 / 266
Vdd
+15V C3
4
68nF GND Vdd Vdd Vdd
+ +15V +15V +15V
IC1 C26 R83 C25
186 / 266
TL084 GND MP5
- GND
1k
STEUERBUS
C1 IC8 68nF 8 IC12 68nF IC12
5 18 GND
11
IC15 6 8
+ =1 4 =1
GND
D0-D7 13
D0 VOUT 2 4 Vin Fout
1 5 1N4148 9
Vee 68nF
-15V 12 Vdd 3 RT
D1 U
11 +15V 7 4030 D18 4030
D2 CT F
10 6 CT DGND
2
D3
C23
C24
R47
R82
R12 9 -
R79
33pF
1nF
1k
1k
D4
4k7
U_FUNKE U_FUNKE/2 AD654 3 GND
8 5 10k
D5
10R 7
D C7 GND
30128-357
R38
R84
C27
5
5k
D6
4k7
2k
1nF
6 - T5
D7 IC4 2 TP16
TP8
A 2n2 12 BS170
LM319 GND 1
GND R36 GND
Vcc 4
20k
R43
Control board
+5V +
4k7
16 3
R85
2k LDAC
TP17
10k
FUNKE_AUS
15 GND MP3
13 CS_DAC2 WR GND GND GND
R11 - 14
D1
CS IC12
rot
IC1 Vdd
D7
U_PHASE 14 17
3
ANALOG_3 RESET RES +15V 13
1N4148
3k3 R10 TL084 =1 11 TSI_STE
12
5k
R44
12 +
10k
3 1 4
2
STE_EIN
AD7224
TP7
10k GND T1 4030
BC547
R35
1
Vcc GND
2k
+5V GND
IC10
GND GND
5
Vdd 4 &
Vdd IC5 +15V GND
+
R23 6 IC7
Vcc +15V 2
R55
3 2
C6
+5V
1k
3 R
3u3
2k GND GND
1 7 3
4 CX 1
6 4 & EIN_AUS
R4 - GND 5
R62
STEUERBUS
13 5
C13
IC1 19 3
D5
4k7
UP_HF 7 IC6 9 1 2
2n2
ANALOG_1 RX/ CX
1N4148
3k3 R5 TL084 10 4082
5k
D0-D7 18
REF
VCC
5 +
D0 11 4528
17
TP3
10k D1 12
16 C0 2
D2
C37
R24
15
330pF
2k
D3 4078
GND GND GND 14 C1 1
D4
R22 13 IPB
Vcc D5 D
+5V 12
D6 A IC10
2k 11 C2 24
D7 11
2 10
R6 - DAC_A0 A0 Vdd 12 &
IC1 9 +15V GND
D6
IP_PAT 1 DAC_A1 A1 C3 23 10
ANALOG_2
1N4148
3k3 R7 TL084 13 IC7
5k
3 + R
8 15 9 9
CS_DAC1 WR CX
TP4
10k 10
ICC 200, 300, 350
7 13
CS
R66
11 &
C38
R21
C14
3k9
14
330pF
2k
2n2
ANA0
ANA1
ANA2
ANA3
RX/ CX 12
GND
GND GND GND MAX516 5 4 21 20
R3 4528 4082
U_NETZT
5k6
n.best
U_NETZT/2
R25 U_INT_A
R1
TP1
5k1
GND GND
68k
R26
RESET
5
U_INT
NT_EIN
SICHER
-
3k3 IC2 1
LM324
D9
1N4148
+
3 +
5k
Diese Zeichnung ist urheber-
C Datum Name rechtlich gesch tzt, daher
Gert/UNIT
C36
TP2
15uF
Weitergabe und Vervielfltigung
Gezeich. 15.02.94 Fritz ohne unsere Genehmigung ICC
GND GND
GND unzulssig
Gepr ft 28-11-94 Hagg Benennung/Title
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
5
1
R MP6
RESET
9
CS_DFF1 C1
Vdd
U_FUNKE/2 0.6
+15V
D0 3 2
1D DAC_A0
U_NETZT/2 Vdd D1 3u3 3u3
C5 4 5 DAC_A1
+15V + +
U_INT_A D2 6 7 MUX_A0
R28 GND D3 11 10 C33 C34
468nF MUX_A1 Vee
D4 13 12 GND
+ MUX_A2 0.6 -15V
6k8 IC2 D5 14 15
6 MUX_A3
- LM324
STEUERBUS
0.8
IC2 - 40174
7
11C4 J1
LM324 IC20
5 + A1 B1
1
Vee GND RESET R A2 B2
68nF 9
C1
IC3 -15V CS_DFF2 A3 B3
GND
30128-357
R27
4067 10 +24V A4 B4 +24V
750R
A0 MUX_A0 D0 3 2
1D BER_1 A5 B5
GND 11 MUX_A1 D1 4 5
A1 BER_2
14 Vee Vdd A6 B6 Vdd
A2 MUX_A2 D2 6 7
R8 FUNKE_AUS -15V +15V A7 B7 +15V
Control board
13 MUX_A3 D3 11 10
UP_HF_A A3
15 Vcc A8 B8 Vcc
INH D4 13 12
3k3 +5V A9 B9 +5V
5k
GND D5 14 15
D0 A10 B10
9 ANALOG_1
STEUERBUS
TP5
Y0
CIRCUIT DIAGRAMS
40174 D1 A11 B11
GND
8 ANALOG_2
Y1 D2
7 Vcc A12 B12 ANALOG_3
R9 Y2 R33
+5V D3 A13 B13
6 ANALOG_4
IP_PAT_A Y3 MP4 D4
5 2k A14 B14
3k3 Y4 9 D5
STEUERBUS
A15 B15
5k
4 -
Y5
D8
IC1 D6 A16 B16
3 8
TP6
ANALOG_4
1N4148
Y6 D7
GND 2 R37 TL084 A17 B17 SICHER
Y7 1
C35
10 + A18 B18
23 Z NT_EIN
180nF
R17 Y8 RESET
GND 22 1k A19 B19 HF_EIN
U_NESSY Y9 CS_DAC1
100R 21 A20 B20 STE_EIN
CS_DAC2
R34
Y10
5k
C2
A21 B21
2k
20 TEMP
1nF
Y11 CS_DFF1
GND GND A22 B22
TP9
19 CS_DFF2 TSI
Y12
GND 18 A23 B23 A
Y13 Vdd U_PRIM
R13 17 +15V A24 B24 B
Y14 TSI_STE
U_SYM 16 A25 B25 AN
Y15 I_HFL
3k3 A26 B26 AUS
RES_ANA2
A27 B27 U_INP
R14
RES_ANA1
5k1
D4
8V2
A28 B28 U_INT
IP_PAT
GND A29 B29 U_NETZT
3
IP_PAT_A
R18 A30 B30
UP_HF U_FUNKE
I_HFL R64
2 A31 B31 U_SYM
3k3 BER_1 UP_HF_A
T2 A32 B32
5k
10k U_PHASE U_NESSY
BC547
R2
3
TP10
n.best
1
GND GND Vdd R63 TP11 R45 D2
2 T3
R15 +15V +24V BER_2 BC338
10k 500R 100R 1N4148
ICC 200, 300, 350
RES_ANA1
TP12 U_NETZT
3k3 1 R46 D3
R39
R41
STEUERBUS
RN2
10k
10k
R16
500R 68R 1N4148 2
3k3
RESET
3 RN1
GND CS_DAC1 D0 2
R19 4 Vdd D1 3
CS_DAC2
R40
R42
5 +15V
2k
2k
RES_ANA2 CS_DFF1 D2 4 Vdd
1
3k3 GND GND 6 D3 5 +15V
CS_DFF2
7 1
D4 6
R20
NT_EIN
3k3
R32 8 D5 7
HF_EIN
GND 9
SICHER D6 8
R29 R31 2k 8x10k D7 9
13
- 10k 8x10k
4k7 12k IC2 14 STE_EIN
9
- LM324 R87
IC2 8 12 +
LM324 Diese Zeichnung ist urheber-
C Datum Name rechtlich gesch tzt, daher
Gert/UNIT
10 + GND
TEMP Weitergabe und Vervielfltigung
Vee Gezeich. 15.02.94 Fritz ohne unsere Genehmigung ICC
-15V unzulssig
Gepr ft 28-11-94 Hagg Benennung/Title
R89
R30
10k
4k7
GND GND
C 3584 C37,C38=330pF 30-1-96 Fritz
LP un.: 40128-095 CONTROL-BOARD
B 3371 R12=10R 11-94 Fritz LP bs.: 30128-357
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 3 von 3 30128-357
187 / 266
ICC 200, 300, 350
Control board (bare)
40128-095
+15V +15V
5
J1
C7
C6
68nF
68nF
A1
A2 GND GND
A3
GND
A4 IC2 Vdd
3u3
+15V
C12
+
A5 Vdd 11 12
D1
+15V 1
A6
1
MUR860
A7 4049
IC1
A8 IC2
1
2 T3 D8
A9 3 9 10 2 T1
1 & 1 VN10KM
A10
3
MUR120 J2
A11 4011 4049 T4 UE1 D10 D9
30128-528
2 1
D3
C2
A12 IC2 VN10KM
MUR860
u68
2
3
14 15 1 MUR120 1N5346 IRFP460
R3
A13 1
150R
GND GND
A14 3
4049
R2
C5
A15
2k2
22nF
2
R5
A16
150R
A17 IC2
A18 7 6 30128-539
1
CIRCUIT DIAGRAMS
A19
QC Power Stage
IC4 4049
A20 IC1
2 IC2
A21 3 8
1
T7
+
C1
C3
1 & 10 5 4 2
1uF
1uF
A22 9 & 1 VN10KM
3
C8
A23 4081
3u3
4011 4049 T8
A24 IC2 2 MP1
VN10KM
A25
3
3 2
1 J3
A26 GND GND GND
A27 1
4049
A28 2
A29
A30 IC3 Vdd
+15V
A31 3 2 MP2
D2
1
1
A32
MUR860
4049
IC1
IC3
1
12 T10 D7
11 5 4 2 T2
13 & 1 VN10KM
3
MUR120
4011 4049 T9 UE2 D5 D6
2
D4
IC3 VN10KM
MUR860
3
7 6 1 MUR120 1N5346 IRFP460
R4
1
150R
GND GND
3
4049
R1
C4
2k2
22nF
2
R6
150R
IC3
9 10 30128-539
1
1
ICC 200, 300, 350
IC4 4049
IC1 IC3
5
4 6
1
T6
+
6 & 4 11
1 12 2
5 & VN10KM
3
C9
4081
3u3
4011 4049 T5
IC3 2
VN10KM
3
14 15
9
6
8
4
2
3
7
5
1
Vdd GND GND GND
+15V 4049
RN1
8*10k
1
Vdd
GND 1 +15V
R7
100k
D11
BC557
2 T11 1N4148
11V Diese Zeichnung ist urheber-
B Datum Name Gert/UNIT
C11
rechtlich gesch tzt, daher
68nF
3 D12 Weitergabe und Vervielfltigung
Gezeich. 11-12-95 M. Hagg ohne unsere Genehmigung ICC
R8 GND
unzulssig
IC4 IC4 Gepr ft Benennung/Title
8 12 100k
+
10 11
9 & 13 & LP un.: 40128-127 QC Power Stage
R9
C10
1k
1uF
4081 4081 LP bs.: 30128-528
GND GND GND GND Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 1 von 1 30128-528
189 / 266
ICC 200, 300, 350
QC Power Stage (bare)
40128-127
U-NT-STE
5
MP4
UE2 REL1
3 7 C1
$rpname $plname D3 UE1 L1
2 U-HF-AE $plname
d50b10skk
$plname $rpname $plname c225_6
9 MUR860 5
1n5
+
1 158uH
+
10 REL1 4
QKE1 1 2
C4
R4
MP3
C14
C7
C5
C17 3 3
ec150r
22uF
$plname
47k
C2
$plname
ec130r
10uF
c380
68nF
c225_11
10nF
L2
c100
150pF
4 12 2
2 $plname c430 $plname
C6
1
c225_11
0.47uF
52uH 9n5
+
+
1 $plname
U-HF-NE
GND
J2
J4 GND
30128-044
C10
R6
C11
ec150r
22uF
$plname
47k
ec130r
10uF
QKE2 D4 R5
d50b10skk r200
MUR860 0R47
GND GND-STE
30128-492
30128-478
C12
c100
150pF
T1 T2
T2_TSI
$plname $plname
UE3
R1
2 IC1 7
R11
$plname
R13
R14
R15
7667
$plname
2k
Power Module
r150
1k
r150
1k
r150
1k
$rpname
3R3
+15V
R19
$plname
$plname
3R3
CIRCUIT DIAGRAMS
30121-073 GND
R12
D2
R7
4 IC1 5
r150
330R
BA159
$plname
470k
$plname
J14
7667 $plname Vdd
R9
1
m3schraub
$rpname
$plname
10k
1.0 +15V
J1 T3
Power Module (UL)
+
A1
$plname
C28
A2 R10
C8
C9
22nF
c150
3u3
68nF
$plname
$plname
A3 GND $plname
C16
C13
R8
10k BUZ74
u68
1nF
$plname
200k
c150
$plname
A4
+
A5 Vdd GND
C18
A6 +15V
1uF
$plname
GND GND GND GND GND
R3
R16
A7
$plname
51k
$plname
1k
A8
A9 GND
A10
A11
A12
NTE
TSI
A13
U-INP
U-INT
U-PRIM
A14
$plname
$rpname
U-NETZT
A15 TEMP
D5
REL1
A16
1N4148
$plname
A17
A18 NTE
Vdd MP2 2.0
A19 NTC1
+15V R2 1206
J3
A20 Vdd
+15V 0.8 $plname 1
A21 U-NT-STE
ICC 200, 300, 350
+
A25 U-PRIM GND-STE $plname
D1
A26
C15
3u3
$plname
$plname
A27 U-INP 9V1
A28 U-INT GND GND
A29 U-NETZT
A30
A31
A32
Diese Zeichnung ist urheber-
19-11-97 D Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC
Gezeich. 31-05-95 M.Fritz ohne unsere Genehmigung
unzulssig
Gepr ft 40128-117
31-05-95 M. Hagg Benennung/Title Power-Module
2 IC2 7
7667 $plname
$rpname
R17 R18
4 IC2 5 T2_TSI
TSI $plname $plname
7667 $plname
$wert $rpname
$wert
191 / 266
ICC 200, 300, 350
Power Module (bare)
Power Module UL (bare)
40128-117
MP3 MP1
5
GND
IC1
10 9
SG CLK Q1
7
TSI-STE Q4
5
Q5
4
Q6
6
Q7
13
Q8
Q9 12 F-ST REL3 REL3
3
AE
30128-555
14
Q10 2
Q11 15 REL19
C1 R1 1
1 UE1
Q12 J4
J1 2 1
Q13 4k7
11 3 J3 1nF
A1 AUS R Q14 R2
GND
C4
C3
D1
A2 1 2
u33
150pF
4020
MUR860
A3 REL19 4k7
C2
CIRCUIT DIAGRAMS
ST Power Stage
C6
D2 4
68nF
A9 Vdd REL1 REL1 J6
D0 GND D3 5 1
A10 BUS 1 +15V
D1 D4 6
A11
D5 7 D4
A12 D2 2 IC4 7
D3 D6 8 7667
A13 1N4148
D7 9 T1 J7
A14 D4
SG 1
A15 D5 8x10k NE
R3 2
A16 D6 4 IC4 5
IC6 3
A17 D7 REL1 +24V 7667 11N80
1 10R
A18 RESET R
CS3 9 AUS
C5
A19 CS5 C1
RESET Vdd
6n8
A20 CS5 +15V
BUS D0 3 2 GND GND
A21 1D IC7 REL2
D1 4 5 3 14
+
A22 F-ST D2 14 15 4 ULN2004A 13
C9
C10
A23
68nF
3u3
D3 13 12 1 16
A24
D4 11 10 2 15 GND GND
A25 REL3
D5 6 7 5 12
A26 TSI-STE 6 11
A27 40174
7 10
ICC 200, 300, 350
A28
A29 REL19
8 9
A30
RN1
A31 2 GND
CS3
A32 4
CS5
3 Vdd
RESET
5 +15V
1
6
7
8
9 Diese Zeichnung ist urheber-
B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
8x4k7 Weitergabe und Vervielfltigung
Gezeich. 15-03-96 M.Fritz ohne unsere Genehmigung
ICC
unzulssig
0.8 0.6
Gepr ft Benennung/Title
Vdd
+15V
Nr. nderung Datum Name Blatt 1 von 1 30128-555
193 / 266
ICC 200, 300, 350
ST Power Stage (bare)
40128-129
R36
5
D26
7k5
1N4148
Vdd
+15V C28
GND
68nF
7
R21 R47
2 1 13
-+ 8 -
7k5 2k IC7 D27 R48 IC8
OFF 6 14 IP_PAT
BIPOLAR MONO AD844 TZ TL084
1N4148 1k
NE AE AE 3 +
- 5
12 + R50
C30
R49
4
C27
D31
D32
1nF
R61
C29
1M
10k
220pF
4k7
1N4148
NE_NESSY
J5
J3
30128-561
GND GND GND GND GND GND GND GND
5
4
3
2
1
1
2
3
Vee 3 +
68nF
-15V TL084 IP_PAT_A
1
IC8
Senso-board
-
2
R62 R63
REL1
REL3
REL2
GND 750R 6k8
TEILER
Vdd
CIRCUIT DIAGRAMS
+15V
R52
REL1
REL3
REL2
D10
7k5
NE 1N4148
Vdd
+15V C14
J9
J7
R25
GND
R23
D22
2k
D33
15V
1:50 R20
560R
J8 68nF
1N4148
5 7
AE - 3
J10 18k IC3 2 1 6
12 -+ 8 -
1 2 LM319 GND IC4 D23 R54 IC8
T3 OFF 6 7 UP_HF
R11
4 2 TZ
R12
D16
D17
R74
+ AD844 TL084
1k
BS170
1k
3M3
3 1N4148 1k
1N4148
UE1 1 3 + 5 + R51
- 5
C33
R53
R64
Vee 4
R67
R38
R24
D28
D29
1nF
C15
1M
4k7
10k
10k
470R
2k
GND GND GND GND -15V GND GND
1N4148
GND GND GND GND GND GND GND GND GND
R17 Vee 10 +
Vee 68nF
-15V -15V TL084 UP_HF_A
8
7k5 Vdd IC8
-
+15V 9
R37 R39
C1 UE2
R14
GND 750R 6k8
10k
150pF 10
- 3 +
1 2 IC3 D20 D21
R15
7 TL084 U_PHASE
2k
LM319 GND 1
R22 1N4148 1N4148 IC9
9 + -
8 2
ICC 200, 300, 350
10k R55
100:8
1k3
4k7
R13
C13
D19
D18
R16
R40
10R
u22
2k
1N4148
R65
3
2
1
3
2
1
4k7
GND GND GND GND
J2
J1
GND GND GND GND
NE AE Vdd Vdd
+15V +15V
C11 C32
FROM GENERATOR
68nF GND 68nF GND
4
11
+ +
IC3 IC8
Diese Zeichnung ist urheber-
LM319 TL084 B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
- - Weitergabe und Vervielfltigung
MP1 6 Gezeich. 12.08.96 Fritz ohne unsere Genehmigung ICC
C12 11 C31
unzulssig
Gepr ft 12.08.96 Fritz Benennung/Title
GND GND
68nF 68nF LP un.: 40128-130 SENSO-BOARD
Vee Vee
GND -15V -15V B 4343 C39 neu hinzu 12-1-98 Fritz LP bs.: 30128-561
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 1 von 3 30128-561
195 / 266
R10 6
-
1k IC9 7 U_FUNKE
2 UE5 D15 R32 TL084
I+9
- 5 +
196 / 266
IC2 1 1
1 1N4148 0R
R1 R2 R6 R7 TL082 14
AE
3 +
2 T1 3
IC1
C4
VN10KM
C22
750k 750k 10k 10k
220pF
R33
10nF
R58
5 3 2
22k
4k7
I+9 AST
4
D2
15V
AST 1
6 8:8:8 GND GND GND GND
C5
-TRIG
R8
10nF
8 10
150k
+TRIG Q T2
D1
12
G 2
15V
RTRIG VN10KM
R4 R5 9 11 3
Q
NE IMAS
2
MR
30128-561
750k 750k RX Vdd
13 +15V
OSC OUT
1
CX 4
Senso-board
R3
C8
IC9
1k
IMAS
1nF
3 TL084
RCX
-
4047 11
7
I+9
Vee
-15V
8 6
-
IMAS
IMAS
+
IC2 IC2 7
TL082 TL082
- 5 +
4
I-9
IMAS
Vdd Vdd
+15V +15V R9 D4
I+9
10R 1N4148
1N4148
C24
UE6 I-9
10nF
D6
+
1 2
1uF
C7
D3
C23
9V1
C6
R34
2n2
1uF
D5
9V1
1k
3
12:16
IMAS
ICC 200, 300, 350
+
2
T6
C26
3u3
BC547
C9
1
18pF
C25
C10
R35
D25
3V
1uF
18pF
56R
GND GND GND GND GND
5
Weitergabe und Vervielfltigung
Gezeich. 12.08.96 Fritz ohne unsere Genehmigung ICC
unzulssig
Gepr ft 12.08.96 Fritz Benennung/Title
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
J4
5
1
NE_NESSY 2 Vdd
NE +15V
3
C36
3u3
D9 10 +
+
C20 GND
UE4 UE3 TL084 U_SYM
C35
1N4148 8
IC9
3u3
1 -
2n2 9 Vee
R72
L2
R27 R56
C2
-15V
10k
100uH
u1
1 2 3
R73
L1
1k 3k
100R
3m3
2
C3
R71
u1
C38
C57
10k
R26
R57
68nF
1uF
10k
3k
30128-561
9:7 2:2:15 GND
GND GND GND GND J6
R28 A1
A2
Senso-board
Vdd GND
2k4 C18 A3
+15V
+24V A4
GND
R42
A5
C39
7 68nF
R29
12k
Vee
10nF
150R
2 1 -15V Vdd A6
-+ 8
CIRCUIT DIAGRAMS
C16 R60 D30 +15V A7
R18
R19 IC5 B/C1 C2 6
2k4
LM318 B/C3 12 + A8
1k 1N4148 Vcc
2k4 1nF 3 + TL084 U_NESSY +5V A9
- 5 14
IC9 D0 A10
C34
4
R59
-
68nF
C21 D1 A11
30k
13
C19
C17
R41
R43
1nF
220pF
D2 A12
4k7
10k
R66
4k7
GND GND GND GND
Vee GND D3 A13
-15V 68nF GND GND GND
D4 A14
D5 A15
D6 A16
D7 A17
STEUERBUS
A18
A19
A20
A21
U_FUNKE
A22
Vdd U_SYM
+15V Vdd A23
U_NESSY
+15V A24
3 U_PHASE
Vdd A25
UP_HF_A
2 +15V A26
R31
R44
UP_HF
T4 Vdd
5k6
5k6
8 A27
BC547 +15V IP_PAT_A
R30 + A28
+
1
1 7 IC6 IP_PAT
3 A29
C37
1 -
10k +24V
3u3
BC557 LM311 A30
RN1
T5 2 IC10 A31
8x10k
1 +
2
3
4
5
6
7
8
9
2 1
GND R A32
B B/S -
ICC 200, 300, 350
9
C1
D0
D1
D2
D3
D4
D5
D6
D7
3 5 6 4
D24
1N4148
Vee STEUERBUS
D13
D14
D7
D0 3 2
REL2
REL3
REL1
-15V D1 4 5
-15V OSZI_DIS
3 3 D2 6 7 3 3 3
D3 11 10 R70
T7 T8 D4 13 12 2 2 2
2 2 T11 T9 T10
BS170 BS170 D5 14 15 10k
1 1 BC547 BC547 BC547
R69 1 1 1
OSZI_DIS 40174
GND GND GND
10k
R46
R45
R68
10k
1k
GND GND GND
10k
Diese Zeichnung ist urheber-
B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung
Gezeich. 12.08.96 Fritz ohne unsere Genehmigung ICC
unzulssig
Gepr ft 12.08.96 Fritz Benennung/Title
197 / 266
ICC 200, 300, 350
Senso-board (bare)
40128-130
5
J5
2
J4
Power-Module
Mainboard 1
J3
J6
30128-479
CIRCUIT DIAGRAMS
J2
1
Upper Wiring Module
2
QK-Endstufe
J1
1
2
ICC 200, 300, 350
199 / 266
ICC 200, 300, 350
Upper Wiring Module (bare)
40128-118
5
CPU Kleinspannung+Ton Control-Board QK-Endstufe Leistungsteil ST-Endstufe
J1 Vcc J2 J3 J4 J5 J6
A1 C1
+5V A1 A1 B1 A1 A1 A1
A2 C2 A2 A2 B2 A2 A2 A2
GND GND GND GND GND GND
A3 C3 A3 A3 B3 A3 A3 A3
GND
A4 C4 A4 +24V A4 B4 A4 A4 A4
+24V +24V +24V +24V +24V
A5 C5 A5 A5 B5 A5 A5 A5
A6 C6 A6
Vee Vee A6 B6
Vee A6
Vee A6
Vee A6
Vee
CS Vdd
ANALOG-1 Vdd -15V Vdd -15V Vdd -15V Vdd -15V Vdd -15V
A7 C7 A7 +15V -15V A7 B7 A7 A7 A7
ANALOG-2 +15V +15V +15V +15V +15V
A8 C8 A8 A8 B8 A8 A8 A8
ANALOG-3 SET Vcc Vcc Vcc Vcc Vcc Vcc
A9 C9 A9 A9 B9 A9 A9 A9
30128-033
+5V +5V +5V +5V +5V +5V
ANALOG-4
A10 C10 A10 A10 B10 A10 A10 A10
ESD0 ESD0 ANALOG-1 ESD0 ESD0 ESD0
A11 C11 A11 A11 B11 A11 A11 A11
ESD1 ESD1 ANALOG-2 ESD1 ESD1 ESD1
Motherboard
CIRCUIT DIAGRAMS
EIN4 EIN15 ESD6 ESD6 ESD6 ESD6 ESD6
A17 C17 A17 A17 B17 A17 A17 A17
EIN5 EIN16 ESD7 ESD7 SICHER ESD7 ESD7 ESD7
A18 C18 A18 A18 B18 A18 A18 A18
EIN6 EIN17 CS1 RESET NT-EIN NTE CS6
A19 C19 A19 A19 B19 A19 A19 A19
EIN7 EIN18 RESET CS2 HF-EIN REL-NT RESET
A20 C20 A20 A20 B20 A20 A20 A20
EIN19 CS3 STE-EIN CS7
A21 C21 A21 A21 B21 A21 A21 A21
CS4 TEMP TEMP
A22 C22 A22 A22 B22 A22 A22 A22
CS5 TSI F-ST
A23 C23 A23 A23 B23 A23 A23 A23
EIN8 SICHER U-PRIM A A TSI
A24 C24 A24 A24 B24 A24 A24 A24
EIN9 EIN20 TSI-STE B B
A25 C25 A25 A25 B25 A25 A25 A25
EIN10 EIN21 I-HFL AN AN U-PRIM
A26 C26 A26 A26 B26 A26 A26 A26
EIN11 EIN22 RES-ANA2 AUS AUS TSI-STE
A27 C27 A27 A27 B27 A27 A27 A27
PSD7 EIN23 RES-ANA1 U-INP U-INP
A28 C28 A28 A28 B28 A28 A28 A28
PSD5 PSD6 IP-PAT U-INT U-INT
A29 C29 A29 A29 B29 A29 A29 A29
PSD3 PSD4 IP-PAT-A U-NETZT U-NETZT
A30 C30 A30 A30 B30 A30 A30 A30
PSD1 PSD2 UP-HF U-FUNKE
A31 C31 A31 A31 B31 A31 A31 A31
PSD0 UP-HF-A U-SYM
A32 C32 A32 A32 B32 A32 A32 A32
RESET U-PHASE U-NESSY
24V-TR
24V-TR
I-HFL
GND
203 / 266
Senso-Board Mono-Output-Board Vcc Vcc Vcc Vdd Vdd
+5V +5V +5V +15V +15V
1
1
J7
C24
A1 J8
68nF
204 / 266
1 2
A2
C3
C4
FING-A1
RN8
RN15
GND RELAIS
68nF
68nF
3 4
8*10k
8*10k
A3 FING-B1 GND
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
A4 5 6
+24V Vdd GND GND
A5 +24V 7 8 +15V
A6
Vee 9 10
A7
Vdd -15V RESET
+15V
A8
A9
Vcc GND
+5V IC4
A10 IC10
ESD0
A11 DMUX 11 1 16
RESET
30128-033
ESD1 0 ULN2004A
A12 9 2 15
ESD2 1 CS1 Ton J2
A13
Vcc R1 10 3 14
Motherboard
A18 3 0 4
CS8 PSD1 7
A19 21 G 18 8 9
RESET PSD2 15 8 Vdd
A20 22 17 +15V
PSD3 3 9 GND
A21 20
U-FUNKE 10
A22 23 19
1
U-SYM SET EN 11
A23 14
U-NESSY 12
A24 Vcc R2 13
RN16
U-PHASE 13
+5V
8*10k
A25 16
UP-HF-A 14
2
3
4
5
6
7
8
9
A26 10k 15 15 IC11
UP-HF 4514 1 16
A27 CS7
IP-PAT-A 2 ULN2004A 15
A28 CS8
IP-PAT 3 14
A29 CS9
A30 4 13
CS10
A31 5 12
CS11
A32 6 11
CS12
7 10
8 9
GND
GND
J9 GND
1 2
8
9
7
6
5
4
3
2
11 12
13 14
ESD0 FING-A3
15
RN9
16 FING-B3
8*10k
ESD1
17
1
18 RES-B1
ESD2
19 20
ESD3 RES-B2
21 22 Vcc
ESD4 RES-B3
23 24 +5V
ESD5 RES-B4
25 26
ESD6 RES-B5
27 28
ESD7 RES-B6
5
29 30
RESET RES-F1
31 32
CS11 RES-F2 Diese Zeichnung ist urheber-
33
B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
34 RES-F3
CS12 Weitergabe und Vervielfltigung ICC 200
35 36 Gezeich. 25-05-92 M.Fritz ohne unsere Genehmigung
RES-F4
37 unzulssig
38 RES-F5 Gepr ft Benennung/Title
RES-ANA1
39 40
RES-ANA2
LP un.: 40128-025 Motherboard 200
RN18=2k2 8-93 MF LP bs.: 30128-033
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 2 von 5 30128-033
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
5
+24V
REL1
RLV
REL1
D1
J11
1
2 REL1 1N4148
5 R3 D2
6
3k6 $wert
R5 F1
~
100R BR1 Vdd Vcc
T200mA
30128-033
+15V +24V +5V
- + Vee
-15V 0.5 0.5
BH37933 Leistungsteil
~
+
Motherboard
J20 J16
C6
R6
1 1
680uF
22k
J15
1 6
3 0.5
ICC 200
CIRCUIT DIAGRAMS
C11
C22
C9
C23
C8
C10
2
68nF
68nF
68nF
68nF
68nF
68nF
+
J14
GND GND GND GND GND GND
C7
R9
C5
680uF
22k
u68
Vdd Vcc Frontplatte
Gehuse J19
1 +15V +5V J10
TR1 1
2
~
1 J22 J18 BR2 3
1 1
Prim.1
J12
24V-TR MASSE
Sek.
- +
+
J13
~
B250C5000
Prim.2
1
C32
C33
C15
u022
u022
1000uF
24V GND
GND
GND
J21 J17
1 1
205 / 266
GND Vdd
+15V
1
1
206 / 266
RN5
RN12
8*4k7
8*10k
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
IC7
1 16
PSD0 ESD0
2 ULN2004A 15
PSD1 ESD1
3 14
PSD2 ESD2
4 13
PSD3 ESD3
5 12
PSD4 ESD4
6 11
PSD5 ESD5
30128-033
7 10
PSD6 ESD6
ESD7
PIO-Ausgnge
PSD7
Motherboard
D8 8 9
R10 Vdd Vcc
ext. Steuerbus
+15V +5V
GND
$wert 2k2
1
D3
ICC 200
RESET Vdd
RN6
1N4148 +15V
8*10k
2
8
7
6
5
4
3
9
1
IC2
1
R
RN13
9
8*10k
CS13 C1 IC8
1 16
3
4
5
6
7
8
2
9
3 2 2 ULN2004A 15
1D HF-EIN
4 5 3 14
NT-EIN
6 7 4 13
RES-F1
11 10 5 12
RES-F2
13 12 6 11
NTE
14 15 7 10
RES-F3
40174
Vcc 8 9
+5V
GND
1
D4
Vdd
RN7
1N4148 +15V
8*10k
2
8
7
6
5
4
3
9
1
IC3
1
R
RN14
Signalleitungen
8*10k
CS14 C1
2
3
4
5
6
7
8
9
IC9
3 2 1 16
1D RES-F4
4 5 2 ULN2004A 15
RES-F5
6 7 3 14
REL-NT
11 10 4 13
RELAIS
13 12 5 12
RLV
14 15 6 11
STE-EIN
5
7 10
40174 SICHER
8 9
SICHER
GND
Vcc Vcc
+5V +5V
Diese Zeichnung ist urheber-
B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC 200
Gezeich. 25-05-92 M.Fritz ohne unsere Genehmigung
unzulssig
C1
C2
Gepr ft Benennung/Title
68nF
68nF
GND GND
LP un.: 40128-025 Motherboard 200
RN18=2k2 8-93 MF LP bs.: 30128-033
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 4 von 5 30128-033
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
GND
5
Vdd Vcc
GND +15V +5V
1
1
1
1
RN10
RN3
8*10k
8*10k
FuÆschalter 1
RN18
RN17
Vdd
2k2
8*10k
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
J23 R12 +15V
5
3
7
6
8
9
4
2
2
3
5
4
6
7
8
9
1 EIN19
2 680R R15 IC13 IC5 EIN20
3 R14 3 2 14 15
680R 1 FUSS-B1 FUSS-A1 1 EIN1
C17
C16
14 15 3 2
68nF
68nF
FuÆschalter 2 1 FUSS-A1 FUSS-B1 1 EIN2
30128-033
Vdd
R11 +15V GND GND
J24 4050 4050
1
R17 IC13 IC5
Motherboard
2 680R 11 12 5 4
3 R16 1 FUSS-B2 FUSS-A2 1 EIN3
680R
4050 4050
680R
IC13 IC5
5 4 11 12
ICC 200
FUSS-A2 EIN4
CIRCUIT DIAGRAMS
C19
C18
1 FUSS-B2 1
68nF
68nF
Vdd
R13 +15V GND GND 4050 4050
J25
1 IC13 IC5
2 680R R18 7 6 7 6
FING-B3 1 FUFI-B3 RES-B5 1 EIN17
3 R19
680R FING-A3
4050 4050
680R IC13 IC5
9 10 9 10
1 FUFI-A3 RES-B6 1 EIN18
C20
C21
68nF
68nF
4050 4050
GND GND
1
1
1
1
RN2
RN1
RN11
RN4
8*10k
8*10k
8*10k
8*10k
9
7
3
5
8
6
2
4
3
4
5
7
9
2
8
6
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
EIN21
IC1 EIN22 IC6 EIN23
14 15 14 15
1 EIN7 FING-A1 1 EIN5
4050 4050
IC1 IC6
5 4 3 2
F-ST 1 EIN8 FING-B1 1 EIN6
4050 4050
IC1 IC6
11 12 5 4
1 EIN9 1 EIN13
4050 4050
IC1 IC6
7 6 11 12
RES-B1 1 EIN10 1 EIN14
4050 4050
IC1 IC6
9 10 7 6
RES-B2 1 EIN11 FUFI-B3 1 EIN15
4050 4050
IC1 IC6
3 2 9 10
RES-B3 1 EIN12 FUFI-A3 1 EIN16
4050 4050
Diese Zeichnung ist urheber-
B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC 200
Gezeich. 25-05-92 M.Fritz ohne unsere Genehmigung
unzulssig
Gepr ft Benennung/Title
207 / 266
ICC 200
Motherboard (bare)
40128-025
J1 J3
5
+24V 1 1
J5
1 2 2 2
RELAIS FING_A1
3 4 3 3
FING_B1
C11
5 6
10nF
7 8
Vdd
D8
+24V +15V REL1 REL1
REL1
1N4148
9 3
3
4
10
2
+
UE1
1
1
2
C8
RELAIS J2
3u3
R2 R1 J4
GND GND 1
Vdd D2 2
+15V 150R 56R
3
D3
R4
D6
IC1 BA159
680R
UE2 11V
1N4148
1N4148
30128-358
D1
C2
C1
10nF
10nF
C4 1 D5
SFH450 BA159
D7
+ 3
C3
R3
D4
Mono Output
GND
1nF
510R
3u3
1N4148
1N4148
2
3 3
10:10:32
D10
D9
ICC 200
SD101A
SD101A
CIRCUIT DIAGRAMS
2 T2 2 T1
BC517 BC517
R11
R10
1 1
4k7
4k7
GND GND
B
Vdd
+15V
T1
T2
C
E
IC1
Vdd
R9
+15V
5k1
SFH350
GND
Vdd
Vdd
R7
+15V IC3
4k7
+15V
Vdd 5 IC4
IC2 IC5
+15V 4 & 6 6
5 6
R8 4 S 1
AST 5 & T1 3
4 C
AST 3 1k 5
R 4011 D
6 1 7 2 FING_A1
-TRIG CX 4
8 Q 10 IC5 R
+TRIG
C9
12
G 1
100pF
4013
C7
RTRIG 3
GND 2 T2
6n8
9
MR Q 11 RX/ CX GND 2 &
2
RX 4528 IC5 4011
13
OSC OUT IC4
1 R6 8
CX 10
9 & 8
S
5k1 13
11
R5
C6
4011 C
10k
Vdd
68nF
+15V
3 9
RCX IC5 D 12
10 FING_B1
4047 12 R
11
13 & 4013
4011 GND
IC3
11
Vdd
+15V 12 & Diese Zeichnung ist urheber-
10
C Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC 200
13 Gezeich. 17-02-94 Fritz ohne unsere Genehmigung
R unzulssig
0.6 Vdd Vdd 9
15 Gepr ft 14-07-94 Hagg Benennung/Title
+15V +15V CX
0.9 LP un.: 40128-096
14 C 3252 s.Aenderungsmit. 14.7.94 Fritz Mono-Output-Board
RX/ CX
C5
C10
68nF
68nF
B 3192 C11=10nF 22.6.94 Fritz LP bs.: 30128-358 Zeichnungsnummer/DWG.NO
GND GND GND GND 4528
Nr. nderung Datum Name Blatt 1 von 1 30128-358
209 / 266
ICC 200
Mono Output (bare)
40128-096
5
CPU Kleinspannung+Ton Control-Board QK-Endstufe Leistungsteil ST-Endstufe
J1 Vcc J2 J3 J4 J5 J6
+5V
A1 C1 A1 A1 B1 A1 A1 A1
A2 C2 A2 GND GND
A2 B2 GND
A2 GND
A2 GND
A2 GND
GND
A3 C3 A3 A3 B3 A3 A3 A3
A4 C4 A4 +24V +24V A4 B4 +24V A4 +24V A4 +24V A4 +24V
A5 C5 A5 A5 B5 A5 A5 A5
Vee Vee Vee Vee Vee Vee
A6 C6 CS A6 Vdd A6 B6 A6 A6 A6
ANALOG-1 Vdd -15V Vdd -15V Vdd -15V Vdd -15V Vdd -15V
A7 C7 A7 +15V -15V A7 B7 A7 A7 A7
ANALOG-2 +15V +15V +15V +15V +15V
A8 C8 SET A8 Vcc A8 B8 A8 A8 A8
ANALOG-3 Vcc Vcc Vcc Vcc Vcc
30128-394
A9 C9 A9 +5V +5V A9 B9 +5V A9 +5V A9 +5V A9 +5V
ANALOG-4
A10 C10 A10 ESD0 A10 B10 ANALOG-1 A10 ESD0 A10 ESD0 A10 ESD0
ESD0
A11 C11 A11 ESD1 A11 B11 ANALOG-2 A11 ESD1 A11 ESD1 A11 ESD1
Motherboard
ESD1
A12 C12 A12 ESD2 A12 B12 ANALOG-3 A12 ESD2 A12 ESD2 A12 ESD2
ESD2
A13 C13 EIN12 A13 ESD3 A13 B13 ANALOG-4 A13 ESD3 A13 ESD3 A13 ESD3
EIN1 ESD3
A14 C14 EIN13 A14 ESD4 A14 B14 A14 ESD4 A14 ESD4 A14 ESD4
EIN2 ESD4
A15 C15 EIN14 A15 ESD5 A15 B15 A15 ESD5 A15 ESD5 A15 ESD5
EIN3 ESD5
ICC 300
CIRCUIT DIAGRAMS
A16 C16 EIN15 A16 ESD6 A16 B16 A16 ESD6 A16 ESD6 A16 ESD6
EIN4 ESD6
A17 C17 EIN16 A17 ESD7 A17 B17 SICHER A17 ESD7 A17 ESD7 A17 ESD7
EIN5 ESD7
A18 C18 EIN17 A18 CS1 A18 B18 NT-EIN A18 A18 NTE A18 CS6
EIN6 RESET
A19 C19 EIN18 A19 RESET A19 B19 HF-EIN A19 A19 REL-NT A19 RESET
EIN7 CS2
A20 C20 EIN19 A20 A20 B20 STE-EIN A20 A20 A20 CS7
CS3
A21 C21 A21 A21 B21 TEMP A21 A21 TEMP A21
CS4
A22 C22 A22 A22 B22 TSI A22 A22 A22 F-ST
CS5
A23 C23 SICHER A23 A23 B23 A A23 A A23 TSI A23
EIN8 U-PRIM
A24 C24 EIN20 A24 A24 B24 B A24 B A24 A24
EIN9 TSI-STE
A25 C25 EIN21 A25 A25 B25 AN A25 AN A25 U-PRIM A25
EIN10 I-HFL
A26 C26 EIN22 A26 A26 B26 AUS A26 AUS A26 A26 TSI-STE
EIN11 RES-ANA2
A27 C27 EIN23 A27 A27 B27 U-INP A27 A27 U-INP A27
PSD7 RES-ANA1
A28 C28 PSD6 A28 A28 B28 U-INT A28 A28 U-INT A28
PSD5 IP-PAT
A29 C29 PSD4 A29 A29 B29 U-NETZT A29 A29 U-NETZT A29
PSD3 IP-PAT-A
A30 C30 PSD2 A30 A30 B30 U-FUNKE A30 A30 A30
PSD1 UP-HF
A31 C31 PSD0 A31 A31 B31 U-SYM A31 A31 A31
UP-HF-A
A32 C32 A32 A32 B32 U-NESSY A32 A32 A32
RESET U-PHASE
24V-TR
24V-TR
213 / 266
Senso-Board Refi-Board Vcc Vcc Vcc Vdd Vdd
+5V +5V +5V +15V +15V
1
1
J7 J8
C24
A1 A1
68nF
214 / 266
C3
C4
A2 A2
RN8
RN15
GND GND
68nF
68nF
8*10k
8*10k
A3 A3 GND
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
A4 +24V A4 +24V GND GND
A5 A5
Vee Vee
A6 A6
Vdd -15V Vdd -15V RESET
A7 +15V A7 +15V
A8 A8
Vcc Vcc
A9 +5V A9 +5V IC4
A10 ESD0 A10 ESD0 IC10 30128-394
A11 A11 DMUX 11 1 16 RESET
ESD1 ESD1 0
A12 A12 9 2 ULN2004A 15
CS1 Ton J2
ESD2 ESD2 1
Vcc R1 10 3 14
A13 ESD3 A13 ESD3 +5V 2 CS2
Motherboard
1
A22 A22 23 19
U-SYM SET EN 11
A23 A23 14
U-NESSY FING-A1 12
A24 A24 Vcc R2 13
RN16
U-PHASE FING-B1 13
+5V
$wert
A25 A25 16
2
3
4
5
6
7
8
9
UP-HF-A FING-A2 14
A26 A26 10k 15 15 IC11
UP-HF FING-B2 4514
A27 A27 1 16 CS7
IP-PAT-A
A28 A28 2 ULN2004A 15
CS8
IP-PAT
A29 A29 3 14 CS9
A30 A30 4 13 CS10
A31 A31 5 12 CS11 J10 Res.
A32 A32 6 11 CS12 J10 Res.
7 10 CS13
8 9
GND
J28 J57
1 1 CS13
D24
AE1 Gen. 2 2 CS14
AE1 Bu.
3 BA159 3
8
9
7
6
5
4
3
2
D25
RN9
BA159
8*10k
1
J29 J58
1 1
D26 Vcc
AE2 Gen. 2 2 AE2 Bu. +5V
3 BA159 3
4
5
6
D27
UE1
1
2
3
BA159
Diese Zeichnung ist urheber-
5
A Datum Name rechtlich gesch tzt, daher
Gert/UNIT
J26 J27
Weitergabe und Vervielfltigung ICC300
1 1 Gezeich. 20-07-94 M.Fritz ohne unsere Genehmigung
2 2 unzulssig
NE Nessy NE Bu. Gepr ft 20-07-94 M.Hagg Benennung/Title
3 3
LP un.: 40128-092 Motherboard
LP bs.: 30128-394
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 2 von 5 30128-394
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
5
+24V
REL1
RLV
REL1
D1
J11
1
REL1 1N4148
2
5 R3 D2
6
3k6 rot
R5 F1
~
100R BR1 Vdd Vcc
T200mA
30128-394
+15V +24V +5V
- + Vee
-15V 0.5 0.5
BH37933 Leistungsteil
~
+
Motherboard
J20 J16
C6
R6
680uF
22k
1 1
J15
6
1
3
0.5
ICC 300
C11
C22
C9
C23
C8
C10
2
CIRCUIT DIAGRAMS
68nF
68nF
68nF
68nF
68nF
68nF
+
J14
GND GND GND GND GND GND
C7
R9
C5
680uF
22k
u68
Vdd Vcc Frontplatte
Gehuse J19
1 +15V +5V J10
TR1 1
2
~
1 J22 J18 BR2 3
Prim.1
J12 1 1
24V-TR MASSE
Sek.
- +
+
J13
~
B250C5000
Prim.2
C32
C33
1
C15
u022
u022
1000uF
24V GND
GND
GND
J21 J17
1 1
215 / 266
GND Vdd
+15V
1
1
216 / 266
RN5
RN12
8*4k7
8*10k
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
IC7
1 16 ESD0
PSD0
2 ULN2004A 15
ESD1
PSD1
3 14 ESD2
PSD2
4 13 ESD3
PSD3
5 12 ESD4
PSD4
6 11 ESD5
PSD5
7 10
30128-394
PSD6 ESD6
ESD7
PIO-Ausgnge
PSD7
Motherboard
ext. Steuerbus
+15V +5V
GND
2k2
1
rot
D3
ICC 300
RESET Vdd
RN6
1N4148 +15V
8*10k
2
8
7
6
5
4
3
9
1
IC2
1
R
RN13
9
8*10k
CS13 C1 IC8
3
4
5
6
7
8
2
9
1 16
3 2 2 ULN2004A 15
HF-EIN
1D
4 5 3 14 NT-EIN
6 7 4 13 RES-F1
11 10 5 12 RES-F2
13 12 6 11 NTE
14 15 7 10 RES-F3
40174
Vcc 8 9
+5V
GND
1
D4
Vdd
RN7
1N4148 +15V
8*10k
2
8
7
6
5
4
3
9
1
IC3
1
R
RN14
Signalleitungen
8*10k
CS14 C1
2
3
4
5
6
7
8
9
IC9
3 2 1 16 RES-F4
1D
4 5 2 ULN2004A 15
RES-F5
6 7 3 14 REL-NT
11 10 4 13 R-BF/CF
13 12 5 12 RLV
14 15 6 11 STE-EIN
7 10 SICHER
5
40174
8 9
SICHER
GND
Vcc Vcc
+5V +5V
Diese Zeichnung ist urheber-
A Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC300
Gezeich. 20-07-94 M.Fritz ohne unsere Genehmigung
unzulssig
C1
C2
Gepr ft 20-07-94 M.Hagg Benennung/Title
68nF
68nF
GND GND
LP un.: 40128-092 Motherboard
LP bs.: 30128-394 Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 4 von 5 30128-394
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
GND
5
Vdd Vcc
GND +15V +5V
1
1
1
1
RN10
RN3
8*10k
8*10k
FuÆschalter 1
RN18
RN17
Vdd
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
8*2k2
8*10k
R12 +15V
5
3
7
6
8
9
4
2
2
3
5
4
6
7
8
9
J23
1 EIN19
680R R15 IC13 IC5
2 EIN20
3 R14 3 2 FUSS-B1 14 15 EIN1
680R 1 FUSS-A1 1
680R 4050 4050
IC13 IC5
C17
C16
14 15 3 2
68nF
68nF
FuÆschalter 2 1 FUSS-A1 FUSS-B1 1 EIN2
Vdd
GND GND
30128-394
J24 R11 +15V 4050
4050
1 IC13 IC5
680R R17
2 11 12 5 4
1 FUSS-B2 FUSS-A2 1 EIN3
Motherboard
3 R16
680R
4050 4050
680R
IC13 IC5
5 4 FUSS-A2 11 12 EIN4
C19
C18
1 FUSS-B2 1
68nF
68nF
Vdd
ICC 300
CIRCUIT DIAGRAMS
R13 +15V GND GND 4050 4050
J25
1 IC13 IC5
680R R18 7 6 7 6
2 FING-B3 1 FUFI-B3 RES-B5 1 EIN17
3 R19
680R FING-A3
4050 4050
680R IC13 IC5
9 10 FUFI-A3 9 10 EIN18
1 RES-B6 1
C20
C21
68nF
68nF
4050 4050
GND GND
1
1
1
1
RN2
RN1
RN11
RN4
8*10k
8*10k
8*10k
8*10k
9
7
3
5
8
6
2
4
3
4
5
7
9
2
8
6
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
EIN21
IC1 EIN22 IC6 EIN23
14 15 EIN7 14 15 EIN5
1 FING-A1 1
4050 4050
IC1 IC6
5 4 EIN8 3 2 EIN6
F-ST 1 FING-B1 1
4050 4050
IC1 IC6
BF/CF 11 12 EIN9 5 4 EIN13
BF/CF 1 FING-A2 1
4050 4050
IC1 IC6
R20
7 6 11 12
0R
RES-B1 1 EIN10 FING-B2 1 EIN14
4050 4050
IC1 IC6
GND 9 10 EIN11 7 6 EIN15
RES-B2 1 FUFI-B3 1
4050 4050
IC1 IC6
3 2 EIN12 9 10 EIN16
RES-B3 1 FUFI-A3 1
4050 4050
Diese Zeichnung ist urheber-
A Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC300
Gezeich. 20-07-94 M.Fritz ohne unsere Genehmigung
unzulssig
Gepr ft 20-07-94 M.Hagg Benennung/Title
217 / 266
ICC 300
Motherboard (bare)
40128-092
5
R2 R1 J3
1
Vdd 2
REL1 REL1 +15V 150R 56R
3
D1
R8
D4
IC1
680R
UE1 11V
1N4148
1N4148
3
C3
C1
10nF
10nF
2
C9 1 D5
SFH450
D3
D7
1 + 3
R7
R3
C4
D2
D6
J2 GND
510R
0R
1nF
n.best
REL2 REL2 3u3
1N4148
1N4148
n.best
2
3 3
10:10:32
D17
D18
SD101A
SD101A
2 T1 2 T2
BC517 BC517
30128-352
+24V +24V
R13
R17
1 1
4k7
4k7
Relay Board
GND GND
D15
D16
REL1
REL2
R6 R5 J4
1N4148
1N4148
1
Vdd
3
3
IC8 2
T1
T2
+15V 150R 56R
1
R R14 2 2
3
ICC 300
CIRCUIT DIAGRAMS
R10
D10
D12
9 T3 T4 IC2
680R
C1 UE2 11V
1N4148
1N4148
10k BC547 BC547
C2
C6
1
1
D0 11 10
10nF
10nF
1D R15 C8 1 D14
D1 6 7 GND GND SFH450
D8
+ 3
R9
R4
D9
C5
D11
D13
D2 13 12 10k
510R
0R
n.best
1nF
3u3
1N4148
1N4148
n.best
D3 4 5 GND 2
D4 3 2
D5 14 15 10:10:32
3 3
B
B
Vdd Vdd
D19
D20
40174
STEUERBUS
+15V +15V
SD101A
SD101A
2 T5 2 T6
STEUERBUS 2
RN1
D0
BC517 BC517
C
E
C
E
D1 3
Vdd
4
R16
R18
D2 +15V 1 1
IC1
IC2
4k7
4k7
D3 5
GND GND
R20
R23
MP1 1
5k1
SFH350
SFH350
5k1
D4 6
J1 D5 7 GND GND
A1 8
D6
T1
T2
A2 9
R19
R25
D7
4k7
n.best.
A3 GND
8x10k Vdd
A4 +24V +15V Vdd
IC5 +15V
A5
Vdd 11 IC3 IC7
A6 IC4
Vdd Vee +15V IC6 12
A7 +15V -15V 5
& R21 8
10
6
S 1
6
S 1
10 T1
AST 9 & 3 3
A8 Vcc 4 C C
AST 13 1k 5 5
A9 +5V R 4011 D D
6 15 9 2 2
-TRIG CX 4 4
A10 D0 STEUERBUS 8 10 R R
+TRIG Q IC4
C11
A11 D1 12
G 13
100pF
4013 4013
C7
RTRIG 11
A12 GND 14 T2
6n8
D2 9 11 RX/ CX GND 12 &
MR Q
A13 D3 2
RX 4528 IC4 4011
A14 13
FING_A1
FING_A2
D4 OSC OUT
1 R22 5 IC3 IC7
A15 D5 CX 4
A16 D6
6 & 8
S 8
S
5k1 13 13
11 11
R24
A17
C13
D7 4011 C C
10k
Vdd
+15V
68nF
A18
3 9 9
RCX IC4 D 12 D 12
A19
10 10
2 R R
4047 3
A20 1 & 4013 4013
A21
4011 GND GND
A22
IC5
FING_B1
FING_B2
A23
FING_A1 5
A24
FING_B1 4 &
A25 Diese Zeichnung ist urheber-
FING_A2 6 B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
A26 Weitergabe und Vervielfltigung
FING_B2 3
R Gezeich. 10-02-94 M.Fritz ohne unsere Genehmigung ICC
A27 Vdd Vdd Vdd 1 7 unzulssig
A28 +15V +15V +15V CX Gepr ft 14-07-94 M.Hagg Benennung/Title
A29 Vdd
+
+15V +24V 0.8 LP un.: 40128-093
A30 2
RX/ CX
RELAIS-BOARD
C14
C10
C12
A31
3u3
68nF
68nF
4528 B 3251 s.Anderungsmit. 14-7-94 Fritz LP bs.: 30128-352
A32 0.6 0.6 GND GND GND GND GND Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 1 von 1 30128-352
219 / 266
ICC 300
Relay Board (bare)
40128-093
5
CPU Kleinspannung+Ton Control-Board QK-Endstufe Leistungsteil ST-Endstufe
J1 Vcc J2 J3 J4 J5 J6
+5V
A1 C1 A1 A1 B1 A1 A1 A1
A2 C2 A2 GND GND
A2 B2 GND
A2 GND
A2 GND
A2 GND
GND
A3 C3 A3 A3 B3 A3 A3 A3
A4 C4 A4 +24V +24V A4 B4 +24V A4 +24V A4 +24V A4 +24V
A5 C5 A5 A5 B5 A5 A5 A5
Vee Vee Vee Vee Vee Vee
A6 C6 CS A6 Vdd A6 B6 A6 A6 A6
ANALOG-1 Vdd -15V Vdd -15V Vdd -15V Vdd -15V Vdd -15V
A7 C7 A7 +15V -15V A7 B7 A7 A7 A7
ANALOG-2 +15V +15V +15V +15V +15V
A8 C8 SET A8 Vcc A8 B8 A8 A8 A8
ANALOG-3 Vcc Vcc Vcc Vcc Vcc
A9 C9 A9 +5V A9 B9 A9 A9 A9
30128-351
ANALOG-4 +5V +5V +5V +5V +5V
A10 C10 A10 ESD0 A10 B10 ANALOG-1 A10 ESD0 A10 ESD0 A10 ESD0
ESD0
A11 C11 A11 ESD1 A11 B11 ANALOG-2 A11 ESD1 A11 ESD1 A11 ESD1
ESD1
Motherboard
A12 C12 A12 ESD2 A12 B12 ANALOG-3 A12 ESD2 A12 ESD2 A12 ESD2
ESD2
A13 C13 EIN12 A13 ESD3 A13 B13 ANALOG-4 A13 ESD3 A13 ESD3 A13 ESD3
EIN1 ESD3
A14 C14 EIN13 A14 ESD4 A14 B14 A14 ESD4 A14 ESD4 A14 ESD4
EIN2 ESD4
A15 C15 EIN14 A15 ESD5 A15 B15 A15 ESD5 A15 ESD5 A15 ESD5
EIN3 ESD5
A16 C16 A16 A16 B16 A16 A16 A16
ICC 350
CIRCUIT DIAGRAMS
A17 C17 EIN16 A17 ESD7 A17 B17 SICHER A17 ESD7 A17 ESD7 A17 ESD7
EIN5 ESD7
A18 C18 EIN17 A18 CS1 A18 B18 NT-EIN A18 A18 NTE A18 CS6
EIN6 RESET
A19 C19 EIN18 A19 RESET A19 B19 HF-EIN A19 A19 REL-NT A19 RESET
EIN7 CS2
A20 C20 EIN19 A20 A20 B20 STE-EIN A20 A20 A20 CS7
CS3
A21 C21 A21 A21 B21 TEMP A21 A21 TEMP A21
CS4
A22 C22 A22 A22 B22 TSI A22 A22 A22 F-ST
CS5
A23 C23 SICHER A23 A23 B23 A A23 A A23 TSI A23
EIN8 U-PRIM
A24 C24 EIN20 A24 A24 B24 B A24 B A24 A24
EIN9 TSI-STE
A25 C25 EIN21 A25 A25 B25 AN A25 AN A25 U-PRIM A25
EIN10 I-HFL
A26 C26 EIN22 A26 A26 B26 AUS A26 AUS A26 A26 TSI-STE
EIN11 RES-ANA2
A27 C27 EIN23 A27 A27 B27 U-INP A27 A27 U-INP A27
PSD7 RES-ANA1
A28 C28 PSD6 A28 A28 B28 U-INT A28 A28 U-INT A28
PSD5 IP-PAT
A29 C29 PSD4 A29 A29 B29 U-NETZT A29 A29 U-NETZT A29
PSD3 IP-PAT-A
A30 C30 PSD2 A30 A30 B30 U-FUNKE A30 A30 A30
PSD1 UP-HF
A31 C31 PSD0 A31 A31 B31 U-SYM A31 A31 A31
UP-HF-A
A32 C32 A32 A32 B32 U-NESSY A32 A32 A32
RESET U-PHASE
24V-TR
24V-TR
223 / 266
Senso-Board Refi-Board Vcc Vcc Vcc Vdd Vdd
+5V +5V +5V +15V +15V
1
1
J7 J8
C24
A1 A1
68nF
224 / 266
C3
C4
A2 A2
RN8
RN15
GND GND
68nF
68nF
8*10k
8*10k
A3 A3 GND
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
A4 +24V A4 +24V GND GND
A5 A5
Vee Vee
A6 A6
Vdd -15V Vdd -15V RESET
A7 +15V A7 +15V
A8 A8
Vcc Vcc
A9 +5V A9 +5V IC4
A10 A10 IC10
ESD0 ESD0
DMUX 11 1 16
30128-351
A11 ESD1 A11 ESD1 0 RESET
A12 A12 9 2 ULN2004A 15
CS1 Ton J2
ESD2 ESD2 1
Vcc
Motherboard
1
A22 A22 23 19
U-SYM SET EN 11
A23 A23 14
U-NESSY FING-A1 12
A24 A24 Vcc R2 13
RN16
U-PHASE FING-B1 13
+5V
$wert
A25 A25 16
2
3
4
5
6
7
8
9
UP-HF-A FING-A2 14
A26 A26 10k 15 15 IC11
UP-HF FING-B2 4514
A27 A27 1 16 CS7
IP-PAT-A
A28 A28 2 ULN2004A 15
CS8
IP-PAT
A29 A29 3 14 CS9
A30 A30 4 13 CS10
A31 A31 5 12 CS11 J10 Res.
A32 A32 6 11 CS12 J10 Res.
7 10 CS13
8 9
GND
GND
J9 GND
1 2
Vcc Vdd -15V 3 4 -15V Vdd Vcc
+5V +15V Vee +24V 5 6 +24V Vee +15V +5V
CS13
7 8 CS14
9 10
8
9
7
6
5
4
3
2
11 12
13 14 FING-A3
ESD0
RN9
15 16 FING-B3
8*10k
ESD1
17 18
1
ESD2 RES-B1
19 20 RES-B2
ESD3
21 22 RES-B3 Vcc
ESD4
23 24 +5V
ESD5 RES-B4
25 26 RES-B5
ESD6
5
27 28 RES-B6
ESD7
29 30 RES-F1
RESET
31 32 RES-F2 Diese Zeichnung ist urheber-
CS11 A Datum Name Gert/UNIT
33 34 rechtlich gesch tzt, daher
CS12 RES-F3 Weitergabe und Vervielfltigung
35 36 RES-F4
Gezeich. 27.01.94 M.Fritz ohne unsere Genehmigung
ICC
CS13 unzulssig
37 38 Gepr ft 20-07-94 M.Hagg Benennung/Title
RES-ANA1
39 40 RES-F6
RES-ANA2
LP un.: 40128-092 Motherboard
nicht bestueckt LP bs.: 30128-351
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 2 von 6 30128-351
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
5
+24V
REL1
RLV
REL1
D1
J11
1
REL1 1N4148
2
5 R3 D2
6
3k6 rot
R5 F1
~
100R BR1 Vdd Vcc
T200mA
30128-351
+15V +24V +5V
- + Vee
-15V 0.5 0.5
BH37933 Leistungsteil
~
+
Motherboard
J20 J16
C6
R6
680uF
22k
1 1
J15
6
1
3
0.5
ICC 350
CIRCUIT DIAGRAMS
C11
C22
C9
C23
C8
C10
2
68nF
68nF
68nF
68nF
68nF
68nF
+
J14
GND GND GND GND GND GND
C7
R9
C5
680uF
22k
u68
Vdd Vcc Frontplatte
Gehuse J19
1 +15V +5V J10
TR1 1
2
~
1 J22 J18 BR2 3
Prim.1
J12 1 1
24V-TR MASSE
Sek.
- +
+
J13
~
B250C5000
Prim.2
C32
C33
1
C15
u022
u022
1000uF
24V GND
GND
GND
J21 J17
1 1
225 / 266
GND Vdd
+15V
1
1
226 / 266
RN5
RN12
8*4k7
8*10k
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
IC7
1 16 ESD0
PSD0
2 ULN2004A 15
ESD1
PSD1
3 14 ESD2
PSD2
4 13 ESD3
PSD3
5 12 ESD4
PSD4 30128-351
6 11 ESD5
PSD5
7 10 ESD6
PSD6
ESD7
PIO-Ausgnge
Motherboard
PSD7
D8 R10 Vdd Vcc 8 9
ext. Steuerbus
+15V +5V
GND
2k2
1
rot
D3
ICC 350
RESET Vdd
RN6
1N4148 +15V
8*10k
2
8
7
6
5
4
3
9
1
IC2
1
R
RN13
9
8*10k
CS13 C1 IC8
3
4
5
6
7
8
2
9
1 16
3 2 2 ULN2004A 15
HF-EIN
1D
4 5 3 14 NT-EIN
6 7 4 13 RES-F1
11 10 5 12 RES-F2
13 12 6 11 NTE
14 15 7 10 RES-F3
40174
Vcc 8 9
+5V
GND
1
D4
Vdd
RN7
1N4148 +15V
8*10k
2
8
7
6
5
4
3
9
1
IC3
1
R
RN14
Signalleitungen
8*10k
CS14 C1
2
3
4
5
6
7
8
9
IC9
3 2 1 16 RES-F4
1D
4 5 2 ULN2004A 15
RES-F5
6 7 3 14 REL-NT
11 10 4 13 R-BF/CF
13 12 5 12 RLV
14 15 6 11
5
STE-EIN
7 10 SICHER
40174
8 9
SICHER
GND
Vcc Vcc
+5V +5V
Diese Zeichnung ist urheber-
A Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC
Gezeich. 27.01.94 M.Fritz ohne unsere Genehmigung
unzulssig
C1
C2
Gepr ft 20-07-94 M.Hagg Benennung/Title
68nF
68nF
GND GND
LP un.: 40128-092 Motherboard
LP bs.: 30128-351
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 4 von 6 30128-351
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
GND
5
Vdd Vcc
GND +15V +5V
1
1
1
1
RN10
RN3
8*10k
8*10k
FuÆschalter 1
RN18
RN17
Vdd
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
8*2k2
8*10k
R12 +15V
5
3
7
6
8
9
4
2
2
3
5
4
6
7
8
9
J23
1 EIN19
680R R15 IC13 IC5
2 EIN20
3 R14 3 2 FUSS-B1 14 15 EIN1
680R 1 FUSS-A1 1
680R 4050 4050
IC13 IC5
C17
C16
14 15 3 2
68nF
68nF
FuÆschalter 2 1 FUSS-A1 FUSS-B1 1 EIN2
Vdd
30128-351
R11 +15V GND GND
J24 4050 4050
1 IC13 IC5
680R R17
2
Motherboard
11 12 FUSS-B2 5 4 EIN3
R16 1 FUSS-A2 1
3 680R
4050 4050
680R
IC13 IC5
5 4 FUSS-A2 11 12 EIN4
C19
C18
1 FUSS-B2 1
ICC 350
CIRCUIT DIAGRAMS
68nF
68nF
Vdd
R13 +15V GND GND 4050 4050
J25
1 IC13 IC5
680R R18 7 6 7 6
2 FING-B3 1 FUFI-B3 RES-B5 1 EIN17
3 R19
680R FING-A3
4050 4050
680R IC13 IC5
9 10 FUFI-A3 9 10 EIN18
1 RES-B6 1
C20
C21
68nF
68nF
4050 4050
GND GND
1
1
1
1
RN2
RN1
RN11
RN4
8*10k
8*10k
8*10k
8*10k
9
7
3
5
8
6
2
4
3
4
5
7
9
2
8
6
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
EIN21
IC1 EIN22 IC6 EIN23
14 15 EIN7 14 15 EIN5
1 FING-A1 1
4050 4050
IC1 IC6
5 4 EIN8 3 2 EIN6
F-ST 1 FING-B1 1
4050 4050
IC1 IC6
11 12 EIN9 5 4 EIN13
BF/CF 1 FING-A2 1
4050 4050
IC1 IC6
7 6 EIN10 11 12 EIN14
RES-B1 1 FING-B2 1
4050 4050
IC1 IC6
9 10 EIN11 7 6 EIN15
RES-B2 1 FUFI-B3 1
4050 4050
IC1 IC6
3 2 EIN12 9 10 EIN16
RES-B3 1 FUFI-A3 1
4050 4050
Diese Zeichnung ist urheber-
A Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC
Gezeich. 27.01.94 M.Fritz ohne unsere Genehmigung
unzulssig
Gepr ft 20-07-94 M.Hagg Benennung/Title
228 / 266
J28 J57
1 1
D24
228
AE1 Gen. 2 2
AE1 Bu.
3 BA159 3
/ 266
D25
BA159
J29 J58
1 1
D26
AE2 Gen. 2 2 AE2 Bu.
3 BA159 3
4
5
6
D27
30128-351
UE1
1
2
3
BA159
Motherboard
+24V
J26 J27
1 1 REL2
NE Nessy 2 2
ICC 350
NE Bu. R-BF/CF
3 3
D12
Vdd Vdd
C31
C30
u022
u022
+15V +15V 1N4148
R74 D23
3k6 rot
C26
REL2
68nF
GND
D22
R22
10k
2 RES-F5
7
-
2 1N4148
1
IC12 1 -+
5
I-HFL R23 D9
REL2
D5 R7 TL082 IC14 OFF 6 BF/CF
3 +
R24 LF356
2k2 1N4148
1N4148 10k 3 +
-
68R
D6
10V
R25
D10
D11
C28
R21
L1
1k2
BA159
BA159
u15
TP1
R4
C13
R8
1k/1W
C29
10nF
100k
R20
C25
D7
u15
3M3
330k
1uF
10V
220R
GND
C27
GND
68nF
GND GND GND
Vee GND
-15V
Vdd
+15V
5
8
C12
6
68nF
+ -
IC12 IC12 7
TL082 TL082
GND - 5 +
4
C14
68nF
GND
Vee
-15V
Diese Zeichnung ist urheber-
A Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC
Gezeich. 27.01.94 M.Fritz ohne unsere Genehmigung
unzulssig
Gepr ft 20-07-94 M.Hagg Benennung/Title
CIRCUIT DIAGRAMS
ICC 350
Motherboard (bare)
40128-092
Art. No. 80116-201
09 / 2004
D1
D4
R8
IC1
680R
UE1 11V
1N4148
1N4148
230 / 266
3
C3
C1
10nF
10nF
2
C9 1 D5
SFH450
D3
D7
1 + 3
C4
D2
D6
R7
R3
J2 GND
1nF
n.best
510R
0R
REL2 REL2 3u3
1N4148
1N4148
n.best
2
3 3
10:10:32
D17
D18
SD101A
SD101A
2 T1 2 T2
BC517 BC517 30128-352
+24V +24V
R13
R17
1 1
4k7
4k7
GND GND
Relay Board
D15
D16
REL1
REL2
R6 R5 J4
1N4148
1N4148
1
Vdd
3
3
IC8 2
T1
T2
+15V 150R 56R
1 R14 2 2 3
R
ICC 350
D10
D12
R10
9 T3 T4 IC2
680R
C1 UE2 11V
1N4148
1N4148
10k BC547 BC547
C2
C6
1
1
D0 11 10
10nF
10nF
1D R15 C8 1 D14
D1 6 7 GND GND SFH450
D8
+ 3
C5
D11
D13
R4
D9
R9
D2 13 12 10k
1nF
0R
n.best
510R
3u3
1N4148
1N4148
n.best
D3 4 5 GND 2
D4 3 2
D5 14 15 10:10:32
3 3
B
B
Vdd Vdd
D19
D20
40174
STEUERBUS
+15V +15V
SD101A
SD101A
2 T5 2 T6
STEUERBUS 2
RN1
D0
BC517 BC517
C
E
C
E
D1 3
Vdd
4
R16
R18
D2 +15V 1 1
IC1
IC2
4k7
4k7
D3 5 GND GND
R20
R23
MP1 1
SFH350
SFH350
5k1
5k1
D4 6
J1 D5 7
GND GND
A1 8
D6
T1
T2
A2 9
R19
R25
D7
4k7
n.best.
A3 GND
8x10k Vdd
A4 +24V +15V Vdd
IC5 +15V
A5
Vdd 11 IC3 IC7
A6 IC4
Vdd Vee +15V IC6 12
A7 +15V -15V 5
& R21 8
10
6
S 1
6
S 1
10 T1
AST 9 & 3 3
A8 Vcc 4 C C
AST 13 1k 5 5
A9 +5V R 4011 D D
6 15 9 2 2
-TRIG CX 4 4
A10 D0 STEUERBUS 8 10 R R
+TRIG Q IC4
C11
A11 D1 12
G 13
100pF
4013 4013
C7
RTRIG 11
A12 GND 14 T2
6n8
D2 9 11 RX/ CX GND 12 &
MR Q
A13 D3 2
RX 4528 IC4 4011
A14 13
FING_A1
FING_A2
D4 OSC OUT
1 R22 5 IC3 IC7
A15 D5 CX 4
A16 D6
6 & 8
S 8
S
5k1 13 13
11 11
R24
A17
C13
D7 4011 C C
Vdd
10k
68nF
+15V
A18
3 9 9
RCX IC4 D 12 D 12
A19
10 10
4047 2 R R
A20
3
1 & 4013 4013
5
A21
4011 GND GND
A22
IC5
FING_B1
FING_B2
A23
FING_A1 5
A24
FING_B1 4 &
A25 Diese Zeichnung ist urheber-
FING_A2 6 B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
A26 Weitergabe und Vervielfltigung
FING_B2 3 Gezeich. 10-02-94 M.Fritz ohne unsere Genehmigung ICC
A27 R
Vdd Vdd Vdd 1 7 unzulssig
A28 +15V +15V +15V CX Gepr ft 14-07-94 M.Hagg Benennung/Title
A29 Vdd
+
+15V +24V 0.8 LP un.: 40128-093
A30 2
RX/ CX
RELAIS-BOARD
C14
C10
C12
A31
3u3
68nF
68nF
4528 B 3251 s.Anderungsmit. 14-7-94 Fritz LP bs.: 30128-352
A32 0.6 0.6 GND GND GND GND GND Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 1 von 1 30128-352
CIRCUIT DIAGRAMS
ICC 350
Relay Board (bare)
40128-093
Art. No. 80116-201
09 / 2004
~
J1 BR1
F1 REL1 REL1 2
T3
BUX84
A1 3
- + 2 3
232 / 266
A2 GND B250C800 62mA
~
A3 AE
NEG15
R38
R1
C8
A4
R39
+24V J2-2
820k
10uF
1k5
A5 R9
3
Vee 6 8k2
2
-
2
A6 D1 R5
Vdd -15V 10k NEG15 IC3 7 2
TY1
A7
R22
+15V R19 TL082 1
D2
R6
220k
1
1
3
A8 1N4148 470R
9V1
27k
FTEST T2
R4
Vcc T1 5 +
220R
A9 +5V 1k BUX84 BUX84 MP4
X0303
3
2
3
A10 NULL
ESD0 T5 NE
R2
R8
R3
R15
A11 ESD1 BC557
30128-070
10k
27k
1k
10k
REL2 REL2 J5
1
A12 ESD2 NULL 1
A13 ESD3 R14
R13 2
A14 ESD4 FRES
3
A15 ESD5 10k 10k
POS15
R12
A16
D13
ESD6
390R
R21 9V1 R23
BA159
A17 2 8
ESD7 CLR - IC4
2
5 + MP1
A18 CS12 1k5 D7 10k IC3 +
Neurotest Board
D6
IC6 3 RT
1
C13
A20 - U U-STEUER
CS13 3 + T4
0u047
NULL 7
1N4148
6 CT F
A21 BUX84
NULL 6 2
3
A22 CT DGND
R24
-
10k
C14
A23 I-NEURO AD654
0u33
A24 5
R7
A25
390R
10k
A26
NULL
TP1
A27 NULL
A28
A29
A30
A31
A32
J2
1 J2-1
2 J2-2
3
4 NULL
5 J2-5
IC1 MP5
78xx
ICC 350 Neurotest
D11 7815
1 I O 3 POS15
J2-5 POS15
BA159 G
8
+
+
+
2
MP2
IC3
C9
C1
C12
TL082
100uF
100nF
1uF
C3
-
68nF
5
NULL 4
Diese Zeichnung ist urheber-
C Datum Name Gert/UNIT
1
rechtlich gesch tzt, daher
+
+
MP3 NEG15 Weitergabe und Vervielfltigung
G
Gezeich. M.Fritz 14-06-93 ohne unsere Genehmigung
ICC
C10
C2
C11
unzulssig
100uF
100nF
1uF
BA159 Gepr ft Benennung/Title
2 I 79xx O 3 NEG15
J2-5
7915
D12 LP un.: 30128-070 Neurotest-Board
IC2
R36=3k3 14.6.93 MF LP bs.: 40128-027
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 1 von 2 30128-070
CIRCUIT DIAGRAMS
Art. No. 80116-201
09 / 2004
Vdd
5
+15V POS15
MP7
R36
R29
3k3
1k3
IC7
9 16 2
I-NEURO
-
IC6 D3
8 1 NULL 1 U-STEUER
I-FREQ POS15 TL082
GND
R25 D5 1N4148
CNY66 3 +
R10
R20
R18
R16
1 +15V + 3 R26 D8
3k3
3k3
3k3
3k3
R11
RESET R R31 IC8 BCD/DEC 0
220k
9 16 9 14
CS12 C1 1 13k 1N4148
IC13 1k3 2 NEG15
2 R27 D9
30128-070
11 10 1 16 1 8 10 15
ESD0 1D ULN2004A 1 3
6 7 2 15 Vdd 13
2 1 7k5 1N4148
ESD1
+15V CNY66 4
13 12 3 14 12 6 R28 D10
ESD2 R32 IC9 4 5
4 5 4 13 16 9 11 7
ESD3 8 6
3 2 5 12 1k3 4 CLR 4k3 1N4148
ESD4 7
14 15 7 10 1 8 9 FRES R17 D4
ESD5 8
40174 6 11 Vdd 9 5 FTEST
+15V CNY66 2k4 1N4148
CIRCUIT DIAGRAMS
Neurotest Board
-
R33 IC10
8 9 16 9 4028 8
GND
1k3 NULL
+24V 1N4148 1 8
Vdd
D15 +15V CNY66
REL1 R34 IC11
16 9 POS15
1k3
1 8
Vdd
+15V CNY66
1N4148
R35 IC12
16 9
D16
R30
REL2 2k2
8k2
1 8 NULL
CNY66
R37
POS15
1k5
Vdd
Diese Zeichnung ist urheber-
8 D14 +15V C Datum Name rechtlich gesch tzt, daher
Gert/UNIT
+ Weitergabe und Vervielfltigung ICC
Gezeich. M.Fritz 14-06-93 ohne unsere Genehmigung
IC6 rot unzulssig
TL082 Gepr ft
C5
C4
C6
C7
Benennung/Title
68nF
68nF
68nF
68nF
-
4 GND
LP un.: 30128-070 Neurotest-Board
NULL NEG15
R36=3k3 14.6.93 MF LP bs.: 40128-027 Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 2 von 2 30128-070
ICC 350 Neurotest
233 / 266
ICC 350 Neurotest
Neurotest Board
40128-027
5
J1 Vdd Vdd
A1 +15V +15V UE1
A2
GND
A3
A4
C2
+24V 1 2
1u5
A5 J3
C4
1
68nF
A6
Vee C3
Vdd -15V 2
R3
A7
C6
1k
+15V 3
u15
A8 10:10 68nF
Vcc
3
A9 R1 IC1 L1
+5V
A10 R2 2
ESD0 T1
A11 100R 1m8
ESD1 1k BC517 SFH450
A12
+
ESD2
30128-071
A13
ESD3 R7
D1
2V7
C5
1
A14
2u2
ESD4
A15 GND GND 100R GND
ESD5
A16
ESD6
A17
ESD7
A18
CS12
A19
RESET
A20
CIRCUIT DIAGRAMS
CS13
A21
C
A27 4
LED-FERN B
IC2
A28 5
IC1 7 6
R4
R6
A29 1
Motherboard Neurotest
10k
1k
SFH350
A30
E
IC2 4050
A31 IC2
3 2
A32 1 FING-NEU 9 10
1
4050
IC2 4050
C1
R5
1N4148 D3
u47
22k
5 4 IC2
1 GND 11 12
GND GND D2 1
rot
4050
J2 4050
GND 1 GND
2 IC2
Vcc Vdd -15V 3 4 -15V Vdd Vcc 14 15
+5V +15V Vee +24V +24V Vee +15V +5V 1
5 6
GND
7 8 4050
9 10
11 12
13 14
ESD0 FING-A3
15 16
ESD1 FING-B3
17 18
ESD2 F-IIST
19 20
ESD3 FING-NEU
ICC 350 Neurotest
21 22
ESD4 F-INTENS
23 24
ESD5 RES-B4
25 26
ESD6 RES-B5
27 28
ESD7 RES-B6
29 30
RESET LED-FERN
31 32
CS11 RES-F2 Diese Zeichnung ist urheber-
33
B Datum Name rechtlich gesch tzt, daher
Gert/UNIT
34 RES-F3
CS12 Weitergabe und Vervielfltigung ICC
35 36 Gezeich. M.Fritz 15.10.92 ohne unsere Genehmigung
CS13 RES-F4
37 unzulssig
38 Gepr ft Benennung/Title
RES-ANA1
39 40
RES-ANA2 RES-F6 Neurotest-Motherboard
LP un.: 40128-028
ZMK
LP bs.: 30128-071
Zeichnungsnummer/DWG.NO
Nr. nderung Datum Name Blatt 1 von 1 30128-071
235 / 266
ICC 350 Neurotest
Motherboard Neurotest (bare)
40128-028
U_KENN
5
5k
5k
MASSE AE NE 5 + 3 +
TP1
TP2
J1 TL082 RES-ANA1 TL082 RES-ANA2
J2
J6
7 1
IC1 IC1
1
2
3
1
2
3
A1
- -
A2 6 2
GND J12 Vdd Vdd
A3 +15V +15V R33
J13 R35
A4
R7
R32
R8
R34
+24V
4k7
4k7
4k7
4k7
A5 2k7 2k7
Vee GND GND GND GND
A6
R21
R22
OSZ_OUT
10k
10k
Vdd -15V
REL2
REL3
REL4
REL5
REL1
REL6
A7 MP1
+15V UE2 R9 R26 D9
A8
A9
Vcc 3 +
+5V 2k4 Vdd C7 100R 1N4148 TL084
30128-200
MIC Board
REL2
REL3
REL4
REL5
REL1
REL6
GND
R25
ESD1 -
68nF
15k
D11
2
7
A12
R12
ESD2 C15
P6KE18CA
2
2k4
A13
1
-+
8
ESD3 C1
A14 R11 IC2 B/C1 C2 6
ESD4 J8 15:15 1uF
A15 LM318 B/C3
ESD5 UE1 2k4
A16 J9 1nF 3 +
-
5
ESD6 J10
A17
CIRCUIT DIAGRAMS
4
ESD7 J11 C10
A18
C3
C2
R10
R24
R27
C11
CS12 2 1
220pF
1nF
4k7
12k
20k
22nF
A19
RESET Vee
D10
A20 GND GND GND GND 68nF GND GND GND
C14 -15V
P6KE18CA
CS11
A21
3
2
1
3
2
1
3
2
1
A22 15:15 1uF
J3
J4
J5
A23 3 3
A24
A25 T3 T2
A26
2 2 MP2
A1 BS170 A2 BS170
A27 1 1
A28 GND GND R15
A29
+24V 2k
A30
TRANS_1 R18 C5 R16 R29 R30 R14 R13
A31
RES-ANA1 OSZ_OUT
A32
RES-ANA2 22k 22nF 5k6 2k4 2k4 2k4 390R
IC6 9 6 13
- - -
REL7
REL2
REL3
REL4
REL5
REL1
REL6
1 IC3 IC3 IC3
RESET R 8 7 14
9 TL084 TL084 TL084
CS12 C1
IC4 10 + 5 + 12 +
3 2 1 16 GND GND
ESD0 1D
R17
14 15 2 ULN2004A 15
2k4
R19
ESD1
10k
4 5 3 14
ESD2
13 12 4 13 Vdd
ESD3 +15V Vdd
C4
6 7 5 12 REL7 0.7
1nF
ESD4 +15V
11 10 6 11 +24V
ESD5
7 10
R23
40174
C6
J7
10k
22nF
IC5 1
0.7
C12
R28
8 9 2
1nF
2k4
1
R20
R2
R1
R3
R4
R5
R6
RESET R
GND GND 3
2k
2k
2k
2k
2k
2k
2k
9 GND 3
CS11 C1 +24V 4 Vee
C13
D8
68nF
BA159
5
Ventil -15V
6 7 T1
ESD0 1D 2 REL7
11 10 BS170 OSZI_ON
OSZI_ON 1.0
D7
rot
D1
rot
D2
rot
D3
rot
D4
rot
D5
rot
D6
gelb
ESD1 1
4 5 A1
ESD2
13 12 A2 GND GND
ESD3 GND
3 2
ESD4
14 15 TRANS_1
ESD5 Vdd
40174 +15V
Diese Zeichnung ist urheber-
RN1 D Datum Name rechtlich gesch tzt, daher
Gert/UNIT
2
Weitergabe und Vervielfltigung
4
ESD0 8 Gezeich. 28-05-93 M.Fritz ICC
3 ohne unsere Genehmigung
ESD1 + + unzulssig
4 IC3 IC1 Gepr ft Benennung/Title
ESD2 Vdd
5 TL084 TL082
C9
C8
1
+15V
68nF
68nF
ESD3 - - LP un.: 40128-064 MIC-Board
6 Vdd
ESD4 R31 +15V 4 D 4015 D10,D11 neu 10.12.96 Fritz
7
11
ESD5 CS11 LP bs.: 30128-200
8
C 3107 R17=2k4 30.4.94 Fritz
22k Vee Zeichnungsnummer/DWG.NO
CS12
9 -15V Nr. nderung Datum Name Blatt 1 von 1 30128-200
ICC 350 MIC-MIEN-DOKU
RESET
22k
237 / 266
ICC 350 MIC-MIEN-DOKU
MIC Board (bare)
40128-064
J11
5
F10
1
3
2
2 250mA
3
1
J10
D106
NS2004
NS2004
D109
D104 D105
Bruecke Bruecke
D103
1N5383
30128-661
C100
0.01uF
D102
1N5383
D101
1N5373
D107
CIRCUIT DIAGRAMS
D108
Protection Board
NS2004
NS2004
Diese Zeichnung ist urheber-
A Datum Name rechtlich gesch tzt, daher
Gert/UNIT
Weitergabe und Vervielfltigung ICC 350 MMH Doku
Gezeich. 01-12-97 E.Werner ohne unsere Genehmigung
unzulssig
Gepr ft 01-12-97 E.Werner Benennung/Title
239 / 266
ICC 350 MIC-MIEN-DOKU
Protection Board (bare)
40128-141
51601-056 51611-051
30128-063 30121-086 50610-009 51031-043 51603-000
51501-190
51501-191
51501-192
40128-103
40128-112 (F)
Gezeich. = Drawn
Geprüft = Checked
Freigabe = Approv.
Datum = Date*
Name = Name
Maßstab = Scale
Datei = File
Projekt = Project
Benennung = Title
Nummer = Number
40128-133 (D/INT)
40128-134 (F)
Gezeich. = Drawn
Geprüft = Checked
Freigabe = Approv.
Datum = Date*
Name = Name
Maßstab = Scale
Datei = File
Projekt = Project
Benennung = Title
Nummer = Number
30121-431
51708-043
40128-101
40128-110 (F)
Gezeich. = Drawn
Geprüft = Checked
Freigabe = Approv.
Datum = Date*
Name = Name
Maßstab = Scale
Datei = File
Projekt = Project
Benennung = Title
Nummer = Number
Abbreviations
The following list summarizes all those abbreviations and symbols which are used in this service manual.
Parts lists
This service manual includes no parts lists. However, if you should need to refer to part numbers, please see
Appendix A.
Measuring equipment
For a list of recommended measuring equipment for servicing the units ICC 200, ICC 300 and ICC 350,
please refer to this service manual (Chapter 1, Test program 16).
Any questions?
This service manual has been put together carefully and was subjected to a continuous improvement process
during its creation by the Service Department and/or the Development Department at ERBE Elektromedizin.
Art. No.: 80116-201
Nevertheless, you may still have questions; additionally, this manual cannot assume to be perfect and
completely without error. In such cases, please contact:
09 / 2004
Contents, formulation, structure, technical Technical questions regarding service and the
information units
Dipl.-Phys. Michael Grosse (Development Dept.) Service Manager Roland Bauer (Service Dept.)
Tel.: (+49) 70 71 / 755–254 Tel.: (+49) 70 71 / 755–454
E-mail: mgrosse@erbe-med.de E-mail: techservice@erbe-med.de