Lecture 10

Timers overflow

External Hardware Interrupts

Serial Communication Interrupts

Reset
• 1 for High Priority
• 0 for Low Priority
In 8051 the Interrupt Vector means the starting
address of the interrupt service routine i.e. the code
memory location where the execution is
transferred on the occurrence of interrupt
Difference between interrupt vectors is very small
3 bytes for Reset and 8 bytes for others
ISRs for interrupts other than reset, if smaller than 9
bytes of code, can be placed within the 8 bytes
For larger ISRs one must has to use jumps to transfer
control of execution to other locations where the
large ISRs are written in code memory
TF0/TF1/TF2 are set by hardware when
Timer0/Timer1/Timer2 overflows
EXF2 set by hardware when a capture/reload is caused by
a high to low transition on T2EX pin of 8052
TF0/TF1 are set by hardware when CPU starts executing
the relevant ISR or by software
Same ISR for TF2 and EXF2

TF2/EXF2 are cleared by software in the ISR and not by

hardware
RI is set when a complete byte is received through
RXD pin
Ti is set when a complete byte is transmitted through
TXD pin
Same ISR for both RI and TI

RI/TI is cleared by software in ISR and not by

hardware
 Activated by a low level or falling edge on INT0/INT1 line
(Port 3.2/3.3) of 8051
 Level or Edge triggering is selected by IT0/IT1 bits in TCON
register (TCON.0 and TCON.2)
 Interrupt flag IE0/IE1 is cleared by hardware on the execution
transfer to ISR
 External Interrupt pins are sampled once in each machine cycle
so the input must be held for at least one machine cycle (12
clock periods)
 For edge triggered interrupts, the input must be held high for
one machine cycle and low for another
 Level triggered interrupt must retain till ISR begins and cleared
before ISR finishes