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  • Vlsi

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    Jamila Shakir
    7 views7 pages
    The document describes basic gate designs including a transmission gate with driver, NAND2 gate, NOR2 gate, and NAND3 and NOR3 gates. It shows the circuit schematics for each gate using pFETs, nFETs, and wiring to connect the inputs and outputs. The transmission gate uses a single pFET and nFET controlled by input signals to pass a signal from its input to output. The NAND and NOR gates are constructed from combinations of pFETs and nFETs to perform the logic functions.

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    vlsi

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    The document describes basic gate designs including a transmission gate with driver, NAND2 gate, NOR2 gate, and NAND3 and NOR3 gates. It shows the circuit schematics for each gate using pFETs, nFETs, and wiring to connect the inputs and outputs. The transmission gate uses a single pFET and nFET controlled by input signals to pass a signal from its input to output. The NAND and NOR gates are constructed from combinations of pFETs and nFETs to perform the logic functions.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as ppt, pdf, or txt
    7 views7 pages

    Vlsi

    Uploaded by

    Jamila Shakir
    The document describes basic gate designs including a transmission gate with driver, NAND2 gate, NOR2 gate, and NAND3 and NOR3 gates. It shows the circuit schematics for each gate using pFETs, nFETs, and wiring to connect the inputs and outputs. The transmission gate uses a single pFET and nFET controlled by input signals to pass a signal from its input to output. The NAND and NOR gates are constructed from combinations of pFETs and nFETs to perform the logic functions.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as ppt, pdf, or txt
    of 7

    BASIC GATE DESIGN

    TRANSMISSION GATE WITH


    DRIVER Vdd

    y y
    x X

    s
    s

    gnd
    Vdd
    Vdd

    F out

    a
    a b
    gnd
    b gnd

    NAND2 GATE
    Vdd
    Vdd

    F
    out

    gnd

    GND
    a b

    a
    b
    NOR2 GATE
    pFET Vdd

    OUT

    + wiring
    gnd NAND2
    nFET

    Vdd
    NOR2

    OUT

    gnd
    Vdd Vdd

    out
    out

    a b c c
    a b
    gnd gnd

    NOR3 NAND3

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