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Syllabus ECVE
Syllabus ECVE
FOR
WITH SPECIALIZATION IN
SEMESTER - I
Hrs / Week Evaluation Scheme (Marks)
Sl. Course Credits
Subject Sessional
No. No. (C)
L T P ESE Total
Sub
TA CT
Total
1 LMV 101 Analog Integrated Circuit Design 4 0 0 25 25 50 100 150 4
Electives: New Electives may be added by the department according to the needs of
emerging fields of technology. The name of the elective and its syllabus should
be submitted to the University before the course is offered
1
SEMESTER - II
Hrs / Week Evaluation Scheme (Marks)
Sl. Course Credits
Subject Sessional
No. No. (C)
L T P ESE Total
Sub
TA CT
Total
1 LMV 201 Principles of Real Time System 4 0 0 25 25 50 100 150 4
Electives: New Electives may be added by the department according to the needs of
emerging fields of technology. The name of the elective and its syllabus should
be submitted to the University before the course is offered
2
SEMESTER - III
* TA based on a Technical Report submitted together with presentation at the end of the
Industrial Training
** Evaluation of the Industrial Training will be conducted at the end of the third semester
by a panel of examiners, with at least one external examiner, constituted by the
University
SEMESTER - IV
* 50% of the marks to be awarded by the Project Guide and the remaining 50% to be
awarded by a panel of examiners, including the Project Guide, constituted by the
Department
** Thesis evaluation and Viva-voce will be conducted at the end of the fourth semester by a
panel of examiners, with at least one external examiner, constituted by the University
3
L T P C
LMV 101 ANALOG INTEGRATED CIRCUIT DESIGN
4 0 0 4
Module 1
MOS transistors - Advanced MOS modeling in linear, saturation and cutoff - high
frequency equivalent circuit.
Module 2
Current mirrors – active loads - output stages- cascode and Folded cascode structures-
frequency response
Module 3
Module 4
Text Books :
1. David A Johns & Ken Martin, ‘Analog Integrated Circuit Design’ John Wiley and
Sons, 2008
2. Gray, Hurst, Lewis, and Meyer, “Analysis and Design of Analog Integrated
th
Circuits”, 5 edition by, John Wiley and Sons, 2009.
3. Behzad Razavi, ‘Design of Analog CMOS Integrated Circuit’ Tata-Mc GrawHill,
2008
References:
1. Philip Allen & Douglas Holberg, ‘ CMOS Analog Circuit Design’, Oxford
University Press, 2009
2. R. Gregorian, G.C. Temes, "Analog MOS ICs for Signal Processing", Wiley 2004.
4
L T P C
LMV 102 CMOS DIGITAL INTEGRATED CIRCUITS
4 0 0 4
Module 1
Module 2
Module 3
Inverters and logic gates- NMOS and CMOS inverters, inverter ratio, DC and transient
characteristics, switching times, super buffers, driving large capacitance loads, CMOS logic
structures, transmission gates.
Module 4
Text Books:
1. Sung Mo Kang and Yusuf Lebelci, “CMOS Digital integrated Circuits Analysis and
Design”, Tata McGraw- Hill , New Delhi, 2003.
3. Neil H E Weste, David Harris and Ayan Banerjee,” CMOS VLSI Design- A circuit
System Perspective”, Pearson Education, 2004.
4. Muller Richards, Kamins and Theodre “Device Electronics for Integrated Circuits”
John Wiley, New York, 2003.
5
L T P C
LMV 103 ADVANCED DIGITAL SYSTEM DESIGN
4 0 0 4
Module 1
Module 2
Module 3
Study of programmable Logic Families- PLD, CPLD, FPGA, PLA. Synthesis and
implementation issues
Module 4
Text Books :
2. Donald D Givone , “Digital Principles and Design “, Tata Mc Graw Hill, 2004.
3. Parag K Lala, “Digital Circuit Testing and Testability” ,Academic Press, 1997
6
INTRODUCTION TO VLSI TECHNOLOGY & L T P C
LMV 104
DESIGN 4 0 0 4
Module 1
Oxidation technologies in VLSI and ULSI -.Kinetics of Silicon dioxide growth both for
thick, thin and ultra thin films- High k and low k dielectrics for ULSI- Solid State diffusion
modeling and technology; Ion Implantation modeling, damage annealing
Module 2
Photolithography, E-beam lithography and newer lithography techniques for VLSI/ULSI.
CVD techniques for deposition of films; Etching- Evaporation and sputtering techniques-
metal interconnects; Multi-level metallization schemes. Plasma etching and RIE techniques
Module 3
Process integration -NMOS, CMOS and Bipolar process.
Module 4
VLSI Design - Introduction to ASICS, CMOS LOGIC and ASIC Library Design - Types of
ASICs – design flow- CMOS transistors CMOS design rules – combinational logic cell –
sequential logic cell- Data path logic cell – transistors and resistors – transistor parasitic
capacitance – logical effort – library cell design – library architecture
Text Books :
1. C.Y. Chang and S.M.Sze (Ed), ULSI Technology, McGraw Hill Companies Inc,
2002, reprinted.
2. S.M. Sze (Ed), VLSI Technology, 2nd Edition, McGraw Hill, 2008.
3. Stephen Campbell, The Science and Engineering of Microelectronics, Oxford
University Press, 2001.
4. M.J.S. Smith, “Application – specific integrated circuits” – Addison – Wesley
Longman Inc. 2008.
7
References:
1. S.K. Ghandhi, VLSI Fabrication Principles, John Wiley Inc., New York, 2008.
2. James Plummer, M. Deal and P.Griffin, Silicon VLSI Technology, Prentice Hall
8
L T P C
LMV 105 - 1 WIRELESS COMMUNICATION
3 0 0 3
Second generation cellular systems: GSM specifications and Air Interface - specifications,
IS 95 CDMA- 3G systems: UMTS & CDMA 2000 standards and specifications
9
Text Books:
1. Andrea Goldsmith, “Wireless Communications”, Cambridge University Press, 2005.
2. Simon Haykin & Michael Moher, “Modern Wireless Communications”, Person
Education, 2007.
3. T. S. Rappaport, “Wireless Communication, Principles & Practice”, Dorling Kindersley
(India) Pvt. Ltd., 2009.
References:
10
L T P C
LMV 105 - 2 DSP INTEGRATED CIRCUITS
3 0 0 3
Text Books :
References:
1. Texas Instruments Documentation, Analog Devices Documentation
11
L T P C
LMV 105 - 3 CAD FOR VLSI
3 0 0 3
Module 1
Logic Synthesis and Technology Mapping-Introduction, Y Chart-physical design top-down
flow, comparison of FPGA/ASIC design styles. review of graph theory and data structures-
computer aided sythesis and optimization, circuit models synthesis-logic synthesis,
architectureral synthesisis and optimization. Graph, graph optimization problems and
algorithms. Introduction to combinational logic synthesis-binary decision
diagrams:principles implementation and constructions, manipulation, variable ordering,
applications to verification and optimizations. Two level and multi level optimization,
sequential logic optimization. Technology mapping. Cell library binding,.
Module 2
Physical design automation- floor planning. Power planning. Clock tree synthesis.
Placement. Pin assignment.routing:global,detail,over the cell routing. Clock and power
routing.
Module 3
Module 4
Timing analysis prelayout and post layout, static and dynamic timing analysis for single and
multiple path data flows.copensational techniques. Critical path delays. Back
annotation,circuit extraction and DRC, BIST.
Text Books:
12
2. Naveed Sherwani “Algorithms for VLSI Physical Design Automation”, 3rd edition,
Springer International edition, 2005.
3. H Yosuff and S M Sait “VLSI Physical Design Automation Theory and Practice”,
Mc Graw Hill Pub. , 1995.
References:
2. Sabih. H. Gerez, “Algorithm for VLSI Design Automation Theory and Practice”,
John Willey & Sons Ltd., 2004
13
L T P C
LMV 105 - 4 TESTING OF VLSI CIRCUITS
3 0 0 3
Module 1
Introduction-VLSI testing process and Test Equipment-Test Economics and Product
Quality- why fault modeling-Fault Modeling-Logic and Fault Simulation-glossary of Faults-
single stuck-at-faults-functional equivalence-bridging faults.
Module 2
Logic simulation-modeling single states-algorithm for true value simulation-serial and
parallel fault simulation-Testability Measures-Combinational Circuit Test Generation-
Sequential Circuit Test Generation.
Module 3
Introduction to SCAN-Binary Decision Diagram-combinational ATPG Algebra-redundancy
–D algorithm-PODEM algorithm-FAN algorithm-circuit test approach-observability-
controllability.
Module 4
Memory Test-Analog and Mixed signal Test-delay test-IDDQ Test. DFT Fundamentals-
ATPQ Fundamental-Scan Architecture and Technique. System Test- Embedded Core Test-
Future Testing.
Text Books:
2. Alfred L Cronch, “Design for Test for Digital IC’s and Embedded Core system”,
Prentice Hall, 1999.
3. Niraj Jha and Sanjeep K Gupta, “Testing of Digital Systems”, Cambridge University
Press, 2003.
14
L T P C
LMV 106 - 1 ADVANCED MICROCONTORLLERS
3 0 0 3
Module 1
Low pin count controllers – Atmel AVR family – ATTiny15L controller - architecture – pin
descriptions – features – addressing modes – I/O space – reset and interrupt handling – reset
sources - Tunable internal oscillator.
Module 2
Timers – Watch dog timer – EEPROM – preventing data corruption – Analog comparator –
A/D converter – conversion timing – ADC noise reduction – PortB – alternate functions –
memory programming – fuse bits – high voltage serial programming – algorithm.
Module 3
Module 4
Power saving modes – Dual clock operation – Multi input wake up – USART – framing
formats – baud rate generation – A/D conversion – operating modes – prescaler – Interrupts
– interrupt vector table – Watch dog – service window – Micro-wire interface – waveforms.
Text Books:
References:
15
1. DS101374: National Semiconductor reference manual.
2. National semiconductor web site – www.national.com
3. 1187D: Atmel semiconductor reference manual.
4. Atmel semiconductor web site – www.atmel.com
5. DS30292B: Microchip reference manual. Microchip semiconductor web site –
www.microchip.com
16
DESIGN OF DIGITAL SIGNAL PROCESSING L T P C
LMV 106 - 2
SYSTEM 3 0 0 3
Module 1
Module 2
Programming - Instruction Set and Addressing Modes - Code Composer Studio - Code
Generation Tools - Code Composer Studio Debug Tools – Simulator.
Module 3
Digital Signal Processing Applications : Filter Design - FIR & IIR Digital Filter Design -
filter Design programs using MATLAB - Fourier Transform: DFT, FFT programs using
MATLAB - Real Time Implementation : Implementation of Real Time Digital filters using
DSP - Implementation of FFT applications using DSP - DTMF Tone Generation and
Detection
Module 4
Text Books:
17
References:
1. Rulph Chassaing, “DSP Applications using ‘C’ and the TMS320C6X DSK”, 1st
Edition, 2002.
2. Andrew Bateman, Warren Yates, Digital Signal Processing Design, 1 st Edition,
1989.
3. John G Proakis, Dimitris G Manolakis, “Introduction to Digital Signal Processing”,
4th Edition, 2006.
4. Kreig Marven & Gillian Ewers, A Simple approach to Digital Signal processing, 1st
Edition; Wiely Interscience, 1996
5. JAMES H. McClellan, Ronald Schaffer and Mark A. Yoder, DSP FIRST - A
Multimedia Approach, 1 st Edition; Prentice Hall, 1997
6. Oppenheim A.V and Schafer R.W, Digital Signal Processing, 1 st Edition; PH, 1975
18
L T P C
LMV 106 - 3 COMMUNICATION NETWORK
3 0 0 3
Module 1
Architectural concepts in ISO’s OSI layered model, layering in the Internet. TCP/IP
protocol stack. Transport layer - TCP and UDP. Network layer - IP, routing,
internetworking.
Module 2
Module 3
Markov chain- Discrete time and continuous time Markov chains- Poisson process- Queuing
models for Data gram networks- Little’s theorem- M/M/1 queuing systems- M/M/m/m
queuing models- M/G/1 queue- Mean value analysis- Time reversibility- Closed queuing
networks- Jackson’s Networks.
Module 4
Text books:
19
3. S. Keshav, “An Engineering Approach to Computer Networking”, Addison Wesley,
2008.
4. Peterson L.L. & Davie B.S., “Computer Networks: A System Approach”, Morgan
Kaufman Publishers, 2007.
5. Anurag Kumar, D. Manjunath, and Joy Kuri, “Communication Networking: An
Analytical Approach”, Morgan Kaufman Publ., 2004.
20
L T P C
LMV 106 – 4 ASIC DESIGN
3 0 0 3
Module 1
Programmable ASICS, Programmable ASIC Logic cells and Programmable ASIC I/o cells -
Anti fuse- static RAM – EPROM and EEPROM technology, PREP benchmarks- Actel
ACT-Xilinx LCA- Altera FLEX- Altera MAX DC & AC inputs and outputs – clock &
Power inputs – Xilinx I/O blocks.
Module 2
Programmable ASIC Interconnect, Programmable ASIC design software and Low level
design entry -Actel ACT-Xilinx LCA – Xilinx EPLD – Altera MAX 5000 and 7000 – Altera
MAX 9000 – Altera FLEX- Design systems – Logic synthesis – half gate ASIC schematic
entry – low level design language – PLA tools – ENDIF-CFI design representation.
Module 3
Logic Synthesis, Simulation and Testing - Verilog and logic synthesis – VHDL and logic
synthesis – types of simulation – boundary scan test- fault simulation automatic test pattern
generation.
Module 4
ASIC construction, Floor Planning, Placement and routing -System partition – FPGA
partitioning – partitioning methods – floor planning – placement – physical design flow-
global routing – detailed routing – special routing – circuit extraction – DRC.
Text Books:
1. M.J.S. Smith, “Application – specific integrated circuits”–Addison–Wesley
Longman Inc. 1997.
2. Andrew Brown, - “VLSI circuits and systems in silicon”, Mc Graw Hill, 1991.
3. S.D. Brown, R.J. Francis, J.Rox, Z.G. Uranesic, “Field Programmable gate arrays”,
Khuever academic publisher, 1992.
4. S.Y.Kung, H.J. Whilo House, T.Kailath, “VLSI and Modern Signal Processing”,
Prentice Hall, 1984.
21
L T P C
LMV 107 SEMINAR – I
0 0 2 1
Each student shall present a seminar on any topic of interest related to the core / elective
courses offered in the first semester of the M. Tech. programme. He / she shall select the
topic based on the references from international journals of repute, preferably IEEE
journals. They should get the paper approved by the Programme Co-ordinator / Faculty
member in charge of the seminar and shall present it in the class. Every student shall
participate in the seminar. The students should undertake a detailed study on the topic and
submit a report at the end of the semester. Marks will be awarded based on the topic,
presentation, participation in the seminar and the report submitted.
L T P C
LMV 108 VLSI DESIGN AND SIGNAL PROCESSING LAB
0 0 3 2
System simulation experiments based on the courses LMV 102, LMV 103 and the elective
courses opted by the student in the first semester.
22
L T P C
LMV 201 PRINCIPLES OF REAL TIME SYSTEM
4 0 0 4
Introduction - Issues in Real Time Computing, Structure of a Real Time System, Task
classes, Performance Measures for Real Time Systems, Estimating Program Run Times.
Task Assignment and Scheduling - Classical uniprocessor scheduling algorithms,
Uniprocessor scheduling of IRIS tasks, Task assignment, Mode changes, and Fault Tolerant
Scheduling.
Programming Languages and Tools - Desired language characteristics, Data typing, Control
structures, Facilitating Hierarchical Decomposition, Packages, Run - time (Exception) Error
handling, Overloading and Generics, Multitasking, Low level programming, Task
Scheduling, Timing Specifications, Programming Environments, Run - time support.
Basic Definition, Real time Vs General Purpose Databases, Main Memory Databases,
Transaction priorities, Transaction Aborts, Concurrency control issues, Disk Scheduling
Algorithms, Two-phase Approach to improve Predictability, Maintaining Serialization
Consistency, Databases for Hard Real Time Systems.
Module 4 :
a. Communication
b. Clock Synchronization
1. C.M. Krishna, Kang G. Shin, "Real Time Systems", McGraw - Hill International
Editions, 1997
24
L T P C
LMV 202 INTRODUCTION TO EMBEDDED SYSTEM
4 0 0 4
Module 1
a. Embedded Architecture
b. Networks
Hardware and Software Architectures – Networks for Embedded Systems – I2C – CAN
Bus– Zig Bee - Blue tooth – SPI - USB - Ethernet – Myrinet – Internet – Network–Based
design – Communication Analysis – System Performance Analysis
Multiple Processes in an Application - Data sharing by multiple tasks and routines- Inter
Process Communication
Operating System Services , I/O Subsystems - Network Operating Systems - Real Time and
Embedded System Operating systems. Interrupt routines in RTOS Environments - RTOS
Task Scheduling models , Interrupt Latency and response Times – Performance metric in
scheduling models
25
Text Books:
References:
26
L T P C
LMV 203 DIGITAL IMAGE PROCESSING
4 0 0 4
Module 1
Image representation: Gray scale and colour Images, image sampling and quantization. Two
dimensional orthogonal transforms: DFT, WHT, Haar transform, KLT, DCT. Image
enhancement - filters in spatial and frequency domains, histogram-based processing,
homomorphic filtering. Edge detection - non parametric and model based approaches, LOG
filters, localisation problem.
Module 2
Image Restoration: Degradation Models, PSF, circulant and block - circulant matrices,
deconvolution, restoration using inverse filtering, Wiener filtering and maximum entropy-
based methods.Image Segmentation: Pixel classification, Bi-level thresholding, Multi-level
thresholding, P-tile method, Adaptive thresholding, Spectral & spatial classification, Edge
detection, Hough transform, Region growing.
Module 3
Fundamental concepts of image compression - Compression models - Information theoretic
perspective - Fundamental coding theorem - Lossless Compression: Huffman Coding-
Arithmetic coding - Bit plane coding - Run length coding - Lossy compression: Transform
coding – Image compression standards.
Module 4
Fundamentals of Wavelet Transforms, DWT in one and two Dimensions, Mallat structure
for implementation in 2 Dimensions, Applications of DWT to Image Compression, SPIHT,
JPEG 2000
Text Books:
27
4. A. Rosenfold and A. C. Kak, “Digital Image Processing”, Vols. 1 and 2, Prentice
Hall, 1986.
5. H. C. Andrew and B. R. Hunt, “Digital Image Restoration”, Prentice Hall, 1977.
6. R. Jain, R. Kasturi and B.G. Schunck, Machine Vision, McGraw-Hill International
Edition, 1995.
7. A. M. Tekalp, “Digital Video Processing”, Prentice-Hall, 1995.
8. A. Bovik, Handbook of Image & Video Processing, Academic Press, 2000
28
L T P C
LMV 204 HIGH SPEED DIGITAL DESIGN
4 0 0 4
Frequency, time and distance - Capacitance and inductance effects - High seed properties of
logic gates - Speed and power -Modelling of wires -Geometry and electrical properties of
wires - Electrical models of wires - transmission lines - lossless LC transmission lines -
lossy LRC transmission lines - special transmission lines
Power supply network - local power regulation - IR drops - area bonding - onchip bypass
capacitors - symbiotic bypass capacitors - power supply isolation - Noise sources in digital
system - power supply noise - cross talk - intersymbol interference
Signalling modes for transmission lines -signalling over lumped transmission media -
signalling over RC interconnect - driving lossy LC lines - simultaneous bi-directional
signalling - terminations - transmitter and receiver circuits
Timing fundamentals - timing properties of clocked storage elements - signals and events -
open loop timing level sensitive clocking - pipeline timing - closed loop timing - clock
distribution - syncronisation failure and metastability - PLL and DLL based clock aligners
Text Books:
29
REAL TIME EMBEDDED SYSTEM AND L T P C
LMV 205 - 1
CONTROLLERS 3 0 0 3
Module 1
Module 2
Module 3
Module 4
Text Books:
1. Andrew N Sloss, Dominic Symes, Chris Wright “ARM System Developers Guide-
Designing and Optimizing System software”, Morgan Kaufmann Publishers, 2004.
2. Steave Furber, “ARM System on Chip Architecture”, Addison Wesley, 2000.
30
References:
1. Vx Works Programmers Guide.
31
ANALYSIS AND DESIGN OF ANALOG AND L T P C
LMV 205 - 2
MIXED VLSI CIRCUITS 3 0 0 3
Module 1
Depletion region of a PN junction-Large signal model of bipolar transistors-small signal
model of biplolar transistor-short channel effects in MOS transistors-weak inversion in
MOS transistors-substrate current flow in MOS transistor
Module 2
Analysis of difference amplifiers with active load using BJT and FET- Supply and
Temperature independent biasing techniques-voltage references. Output Stages-Emitter
follower-source follower and push pull output stages.
Module 3
Module 4
Text Books:
1. Phillip E Allen and Douglas R Holberg “CMOS Analog Circuit Design”, Oxford
University Press, USA, 2002.
2. Behzad Razavi, “Analysis and Design of CMOS integrated Circuits”, Tata Mc Graw
Hill, 2008.
3. Gray, Meyer, Lewis Hurst “Analysis and Design of Analog IC”, Wiley International
4th Edition, 2009.
Module 1
DSP array processor architectures, fast convolution- Cook Toom Algorithm, Winograd
algorithm, Iterated convolution, cyclic convolution, algorithmic strength reduction in filters
and transforms, pipelined and parallel recursive and adaptive filters.
Module 2
Scaling and round off noise, digital lattice filter structures, bit level arithmetic architectures,
parallel multipliers, interleaved floor plane and bit plane based digital filters, bit serial
multipliers, bit serial filter design and implementations
Module 3
Pipelining and parallel processing- pipelining of FIR digital filters, parallel processing,
pipelining and parallel processing for low power, retiming, unfolding and folding
transformations, register minimization techniques, register minimization in folded
architectures
Module 4
Synchronous wave and asynchronous pipelines, synchronous pipelining and clocking styles
clock skew and clock distribution in a bit level pipelined VLSI design, wave pipelining and
asynchronous pipelining
Text Books:
References:
33
L T P C
LMV 205 - 4 MICRO ELECTRO MECHANICAL SYSTEM
3 0 0 3
Module 1
Module 2
Fundamental devices and processes, Multi User MEMS Process (MUMPs), SUMMiT:
design rules; applications; micro hinges and deployment actuators, CMOS MEMS,
cleanroom lab techniques, MicroOptoElectroMechanical Systems (MOEMS), bioMEMS
and biomaterials, piezoresistivity; scanning probe microscopy, scaling laws, applications.
Module 3
Module 4
Application case studies: MEMS Scanners and Retinal Scanning Displays (RSD), Grating
Light Valve (GLV), Digital Micromirror Devices (DMD), Optical switching,Capacitive
Micromachined Ultrasonic Transducers (CMUT)
Text Books:
1. Gregory T A, Kovacs Micromachined Transducers Sourcebook, WCB
McGraw-Hill, 1998.
2. Nadim Maluf, An introduction to Microelectromechanical system design, Artech
House, 2000
3. Victor M. Bright, Editor, Selected papers on Optical MEMS, SPIE Milestone
Series, Volume MS 153, SPIE Press, 1999
34
4. Mohamed Gad-el-Hak, Editor, The MEMS Handbook, CRC Press, Baco Raton,
2002
5. Marc Madou, Fundamentals of Microfabrication, CRC Press, New York, 2002.
6. Gregory T. A. Kovacs, Micromachined Transducers Sourcebook, WCB /
McGraw-Hill, 1998
7. W. Trimmer, Editor, Micromechanics and MEMS: Classic and Seminal Papers to
1990, IEEE Press, 1997.
35
SYSTEM DESIGN USING EMBEDDED L T P C
LMV 206 - 1
PROCESSORS 3 0 0 3
Memory: Memory write ability and storage performance - Memory types - composing
memory - Advance RAM interfacing communication basic - Microprocessor interfacing I/O
addressing - Interrupts - Direct memory access - Arbitration multilevel bus architecture -
Serial protocol - Parallel protocols - Wireless protocols - Digital camera example.
Modes of operation - Finite state machines - Models - HCFSL and state charts language -
state machine models - Concurrent process model - Concurrent process - Communication
among process -Synchronization among process - Implementation - Data Flow model.
Design technology; Automation synthesis - Hardware software co-simulation - IP cores -
Design Process Model.
Text Books:
2. Frank Vahid and Tony Givargis, "Embedded System Design", John Wiley & sons, 2006
References:
1. ARM, AMBA Bus Specification.
36
L T P C
LMV 206 - 2 ARTIFICIAL NEURAL NETWORKS
3 0 0 3
Module 1
Module 2
Recurrent neural networks: preliminaries- states and state dynamics, Lyupanov stability,
Cohen Grossberg Theorem, associative learning, Hopfield neural networks, error
performance of Hopfield Neural Networks, applications of Hopfield Neural networks,
simulated annealing, Boltzmann machines, learning law in Boltzmann machines,BAMs.
Module 3
Support Vector machines and Radial Basis function networks-learning from examples and
generalization, Support Vector Machines, Regularization theory route to RBF NN,
Generalized RBFNN, learning in RBFNN, image classification, other models for valid
generalization.
Module 4
Text Books:
References:
Basic multi-rate operations and their spectral representation. Linear Periodically Time
varying systems, interconnection of building blocks, Fractional Sampling rate alteration
poly-phase representation, multistage implementation, applications of multi-rate systems,
special filters and filter banks.
Errors created in the QMF bank, aliasfree QMF system, power symmetric QMF banks, M-
channel filter banks, poly-phase representation, perfect reconstruction systems, alias-free
filter banks, tree structured filter banks, trans-multiplexers.
Lossless transfer matrices, filter bank properties induced by paraunitariness, two channel
Para-unitary lattices, M-channel FIR Para-unitary QMF banks, transform coding.
Module 4
Necessary conditions, lattice structures for linear phase FIR PR QMF banks, formal
synthesis of linear phase FIR PR QMF lattice.
Pseudo-QMF bank and its design, efficient poly-phase structures, properties of cosine
matrices, cosine modulated perfect reconstruction systems.
Text Books:
1. P.P. Vaidyanathan, “Multirate Systems and Filter Banks,"Pearson Education (Asia) Pte.
Ltd, 2008.
38
References:
39
L T P C
LMV 206 - 4 HARDWARE/SOFTWARE CO DESIGN
3 0 0 3
Module 1
Specification of embedded systems-Why Co-design? –Comparison of co-design
approaches-MoCs: State oriented, Activity oriented, Structure oriented, Data oriented and
Heterogeneous- Software CFSMs-Processor Characterization.
Module 2
HW/SW Partitioning Methodologies-principle of hardware/software mapping-Real time
scheduling-Design specification and constraints on embedded systems- trade offs –
Partitioning granularity-Kernigan-Lin Algorithm- Extended Partitioning- Binary
Partitioning: GCLP algorithm.
Module 3
Co-synthesis & Estimation –Software synthesis –Hardware Synthesis –Interface Synthesis-
Co-synthesis Approaches: Vulcan, Cosyma, Cosmos, Polis and COOL-estimation:
Hardware area, execution timing and power: Software memory and execution timing.
Module 4
Co simulation and Co-verification- principles of co-simulation-abstract level:detailed level-
co-simulation as partition support-cosimulation using Ptolemy approach.
Text Books:
1. Felice Balarin, Massimiliano Chiodo Paolo Giusto, Harry Hsieh, Attila Jurecska,
Luciano Lavagno, Claudio Passerone, Alberto Sangiovanni- Vincentelli, Ellen
Sentovich, Kei Suzuki, Bassamssam Tavvara, “Hardware-software co-design of
embedded system: POLIS Approach”, Springer, 2004.
2. Raf Niemann, “Hardware/ Software Co-design for Data Flow Dominated Embedded
Systems”, Spring, 1998.
References:
Each student shall present a seminar on any topic of interest related to the core / elective
courses offered in the second semester of the M. Tech. programme. He / she shall select the
topic based on the references from international journals of repute, preferably IEEE
journals. They should get the paper approved by the Programme Co-ordinator / Faculty
member in charge of the seminar and shall present it in the class. Every student shall
participate in the seminar. The students should undertake a detailed study on the topic and
submit a report at the end of the semester. Marks will be awarded based on the topic,
presentation, participation in the seminar and the report submitted.
L T P C
LMV 208 EMBEDDED SYSTEM LAB
0 0 3 2
System simulation experiments based on the courses LMV 201, LMV 202 and the elective
courses opted by the student in the second semester.
41
L T P C
LMV 301 INDUSTRIAL TRAINING
0 0 20 10
L T P C
LMV 302 MASTER’S THESIS PHASE - I
0 0 10 0
The thesis (Phase - I) shall consist of research work done by the candidate or a
comprehensive and critical review of any recent development in the subject or a detailed
report of project work consisting of experimentation / numerical work, design and or
development work that the candidate has executed.
In Phase - I of the thesis, it is expected that the student should decide a topic of thesis, which
is useful in the field or practical life. It is expected that students should refer national &
international journals and proceedings of national & international seminars. Emphasis
should be given to the introduction to the topic, literature survey, and scope of the proposed
work along with some preliminary work / experimentation carried out on the thesis topic.
Student should submit two copies of the Phase - I thesis report covering the content
discussed above and highlighting the features of work to be carried out in Phase – II of
the thesis. Student should follow standard practice of thesis writing. The candidate will
deliver a talk on the topic and the assessment will be made on the basis of the work and talks
there on by a panel of internal examiners one of which will be the internal guide. These
examiners should give suggestions in writing to the student to be incorporated in the Phase –
II of the thesis.
42
L T P C
LMV 401 MASTER’S THESIS
0 0 30 20
In the fourth semester, the student has to continue the thesis work and after successfully
finishing the work, he / she has to submit a detailed thesis report. The work carried out
should lead to a publication in a National / International Conference. They should have
submitted the paper before M. Tech. evaluation and specific weightage should be given to
accepted papers in reputed conferences.
A comprehensive viva-voce examination will be conducted at the end of the fourth semester
by an internal examiner and external examiners appointed by the university to assess the
candidate’s overall knowledge in the respective field of specialization.
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