CAD for VLSI Design - II

Lecture 17
V. Kamakoti and Shankar Balachandran
 Overview
• Logical Effort
– Multistage Logic Networks
 Multistage Logic Networks
• Logical effort generalizes to multistage networks
• Path Logical Effort G= gi ∏
Cout-path
• Path Electrical Effort
H =
Cin-path
F = ∏ f i = ∏ gi hi
• Path Effort
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
 Multistage Logic Networks
• Logical effort generalizes to multistage
networks
G = ∏ gi
• Path Logical Effort
Cout − path
• Path Electrical Effort H = C
in − path

• Path Effort F = ∏ f i = ∏ gi hi

• Can we write F = GH?

 Paths that Branch
• No! Consider paths that branch:
15
90
5
G =
15
H = 90
GH =
h1 =
h2 =
F = GH?
 Paths that Branch
• No! Consider paths that branch:
15
90
5
G =1
15
H = 90 / 5 = 18 90
GH = 18
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
 Branching Effort
• Introduce branching effort
– Accounts for branching between stages in
path
Con path + Coff path
b=
Con path Note:

∏h = BH
B = ∏ bi
i

• Now we compute the path effort

– F = GBH
 Multistage Delays
• Path Effort Delay DF = ∑ f i

• Path Parasitic Delay P = ∑ pi

• Path Delay D = ∑ d i = DF + P
 Designing Fast Circuits
D = ∑ d i = DF + P
• Delay is smallest when each stage bears same effort
1
fˆ = gi hi = F N

• Thus minimum delay of N stage path is

1
D = NF + PN

• This is a key result of logical effort

– Find fastest possible delay
– Doesn’t require calculating gate sizes
 Gate Sizes
• How wide should the gates be for least delay?

fˆ = gh = g CCoutin
gi Couti
⇒ Cini =
fˆ

• Working backward, apply capacitance

transformation to find input capacitance of each
gate given load it drives.
• Check work by verifying input cap spec is met.
 Example: 3-stage path
• Select gate sizes x and y for least delay
from A to B x

y
x
45
A 8
x
y B
45
 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G=
Electrical Effort H=
Branching Effort B=
Path Effort F=
Best Stage Effort fˆ =
Parasitic Delay P=
Delay D=
 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
 Example: 3-stage path
• Work backward for sizes
y=
x= x

y
x
45
A 8
x
y B
45
 Example: 3-stage path
• Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3
 Best Number of Stages
• How many stages should a path use?
– Minimizing number of stages is not always
fastest
• Example: drive 64-bit datapath with unit
inverter InitialDriver 1 1 1 1

D = DatapathLoad 64 64 64 64

N: 1 2 3 4
f:
D:
 Best Number of Stages
• How many stages should a path use?
– Minimizing number of stages is not always fastest
• Example: drive 64-bit datapath with unit inverter

InitialDriver 1 1 1 1

D = NF1/N + P 8 4 2.8

= N(64)1/N + N 16 8

23

DatapathLoad 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest
 References
• Adnan Aziz’s Logic Synthesis Course
website
•
http://research.sun.com/vlsi/Publications/KP
Disclosed/logeff/logeff.pdf
• Logical Effort, by Ivan Sutherland, Bob
Sproull, and David Harris (Morgan
Kaufmann, San Francisco, 1999)
Questions and Answers

Thank You